stats: Update to match classic memory changes

25 files changed, 42440 insertions, 42429 deletions

diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
index f1835fc87..e646f5b40 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
@@ -1,110 +1,110 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.909061                       # Number of seconds simulated
-sim_ticks                                1909061460000                       # Number of ticks simulated
-final_tick                               1909061460000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.889223                       # Number of seconds simulated
+sim_ticks                                1889223246000                       # Number of ticks simulated
+final_tick                               1889223246000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  24403                       # Simulator instruction rate (inst/s)
-host_op_rate                                    24403                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              829686396                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 385840                       # Number of bytes of host memory used
-host_seconds                                  2300.94                       # Real time elapsed on the host
-sim_insts                                    56149847                       # Number of instructions simulated
-sim_ops                                      56149847                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  22780                       # Simulator instruction rate (inst/s)
+host_op_rate                                    22780                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              766551699                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 396616                       # Number of bytes of host memory used
+host_seconds                                  2464.57                       # Real time elapsed on the host
+sim_insts                                    56141873                       # Number of instructions simulated
+sim_ops                                      56141873                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst           1046656                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24857664                       # Number of bytes read from this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.inst           1047552                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24859008                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             25905280                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1046656                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1046656                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7563328                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7563328                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              16354                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             388401                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             25907520                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1047552                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1047552                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7566528                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7566528                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              16368                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             388422                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                404770                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          118177                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               118177                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               548257                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             13020882                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide               503                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13569642                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          548257                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             548257                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3961804                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3961804                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3961804                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              548257                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            13020882                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide              503                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17531446                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        404770                       # Number of read requests accepted
-system.physmem.writeReqs                       118177                       # Number of write requests accepted
-system.physmem.readBursts                      404770                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     118177                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 25897600                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      7680                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7561728                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  25905280                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7563328                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      120                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_reads::total                404805                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          118227                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               118227                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               554488                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             13158322                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide               508                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                13713318                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          554488                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             554488                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4005100                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4005100                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4005100                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              554488                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            13158322                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide              508                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               17718418                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        404805                       # Number of read requests accepted
+system.physmem.writeReqs                       118227                       # Number of write requests accepted
+system.physmem.readBursts                      404805                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     118227                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 25900800                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      6720                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7565120                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  25907520                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7566528                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      105                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               25467                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               25712                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25810                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               25757                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               25010                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               25117                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               24705                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               24573                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               25203                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               25292                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25386                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              25018                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              24535                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25541                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25794                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25730                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7820                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               25470                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25713                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25812                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               25774                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25230                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               24950                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               24793                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               24569                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               25113                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               25266                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25525                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              24857                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              24533                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              25560                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              25804                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25731                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7815                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                7678                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8070                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7721                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7116                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7111                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6703                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8068                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7736                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7326                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6953                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6780                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                6420                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7317                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6903                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7274                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7007                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7092                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7990                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7984                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7946                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7238                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6883                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7397                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6875                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7088                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8006                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7993                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7949                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           2                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1909052547000                       # Total gap between requests
+system.physmem.numWrRetry                          20                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1889214280000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  404770                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  404805                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 118177                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    402459                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      2130                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        49                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 118227                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    402482                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      2156                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        50                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
@@ -149,191 +149,193 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1514                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2905                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     7219                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5886                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6802                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6024                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5843                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6456                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     6884                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6578                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8579                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8848                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7457                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7892                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     7078                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7321                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6026                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5605                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      251                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      214                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      136                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      127                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      101                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      147                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      112                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      124                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                       91                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      145                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      109                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      124                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      208                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      184                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      121                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      102                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       82                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       88                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       88                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       89                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       35                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       35                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       28                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        8                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        64573                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      518.162823                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     316.799935                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     407.231768                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          14977     23.19%     23.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        11234     17.40%     40.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4851      7.51%     48.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3268      5.06%     53.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2473      3.83%     56.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         2033      3.15%     60.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         4174      6.46%     66.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1362      2.11%     68.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        20201     31.28%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          64573                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5294                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        76.433321                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2890.025475                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           5291     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     1475                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2724                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5709                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5854                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6607                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6640                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7607                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     8810                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7088                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     7791                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     8480                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     7557                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     6981                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7102                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6189                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5712                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5654                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5555                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      285                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      204                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      201                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      196                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      170                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      194                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      170                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      129                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      153                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      194                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      189                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      226                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      145                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      167                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      235                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      233                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      165                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      209                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      118                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      128                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      118                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      107                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      122                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      101                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       76                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       98                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       99                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       80                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       50                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       48                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        63746                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      524.988548                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     319.641335                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     414.335221                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          14725     23.10%     23.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        10901     17.10%     40.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5357      8.40%     48.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3110      4.88%     53.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2601      4.08%     57.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1701      2.67%     60.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1560      2.45%     62.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1439      2.26%     64.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        22352     35.06%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          63746                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5298                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        76.386372                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2900.765356                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           5295     99.94%     99.94% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5294                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5294                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        22.318096                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       19.102648                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       19.930772                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23            4682     88.44%     88.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31              33      0.62%     89.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39              23      0.43%     89.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47              33      0.62%     90.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55             222      4.19%     94.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63              11      0.21%     94.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71              11      0.21%     94.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79              35      0.66%     95.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87             195      3.68%     99.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-95               5      0.09%     99.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103              6      0.11%     99.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111             4      0.08%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135             5      0.09%     99.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-143             2      0.04%     99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-151             1      0.02%     99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-167             2      0.04%     99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-175             9      0.17%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183             4      0.08%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-191             2      0.04%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-215             5      0.09%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::216-223             1      0.02%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-231             1      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-263             2      0.04%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5294                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2639973000                       # Total ticks spent queuing
-system.physmem.totMemAccLat               10227160500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2023250000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6524.09                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5298                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5298                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        22.311250                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.880356                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       22.145944                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23            4698     88.67%     88.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31              33      0.62%     89.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39             235      4.44%     93.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47              22      0.42%     94.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55              12      0.23%     94.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63              14      0.26%     94.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71              10      0.19%     94.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79               4      0.08%     94.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87              30      0.57%     95.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95              15      0.28%     95.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103            179      3.38%     99.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111             1      0.02%     99.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119             1      0.02%     99.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127             1      0.02%     99.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135             6      0.11%     99.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159             2      0.04%     99.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167             4      0.08%     99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175            12      0.23%     99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183             2      0.04%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191             4      0.08%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199             2      0.04%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231             8      0.15%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-239             1      0.02%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::248-255             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5298                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2164522000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9752647000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2023500000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        5348.46                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25274.09                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          13.57                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.96                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       13.57                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.96                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  24098.46                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          13.71                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           4.00                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       13.71                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        4.01                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.18                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     362738                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     95491                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   89.64                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  80.80                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3650566.02                       # Average gap between requests
-system.physmem.pageHitRate                      87.64                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  238623840                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  130201500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1576777800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                379980720                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           124690266480                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            68013230490                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1085773099500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1280802180330                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              670.908515                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   1806022540250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     63747580000                       # Time in different power states
+system.physmem.avgWrQLen                        24.88                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     363251                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     95908                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   89.76                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  81.12                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3612043.39                       # Average gap between requests
+system.physmem.pageHitRate                      87.81                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  234556560                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  127982250                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1578025800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                380868480                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           123394455600                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            60772181625                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1080221277750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1266709348065                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              670.494357                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   1796832063750                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     63085100000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     39286273500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     29299865000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  249548040                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  136162125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1579492200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                385644240                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           124690266480                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            68685352830                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1085183526750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1280909992665                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              670.964984                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   1805042162250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     63747580000                       # Time in different power states
+system.physmem_1.actEnergy                  247363200                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  134970000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1578634200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                385099920                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           123394455600                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            61856765370                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1079269896750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1266867185040                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              670.577899                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   1795248089750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     63085100000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     40266665250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     30883852750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups                15258422                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          13121569                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            520615                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             12105776                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 4568162                       # Number of BTB hits
+system.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups                15253451                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          13119801                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            515637                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             12113296                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 4570787                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             37.735392                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                  863536                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              33630                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups         6539212                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits             544524                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses          5994688                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted       219095                       # Number of mispredicted indirect branches.
+system.cpu.branchPred.BTBHitPct             37.733636                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                  859438                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              30658                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         6570706                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits             545483                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses          6025223                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted       218035                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                      9320175                       # DTB read hits
-system.cpu.dtb.read_misses                      17427                       # DTB read misses
+system.cpu.dtb.read_hits                      9316925                       # DTB read hits
+system.cpu.dtb.read_misses                      17695                       # DTB read misses
 system.cpu.dtb.read_acv                           211                       # DTB read access violations
-system.cpu.dtb.read_accesses                   764388                       # DTB read accesses
-system.cpu.dtb.write_hits                     6394455                       # DTB write hits
-system.cpu.dtb.write_misses                      2545                       # DTB write misses
-system.cpu.dtb.write_acv                          159                       # DTB write access violations
-system.cpu.dtb.write_accesses                  298887                       # DTB write accesses
-system.cpu.dtb.data_hits                     15714630                       # DTB hits
-system.cpu.dtb.data_misses                      19972                       # DTB misses
-system.cpu.dtb.data_acv                           370                       # DTB access violations
-system.cpu.dtb.data_accesses                  1063275                       # DTB accesses
-system.cpu.itb.fetch_hits                     4019631                       # ITB hits
-system.cpu.itb.fetch_misses                      6355                       # ITB misses
-system.cpu.itb.fetch_acv                          661                       # ITB acv
-system.cpu.itb.fetch_accesses                 4025986                       # ITB accesses
+system.cpu.dtb.read_accesses                   764827                       # DTB read accesses
+system.cpu.dtb.write_hits                     6393212                       # DTB write hits
+system.cpu.dtb.write_misses                      2442                       # DTB write misses
+system.cpu.dtb.write_acv                          158                       # DTB write access violations
+system.cpu.dtb.write_accesses                  298820                       # DTB write accesses
+system.cpu.dtb.data_hits                     15710137                       # DTB hits
+system.cpu.dtb.data_misses                      20137                       # DTB misses
+system.cpu.dtb.data_acv                           369                       # DTB access violations
+system.cpu.dtb.data_accesses                  1063647                       # DTB accesses
+system.cpu.itb.fetch_hits                     4018824                       # ITB hits
+system.cpu.itb.fetch_misses                      6310                       # ITB misses
+system.cpu.itb.fetch_acv                          701                       # ITB acv
+system.cpu.itb.fetch_accesses                 4025134                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -346,85 +348,84 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numPwrStateTransitions               12756                       # Number of power state transitions
-system.cpu.pwrStateClkGateDist::samples          6378                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::mean     281603673.878959                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::stdev    439873554.784215                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::underflows            1      0.02%      0.02% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1000-5e+10         6377     99.98%    100.00% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::min_value          500                       # Distribution of time spent in the clock gated state
+system.cpu.numPwrStateTransitions               12752                       # Number of power state transitions
+system.cpu.pwrStateClkGateDist::samples          6376                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean     281746974.905897                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev    439847984.325030                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1000-5e+10         6376    100.00%    100.00% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::min_value        19000                       # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::max_value   2000000000                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::total            6378                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateResidencyTicks::ON    112993228000                       # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::CLK_GATED 1796068232000                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                        226008061                       # number of cpu cycles simulated
+system.cpu.pwrStateClkGateDist::total            6376                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateResidencyTicks::ON     92804534000                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 1796418712000                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                        185630526                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    56149847                       # Number of instructions committed
-system.cpu.committedOps                      56149847                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       2969857                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends                      6378                       # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles                   3592114868                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi                               4.025088                       # CPI: cycles per instruction
-system.cpu.ipc                               0.248442                       # IPC: instructions per cycle
-system.cpu.op_class_0::No_OpClass             3199355      5.70%      5.70% # Class of committed instruction
-system.cpu.op_class_0::IntAlu                36201883     64.47%     70.17% # Class of committed instruction
-system.cpu.op_class_0::IntMult                  60840      0.11%     70.28% # Class of committed instruction
+system.cpu.committedInsts                    56141873                       # Number of instructions committed
+system.cpu.committedOps                      56141873                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                       2958149                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                      6376                       # Number of times Execute suspended instruction fetching
+system.cpu.quiesceCycles                   3592815966                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi                               3.306454                       # CPI: cycles per instruction
+system.cpu.ipc                               0.302439                       # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass             3199005      5.70%      5.70% # Class of committed instruction
+system.cpu.op_class_0::IntAlu                36197195     64.47%     70.17% # Class of committed instruction
+system.cpu.op_class_0::IntMult                  60822      0.11%     70.28% # Class of committed instruction
 system.cpu.op_class_0::IntDiv                       0      0.00%     70.28% # Class of committed instruction
 system.cpu.op_class_0::FloatAdd                 38079      0.07%     70.35% # Class of committed instruction
 system.cpu.op_class_0::FloatCmp                     0      0.00%     70.35% # Class of committed instruction
 system.cpu.op_class_0::FloatCvt                     0      0.00%     70.35% # Class of committed instruction
 system.cpu.op_class_0::FloatMult                    0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::FloatDiv                  3636      0.01%     70.35% # Class of committed instruction
-system.cpu.op_class_0::FloatSqrt                    0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdAdd                      0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdAddAcc                   0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdAlu                      0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdCmp                      0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdCvt                      0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdMisc                     0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdMult                     0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdMultAcc                  0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdShift                    0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdSqrt                     0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMisc                0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMult                0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     70.35% # Class of committed instruction
-system.cpu.op_class_0::MemRead                9320961     16.60%     86.95% # Class of committed instruction
-system.cpu.op_class_0::MemWrite               6373595     11.35%     98.31% # Class of committed instruction
-system.cpu.op_class_0::IprAccess               951498      1.69%    100.00% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv                  3636      0.01%     70.36% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt                    0      0.00%     70.36% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd                      0      0.00%     70.36% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc                   0      0.00%     70.36% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu                      0      0.00%     70.36% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp                      0      0.00%     70.36% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt                      0      0.00%     70.36% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc                     0      0.00%     70.36% # Class of committed instruction
+system.cpu.op_class_0::SimdMult                     0      0.00%     70.36% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc                  0      0.00%     70.36% # Class of committed instruction
+system.cpu.op_class_0::SimdShift                    0      0.00%     70.36% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     70.36% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt                     0      0.00%     70.36% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     70.36% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     70.36% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     70.36% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     70.36% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     70.36% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc                0      0.00%     70.36% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult                0      0.00%     70.36% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     70.36% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     70.36% # Class of committed instruction
+system.cpu.op_class_0::MemRead                9319321     16.60%     86.95% # Class of committed instruction
+system.cpu.op_class_0::MemWrite               6372729     11.35%     98.31% # Class of committed instruction
+system.cpu.op_class_0::IprAccess               951086      1.69%    100.00% # Class of committed instruction
 system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
-system.cpu.op_class_0::total                 56149847                       # Class of committed instruction
+system.cpu.op_class_0::total                 56141873                       # Class of committed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     6378                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     211594                       # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0                    74821     40.93%     40.93% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::21                     131      0.07%     41.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22                    1907      1.04%     42.04% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  105943     57.96%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               182802                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73454     49.32%     49.32% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.inst.quiesce                     6376                       # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei                     211498                       # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0                    74792     40.94%     40.94% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::21                     131      0.07%     41.01% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::22                    1903      1.04%     42.05% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31                  105883     57.95%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               182709                       # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0                     73425     49.32%     49.32% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::21                      131      0.09%     49.40% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22                     1907      1.28%     50.68% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73454     49.32%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                148946                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1839859866500     96.38%     96.38% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                85941500      0.00%     96.38% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               711439500      0.04%     96.42% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             68403193000      3.58%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1909060440500                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981730                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_good::22                     1903      1.28%     50.68% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::31                    73425     49.32%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total                148884                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0             1835945903000     97.18%     97.18% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                85568000      0.00%     97.18% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               710063500      0.04%     97.22% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             52480708000      2.78%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1889222242500                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0                  0.981723                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.693335                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.814794                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.693454                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.814870                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -463,513 +464,514 @@ system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # nu
 system.cpu.kern.callpal::swpctx                  4173      2.17%      2.17% # number of callpals executed
 system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175631     91.22%     93.43% # number of callpals executed
-system.cpu.kern.callpal::rdps                    6810      3.54%     96.96% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175546     91.22%     93.43% # number of callpals executed
+system.cpu.kern.callpal::rdps                    6807      3.54%     96.96% # number of callpals executed
 system.cpu.kern.callpal::wrkgp                      1      0.00%     96.96% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
 system.cpu.kern.callpal::rdusp                      9      0.00%     96.97% # number of callpals executed
 system.cpu.kern.callpal::whami                      2      0.00%     96.97% # number of callpals executed
-system.cpu.kern.callpal::rti                     5132      2.67%     99.64% # number of callpals executed
+system.cpu.kern.callpal::rti                     5128      2.66%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 192526                       # number of callpals executed
-system.cpu.kern.mode_switch::kernel              5877                       # number of protection mode switches
-system.cpu.kern.mode_switch::user                1738                       # number of protection mode switches
-system.cpu.kern.mode_switch::idle                2094                       # number of protection mode switches
-system.cpu.kern.mode_good::kernel                1906                      
-system.cpu.kern.mode_good::user                  1738                      
+system.cpu.kern.callpal::total                 192434                       # number of callpals executed
+system.cpu.kern.mode_switch::kernel              5876                       # number of protection mode switches
+system.cpu.kern.mode_switch::user                1737                       # number of protection mode switches
+system.cpu.kern.mode_switch::idle                2091                       # number of protection mode switches
+system.cpu.kern.mode_good::kernel                1905                      
+system.cpu.kern.mode_good::user                  1737                      
 system.cpu.kern.mode_good::idle                   168                      
-system.cpu.kern.mode_switch_good::kernel     0.324315                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::kernel     0.324200                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.080229                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.392625                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        38921683000      2.04%      2.04% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           4598347000      0.24%      2.28% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1865540400500     97.72%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_switch_good::idle       0.080344                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      0.392622                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        36856948000      1.95%      1.95% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           4192339500      0.22%      2.17% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1848172945000     97.83%    100.00% # number of ticks spent at the given mode
 system.cpu.kern.swap_context                     4174                       # number of times the context was actually changed
-system.cpu.tickCycles                        85327235                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       140680826                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements           1394976                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.976740                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            13944378                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1395488                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              9.992474                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         124106500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.976740                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999955                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999955                       # Average percentage of cache occupancy
+system.cpu.tickCycles                        85233988                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       100396538                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements           1394263                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.980931                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            13942036                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1394775                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              9.995903                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          94238500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.980931                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999963                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999963                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          227                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          217                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          231                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          213                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          63924438                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         63924438                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data      7983946                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7983946                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      5577839                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        5577839                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       183518                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       183518                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       199043                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       199043                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      13561785                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13561785                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     13561785                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13561785                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1096703                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1096703                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       574639                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       574639                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        16549                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        16549                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1671342                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1671342                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1671342                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1671342                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  45383174000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  45383174000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  33964439500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  33964439500                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    226601500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    226601500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  79347613500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  79347613500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  79347613500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  79347613500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data      9080649                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9080649                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6152478                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6152478                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200067                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       200067                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       199043                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       199043                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15233127                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15233127                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15233127                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15233127                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.120774                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.120774                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.093400                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.093400                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.082717                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.082717                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.109718                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.109718                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.109718                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.109718                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41381.462438                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 41381.462438                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59105.698534                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 59105.698534                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13692.760892                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13692.760892                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 47475.390136                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 47475.390136                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 47475.390136                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 47475.390136                       # average overall miss latency
+system.cpu.dcache.tags.tag_accesses          63909041                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         63909041                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data      7981560                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7981560                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      5577988                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        5577988                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       183448                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       183448                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       199007                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       199007                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      13559548                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         13559548                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     13559548                       # number of overall hits
+system.cpu.dcache.overall_hits::total        13559548                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1096304                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1096304                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       573678                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       573678                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        16581                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        16581                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      1669982                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1669982                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1669982                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1669982                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  31558344500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  31558344500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  22538815500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  22538815500                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    222577500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    222577500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  54097160000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  54097160000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  54097160000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  54097160000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data      9077864                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9077864                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6151666                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6151666                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200029                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       200029                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       199007                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       199007                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     15229530                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15229530                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15229530                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15229530                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.120767                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.120767                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.093256                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.093256                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.082893                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.082893                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.109654                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.109654                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.109654                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.109654                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28786.125472                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 28786.125472                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39288.268855                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 39288.268855                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13423.647548                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13423.647548                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 32393.858137                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 32393.858137                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 32393.858137                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 32393.858137                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks       838068                       # number of writebacks
-system.cpu.dcache.writebacks::total            838068                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        21939                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        21939                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       270415                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       270415                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks       837697                       # number of writebacks
+system.cpu.dcache.writebacks::total            837697                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        21981                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        21981                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       269759                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       269759                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       292354                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       292354                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       292354                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       292354                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1074764                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1074764                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304224                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       304224                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        16546                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        16546                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1378988                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1378988                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1378988                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1378988                       # number of overall MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data       291740                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       291740                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       291740                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       291740                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1074323                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1074323                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       303919                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       303919                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        16578                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        16578                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1378242                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1378242                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1378242                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1378242                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9625                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total         9625                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16555                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total        16555                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  43721360500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  43721360500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  17277660500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  17277660500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    209790000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    209790000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  60999021000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  60999021000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  60999021000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  60999021000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1527294000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1527294000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   1527294000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   1527294000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.118358                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.118358                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049447                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049447                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.082702                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.082702                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.090526                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.090526                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.090526                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.090526                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40679.963694                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40679.963694                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56792.562388                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56792.562388                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12679.197389                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12679.197389                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44234.627858                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 44234.627858                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44234.627858                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 44234.627858                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220388.744589                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220388.744589                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92255.753549                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92255.753549                       # average overall mshr uncacheable latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements           1477492                       # number of replacements
-system.cpu.icache.tags.tagsinuse           508.111413                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            19219698                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1478003                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             13.003829                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       50147606500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   508.111413                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.992405                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.992405                       # Average percentage of cache occupancy
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9621                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total         9621                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16551                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total        16551                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  30011433500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  30011433500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11481403000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  11481403000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    205832000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    205832000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  41492836500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  41492836500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  41492836500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  41492836500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1534160500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1534160500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   1534160500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   1534160500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.118345                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.118345                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049404                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049404                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.082878                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.082878                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.090498                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.090498                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.090498                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.090498                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27935.205241                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27935.205241                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37777.838832                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37777.838832                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12415.972976                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12415.972976                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30105.624774                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 30105.624774                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30105.624774                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 30105.624774                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221379.581530                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221379.581530                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92692.918857                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92692.918857                       # average overall mshr uncacheable latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements           1476241                       # number of replacements
+system.cpu.icache.tags.tagsinuse           509.437018                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            19208652                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1476752                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             13.007365                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       33938325500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   509.437018                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.994994                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.994994                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          407                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1            7                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          401                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          22176055                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         22176055                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst     19219701                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        19219701                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      19219701                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         19219701                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     19219701                       # number of overall hits
-system.cpu.icache.overall_hits::total        19219701                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1478177                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1478177                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1478177                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1478177                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1478177                       # number of overall misses
-system.cpu.icache.overall_misses::total       1478177                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  21231255000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  21231255000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  21231255000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  21231255000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  21231255000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  21231255000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     20697878                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     20697878                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     20697878                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     20697878                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     20697878                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     20697878                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.071417                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.071417                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.071417                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.071417                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.071417                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.071417                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14363.134455                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14363.134455                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14363.134455                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14363.134455                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14363.134455                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14363.134455                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          22162507                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         22162507                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst     19208655                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        19208655                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      19208655                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         19208655                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     19208655                       # number of overall hits
+system.cpu.icache.overall_hits::total        19208655                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1476926                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1476926                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1476926                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1476926                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1476926                       # number of overall misses
+system.cpu.icache.overall_misses::total       1476926                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  20401531500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  20401531500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  20401531500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  20401531500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  20401531500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  20401531500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     20685581                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     20685581                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     20685581                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     20685581                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     20685581                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     20685581                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.071399                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.071399                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.071399                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.071399                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.071399                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.071399                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13813.509614                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13813.509614                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13813.509614                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13813.509614                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13813.509614                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13813.509614                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks      1477492                       # number of writebacks
-system.cpu.icache.writebacks::total           1477492                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1478177                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1478177                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1478177                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1478177                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1478177                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1478177                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  19753078000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  19753078000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  19753078000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  19753078000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  19753078000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  19753078000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.071417                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.071417                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.071417                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.071417                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.071417                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.071417                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13363.134455                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13363.134455                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13363.134455                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13363.134455                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13363.134455                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13363.134455                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements           339587                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65260.798092                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            5032980                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           404749                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            12.434818                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       9689078000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 54026.178970                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  5735.607676                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  5499.011446                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.824374                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.087518                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.083908                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.995801                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65162                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          226                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          888                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         5593                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2924                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55531                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994293                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         46662747                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        46662747                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackDirty_hits::writebacks       838068                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       838068                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks      1476917                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total      1476917                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data            5                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total            5                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       187586                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       187586                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1461767                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total      1461767                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       819079                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       819079                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst      1461767                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1006665                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2468432                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst      1461767                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1006665                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2468432                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data           15                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total           15                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       116651                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       116651                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        16355                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        16355                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       272198                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       272198                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst        16355                       # number of demand (read+write) misses
+system.cpu.icache.writebacks::writebacks      1476241                       # number of writebacks
+system.cpu.icache.writebacks::total           1476241                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1476926                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1476926                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1476926                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1476926                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1476926                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1476926                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  18924605500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  18924605500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  18924605500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  18924605500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  18924605500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  18924605500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.071399                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.071399                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.071399                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.071399                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.071399                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.071399                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12813.509614                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12813.509614                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12813.509614                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12813.509614                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12813.509614                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12813.509614                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.replacements           339622                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65416.328180                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            5334629                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           405144                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            13.167242                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle       6356009000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks   267.504634                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  5791.332200                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 59357.491346                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.004082                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.088369                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.905723                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.998174                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65522                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0            6                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          631                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          402                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5153                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        59330                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999786                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         46327377                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        46327377                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.WritebackDirty_hits::writebacks       837697                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total       837697                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks      1475656                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total      1475656                       # number of WritebackClean hits
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 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks        76665                       # number of writebacks
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 system.cpu.l2cache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
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-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.750000                       # mshr miss rate for UpgradeReq accesses
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-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.011065                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.278642                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.141007                       # mshr miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68833.333333                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68833.333333                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117262.869585                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117262.869585                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121266.493427                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121266.493427                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113712.505235                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113712.505235                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121266.493427                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114777.580758                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115039.488751                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121266.493427                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114777.580758                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115039.488751                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 207885.930736                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 207885.930736                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87022.017517                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87022.017517                       # average overall mshr uncacheable latency
-system.cpu.toL2Bus.snoop_filter.tot_requests      5746179                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2872664                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1960                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         1250                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1250                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data         9621                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::total         9621                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        16551                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total        16551                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       199500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       199500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7887014500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7887014500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1170547500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1170547500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  17243377000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  17243377000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1170547500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  25130391500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  26300939000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1170547500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  25130391500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  26300939000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1447515000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1447515000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   1447515000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   1447515000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.250000                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.250000                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383740                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383740                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.011084                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.011084                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.249543                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.249543                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.011084                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.278785                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.141109                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.011084                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.278785                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.141109                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        39900                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        39900                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67624.234759                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67624.234759                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71510.018938                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71510.018938                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63343.767334                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63343.767334                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71510.018938                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64627.635663                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64905.653253                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71510.018938                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64627.635663                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64905.653253                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208876.623377                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208876.623377                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87457.857531                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87457.857531                       # average overall mshr uncacheable latency
+system.cpu.toL2Bus.snoop_filter.tot_requests      5742250                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2870700                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1972                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops          998                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops          998                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadReq           6930                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2576516                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq          9625                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp         9625                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       956247                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean      1477492                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       820003                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2574859                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq          9621                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp         9621                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       914412                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      1476241                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       819473                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq           20                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp           20                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       304237                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       304237                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      1478177                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1091450                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError           24                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq        41552                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      4433791                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4219310                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8653101                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    189159296                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143002060                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          332161356                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      423210                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic               7576960                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples      3313265                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.001022                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.031947                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadExReq       303930                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       303930                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1476926                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1091030                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError           23                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq          241                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      4430038                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4217161                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8647199                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    188999168                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    142932652                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          331931820                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      340234                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic               4923264                       # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples      3228320                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.000974                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.031197                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            3309880     99.90%     99.90% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               3385      0.10%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            3225175     99.90%     99.90% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               3145      0.10%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3313265                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     5201739500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        3228320                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     5198149000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy       291883                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    2217424681                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    2215530716                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2105003991                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2103938977                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -983,12 +985,12 @@ system.disk2.dma_read_txs                           0                       # Nu
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.iobus.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
+system.iobus.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
 system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
 system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               51177                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              51177                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5106                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::WriteReq               51173                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              51173                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5098                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1006                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
@@ -997,11 +999,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        1812
 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        33110                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        33102                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  116560                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20424                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  116552                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20392                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2717                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
@@ -1010,50 +1012,50 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9060
 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        44364                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total        44332                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2705972                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              5417500                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  2705940                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy              5405000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               799000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               800000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                10500                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy                10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer6.occupancy                11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer22.occupancy              182000                       # Layer occupancy (ticks)
 system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            15625500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            14495500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer24.occupancy             2305500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy             6004000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy             5973000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy               90500                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           215719668                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           216181312                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            23485000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            23481000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer1.occupancy            41946000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
 system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.297488                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.301361                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1750571994000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.297488                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.081093                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.081093                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1731952426000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.301361                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.081335                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.081335                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
 system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
 system.iocache.tags.data_accesses              375525                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
+system.iocache.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
 system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
@@ -1062,14 +1064,14 @@ system.iocache.demand_misses::tsunami.ide        41725                       # n
 system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
 system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
 system.iocache.overall_misses::total            41725                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     21917383                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     21917383                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::tsunami.ide   5244162285                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   5244162285                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide   5266079668                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   5266079668                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide   5266079668                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   5266079668                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::tsunami.ide     21934383                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     21934383                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::tsunami.ide   4859195929                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4859195929                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide   4881130312                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   4881130312                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide   4881130312                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   4881130312                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
@@ -1086,19 +1088,19 @@ system.iocache.demand_miss_rate::tsunami.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126690.075145                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 126690.075145                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126207.217101                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 126207.217101                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 126209.219125                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 126209.219125                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 126209.219125                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 126209.219125                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126788.341040                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 126788.341040                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116942.528133                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 116942.528133                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 116983.350797                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 116983.350797                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 116983.350797                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 116983.350797                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs            18                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    4                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     4.500000                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.writebacks::writebacks           41512                       # number of writebacks
 system.iocache.writebacks::total                41512                       # number of writebacks
@@ -1110,14 +1112,14 @@ system.iocache.demand_mshr_misses::tsunami.ide        41725
 system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13267383                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     13267383                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   3164763984                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   3164763984                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide   3178031367                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   3178031367                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide   3178031367                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   3178031367                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13284383                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     13284383                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   2779181979                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2779181979                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide   2792466362                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   2792466362                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide   2792466362                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   2792466362                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1126,69 +1128,75 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76690.075145                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 76690.075145                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76163.938776                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76163.938776                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76166.120240                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 76166.120240                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76166.120240                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 76166.120240                       # average overall mshr miss latency
-system.membus.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76788.341040                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 76788.341040                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66884.433457                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66884.433457                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66925.496992                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 66925.496992                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66925.496992                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 66925.496992                       # average overall mshr miss latency
+system.membus.snoop_filter.tot_requests        827436                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests       381422                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests          409                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
+system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadReq                6930                       # Transaction distribution
-system.membus.trans_dist::ReadResp             295632                       # Transaction distribution
-system.membus.trans_dist::WriteReq               9625                       # Transaction distribution
-system.membus.trans_dist::WriteResp              9625                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       118177                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           262256                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              167                       # Transaction distribution
+system.membus.trans_dist::ReadResp             295668                       # Transaction distribution
+system.membus.trans_dist::WriteReq               9621                       # Transaction distribution
+system.membus.trans_dist::WriteResp              9621                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       118227                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           262241                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              137                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            116499                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           116499                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        288726                       # Transaction distribution
-system.membus.trans_dist::BadAddressError           24                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            116498                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           116498                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        288761                       # Transaction distribution
+system.membus.trans_dist::BadAddressError           23                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33110                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1148698                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           48                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1181856                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33102                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1148773                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           46                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1181921                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83425                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total        83425                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1265281                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44364                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30810880                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30855244                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total                1265346                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44332                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30816320                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30860652                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2657728                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2657728                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                33512972                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                33518380                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              433                       # Total snoops (count)
 system.membus.snoopTraffic                      27584                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            843934                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::samples            463499                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.001458                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.038162                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  843934    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  462823     99.85%     99.85% # Request fanout histogram
+system.membus.snoop_fanout::1                     676      0.15%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              843934                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            30445500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              463499                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            29272500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1319244966                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1319341290                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy               29500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy               31000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2159924750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2160301000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 system.membus.respLayer2.occupancy             943117                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
-system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
-system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
-system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
-system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -1220,28 +1228,28 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
-system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
-system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
-system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1909061460000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
+system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1889223246000                       # Cumulative time (in ticks) in various power states
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
index 1d7e55213..dfe837c06 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
@@ -1,125 +1,125 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.907672                       # Number of seconds simulated
-sim_ticks                                1907672102500                       # Number of ticks simulated
-final_tick                               1907672102500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.906534                       # Number of seconds simulated
+sim_ticks                                1906533530000                       # Number of ticks simulated
+final_tick                               1906533530000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 159928                       # Simulator instruction rate (inst/s)
-host_op_rate                                   159928                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5430263290                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 337712                       # Number of bytes of host memory used
-host_seconds                                   351.30                       # Real time elapsed on the host
-sim_insts                                    56183395                       # Number of instructions simulated
-sim_ops                                      56183395                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 134861                       # Simulator instruction rate (inst/s)
+host_op_rate                                   134861                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4533949866                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 343876                       # Number of bytes of host memory used
+host_seconds                                   420.50                       # Real time elapsed on the host
+sim_insts                                    56709432                       # Number of instructions simulated
+sim_ops                                      56709432                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.inst           861632                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         24651584                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           117952                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           582656                       # Number of bytes read from this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu0.inst           896192                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         24492096                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst            81664                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           812544                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             26214784                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       861632                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       117952                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          979584                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7845056                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7845056                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst             13463                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            385181                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              1843                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data              9104                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             26283456                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       896192                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst        81664                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          977856                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7904832                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7904832                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst             14003                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            382689                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              1276                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             12696                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                409606                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          122579                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               122579                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              451667                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            12922338                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               61830                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              305428                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide               503                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13741766                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         451667                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          61830                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             513497                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4112371                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4112371                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4112371                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             451667                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           12922338                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              61830                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             305428                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide              503                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17854137                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        409606                       # Number of read requests accepted
-system.physmem.writeReqs                       122579                       # Number of write requests accepted
-system.physmem.readBursts                      409606                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     122579                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 26206336                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      8448                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7843200                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  26214784                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7845056                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      132                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_reads::total                410679                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          123513                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               123513                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              470064                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            12846402                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               42834                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              426189                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide               504                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                13785992                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         470064                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          42834                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             512897                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4146180                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4146180                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4146180                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             470064                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           12846402                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              42834                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             426189                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide              504                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               17932172                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        410679                       # Number of read requests accepted
+system.physmem.writeReqs                       123513                       # Number of write requests accepted
+system.physmem.readBursts                      410679                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     123513                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 26276352                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      7104                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7903488                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  26283456                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7904832                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      111                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               26087                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               25986                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25681                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               25351                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               24681                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               24934                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               25045                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               25140                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               25540                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               26037                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25956                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              25606                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              26142                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25795                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25668                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25825                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8182                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8217                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8055                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7694                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7332                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7389                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7497                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6907                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7336                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7821                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7658                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7295                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7753                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7589                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7825                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               8000                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               26110                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               26073                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25765                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               25777                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25805                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               25558                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               25453                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               25268                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               25514                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               25670                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25901                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              25385                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              25810                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              25833                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              25046                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25600                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8438                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                8395                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                7934                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7573                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7567                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7501                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7444                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7061                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7349                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7703                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7693                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7415                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7960                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8226                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7426                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7807                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          17                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1907667754500                       # Total gap between requests
+system.physmem.numWrRetry                          24                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1906529083500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  409606                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  410679                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 122579                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    317389                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     37968                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     29326                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     24690                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        78                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                        13                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 123513                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    317651                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     38167                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     29690                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     24938                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        89                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                        15                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                         6                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                         5                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
@@ -159,193 +159,209 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1621                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2918                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     3481                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4567                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6159                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6901                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7938                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     9224                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7563                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     8289                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8928                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8280                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7498                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7852                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     8073                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6315                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6568                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6026                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      294                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      221                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      134                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      137                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      111                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      132                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      129                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                       97                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      121                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      226                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      168                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      181                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      182                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      204                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      187                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      201                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      146                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      173                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      163                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      175                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       95                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       89                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       78                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       88                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       31                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       37                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        64695                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      526.308617                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     319.463735                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     416.737705                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          14846     22.95%     22.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        11278     17.43%     40.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5774      8.92%     49.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2666      4.12%     53.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2483      3.84%     57.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1468      2.27%     59.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1658      2.56%     62.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1459      2.26%     64.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        23063     35.65%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          64695                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5527                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        74.082685                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2821.240872                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           5524     99.95%     99.95% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     1595                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2892                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     3447                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4536                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6150                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6970                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     8000                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     9213                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7568                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     8228                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     9103                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     8348                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7491                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7850                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     8309                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6391                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6719                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6204                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      301                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      188                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      199                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      178                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      121                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      116                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      109                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      149                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      133                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      136                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      164                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      201                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      172                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      159                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      187                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      211                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      171                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      206                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      118                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      130                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      140                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      137                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      137                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      119                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      101                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      136                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                      124                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       81                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       65                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       38                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       57                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        64501                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      529.911784                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     323.379229                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     416.310744                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          14472     22.44%     22.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        11319     17.55%     39.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5673      8.80%     48.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2735      4.24%     53.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2521      3.91%     56.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1561      2.42%     59.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1592      2.47%     61.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1422      2.20%     64.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        23206     35.98%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          64501                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5582                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        73.544966                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2807.309852                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           5579     99.95%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5527                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5527                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        22.172969                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.909622                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       21.446069                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23            4919     89.00%     89.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31              36      0.65%     89.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39             243      4.40%     94.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47              19      0.34%     94.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55               5      0.09%     94.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63              15      0.27%     94.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71              14      0.25%     95.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79               2      0.04%     95.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87              36      0.65%     95.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-95              13      0.24%     95.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103            182      3.29%     99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111             3      0.05%     99.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-119             2      0.04%     99.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-127             2      0.04%     99.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135             4      0.07%     99.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-159             3      0.05%     99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-167             5      0.09%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-175             4      0.07%     99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183             1      0.02%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-191             2      0.04%     99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-199             2      0.04%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-207             1      0.02%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-215             1      0.02%     99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-231            12      0.22%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-263             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5527                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     3957301251                       # Total ticks spent queuing
-system.physmem.totMemAccLat               11634938751                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2047370000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9664.35                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5582                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5582                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        22.123253                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.862531                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       21.587113                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            4829     86.51%     86.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             142      2.54%     89.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              15      0.27%     89.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              29      0.52%     89.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             220      3.94%     93.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              21      0.38%     94.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              13      0.23%     94.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               6      0.11%     94.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51               3      0.05%     94.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               8      0.14%     94.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               8      0.14%     94.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               7      0.13%     94.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67               7      0.13%     95.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               3      0.05%     95.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               1      0.02%     95.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               1      0.02%     95.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              21      0.38%     95.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               2      0.04%     95.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91              16      0.29%     95.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               1      0.02%     95.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99             179      3.21%     99.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             2      0.04%     99.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             1      0.02%     99.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             3      0.05%     99.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             2      0.04%     99.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             1      0.02%     99.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.02%     99.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             5      0.09%     99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.02%     99.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             1      0.02%     99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             1      0.02%     99.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.02%     99.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             2      0.04%     99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             6      0.11%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-187             3      0.05%     99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             1      0.02%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             2      0.04%     99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::196-199             2      0.04%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::212-215             1      0.02%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-219             1      0.02%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227            13      0.23%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5582                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     4047296750                       # Total ticks spent queuing
+system.physmem.totMemAccLat               11745446750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2052840000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        9857.80                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28414.35                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          13.74                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           4.11                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       13.74                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        4.11                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  28607.80                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          13.78                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           4.15                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       13.79                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        4.15                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         2.18                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.78                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     368811                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     98518                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   90.07                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  80.37                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3584595.12                       # Average gap between requests
-system.physmem.pageHitRate                      87.84                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  244392120                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  133348875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1582659000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                397049040                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           124599742800                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            57755737350                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1093939329000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1278652258185                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              670.268952                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   1819699135250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     63701300000                       # Time in different power states
+system.physmem.avgRdQLen                         2.26                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        26.95                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     369870                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     99689                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   90.09                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  80.71                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3568995.95                       # Average gap between requests
+system.physmem.pageHitRate                      87.92                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  245828520                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  134132625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1605310200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                401196240                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           124525493040                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            58054066515                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1092995561250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1277961588390                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              670.306343                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   1818124535500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     63663080000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     24270006000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     24745773250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  244702080                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  133518000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1611238200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                397074960                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           124599742800                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            57480963435                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1094180367000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1278647606475                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              670.266509                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   1820097449251                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     63701300000                       # Time in different power states
+system.physmem_1.actEnergy                  241799040                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  131934000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1597120200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                399031920                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           124525493040                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            57215830500                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1093730864250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1277842072950                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              670.243651                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   1819353589250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     63663080000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     23871705749                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     23516733250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.cpu0.branchPred.lookups               18486901                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         15748793                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           541835                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            11639433                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits                5170762                       # Number of BTB hits
+system.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.cpu0.branchPred.lookups               16961800                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         14485891                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           473040                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            10754552                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits                4802971                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            44.424518                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                1045004                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             41208                       # Number of incorrect RAS predictions.
-system.cpu0.branchPred.indirectLookups        5538250                       # Number of indirect predictor lookups.
-system.cpu0.branchPred.indirectHits            525213                       # Number of indirect target hits.
-system.cpu0.branchPred.indirectMisses         5013037                       # Number of indirect misses.
-system.cpu0.branchPredindirectMispredicted       248456                       # Number of mispredicted indirect branches.
+system.cpu0.branchPred.BTBHitPct            44.659889                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                 946597                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             35405                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.indirectLookups        5065158                       # Number of indirect predictor lookups.
+system.cpu0.branchPred.indirectHits            501808                       # Number of indirect target hits.
+system.cpu0.branchPred.indirectMisses         4563350                       # Number of indirect misses.
+system.cpu0.branchPredindirectMispredicted       210940                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dtb.fetch_hits                          0                       # ITB hits
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                    10388247                       # DTB read hits
-system.cpu0.dtb.read_misses                     39745                       # DTB read misses
+system.cpu0.dtb.read_hits                     9542415                       # DTB read hits
+system.cpu0.dtb.read_misses                     34570                       # DTB read misses
 system.cpu0.dtb.read_acv                          614                       # DTB read access violations
-system.cpu0.dtb.read_accesses                  666259                       # DTB read accesses
-system.cpu0.dtb.write_hits                    6304219                       # DTB write hits
-system.cpu0.dtb.write_misses                     9494                       # DTB write misses
-system.cpu0.dtb.write_acv                         419                       # DTB write access violations
-system.cpu0.dtb.write_accesses                 221498                       # DTB write accesses
-system.cpu0.dtb.data_hits                    16692466                       # DTB hits
-system.cpu0.dtb.data_misses                     49239                       # DTB misses
-system.cpu0.dtb.data_acv                         1033                       # DTB access violations
-system.cpu0.dtb.data_accesses                  887757                       # DTB accesses
-system.cpu0.itb.fetch_hits                    1498511                       # ITB hits
-system.cpu0.itb.fetch_misses                     7842                       # ITB misses
-system.cpu0.itb.fetch_acv                         715                       # ITB acv
-system.cpu0.itb.fetch_accesses                1506353                       # ITB accesses
+system.cpu0.dtb.read_accesses                  570502                       # DTB read accesses
+system.cpu0.dtb.write_hits                    5776455                       # DTB write hits
+system.cpu0.dtb.write_misses                     8473                       # DTB write misses
+system.cpu0.dtb.write_acv                         390                       # DTB write access violations
+system.cpu0.dtb.write_accesses                 186760                       # DTB write accesses
+system.cpu0.dtb.data_hits                    15318870                       # DTB hits
+system.cpu0.dtb.data_misses                     43043                       # DTB misses
+system.cpu0.dtb.data_acv                         1004                       # DTB access violations
+system.cpu0.dtb.data_accesses                  757262                       # DTB accesses
+system.cpu0.itb.fetch_hits                    1323023                       # ITB hits
+system.cpu0.itb.fetch_misses                     7096                       # ITB misses
+system.cpu0.itb.fetch_acv                         610                       # ITB acv
+system.cpu0.itb.fetch_accesses                1330119                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -358,606 +374,606 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numPwrStateTransitions              12731                       # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples         6366                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean    290215354.618913                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev   443182270.048279                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::underflows            4      0.06%      0.06% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10         6362     99.94%    100.00% # Distribution of time spent in the clock gated state
+system.cpu0.numPwrStateTransitions              13007                       # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples         6504                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean    284289977.091175                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev   440390387.503353                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows            1      0.02%      0.02% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10         6503     99.98%    100.00% # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::max_value   2000000000                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total           6366                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON    60161154996                       # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 1847510947504                       # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles                       120328672                       # number of cpu cycles simulated
+system.cpu0.pwrStateClkGateDist::total           6504                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON    57511518999                       # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849022011001                       # Cumulative time (in ticks) in various power states
+system.cpu0.numCycles                       115029541                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          28758768                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                      80605672                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                   18486901                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches           6740979                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                     84470777                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                1538724                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                        99                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles               28344                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles       156668                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       425628                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles          282                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                  9251036                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               365043                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.icacheStallCycles          26105514                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                      74391279                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                   16961800                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches           6251376                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                     82220028                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                1360432                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                        20                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles               28534                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles       140847                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       424678                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles          286                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                  8564382                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               320281                       # Number of outstanding Icache misses that were squashed
 system.cpu0.fetch.ItlbSquashes                      1                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         114609928                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.703304                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.035053                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::samples         109600123                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.678752                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.000671                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                99708886     87.00%     87.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                  974143      0.85%     87.85% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                 1998972      1.74%     89.59% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                  868407      0.76%     90.35% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                 2758687      2.41%     92.76% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                  641235      0.56%     93.32% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                  755467      0.66%     93.98% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                  978409      0.85%     94.83% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                 5925722      5.17%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                95795479     87.40%     87.40% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                  897061      0.82%     88.22% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                 1880834      1.72%     89.94% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                  785387      0.72%     90.66% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                 2637004      2.41%     93.06% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                  588358      0.54%     93.60% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                  697546      0.64%     94.23% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                  846325      0.77%     95.01% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                 5472129      4.99%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           114609928                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.153637                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.669879                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                23115734                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles             79187494                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                  9649471                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles              1920435                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles                736793                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved              689182                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred                33223                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts              69733339                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts               101960                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles                736793                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                24053074                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               52045501                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      18448869                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                 10567955                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles              8757734                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts              66954427                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents               200777                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents               2040075                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                234878                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents               4698433                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands           45085797                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups             80572701                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups        80419250                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups           143477                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             36303569                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                 8782228                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts           1592248                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts        261178                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 13101083                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads            10872978                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores            6724173                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1603556                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         1060240                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                  59089633                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            2074933                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                 57153011                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued            84826                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined       10861661                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined      4738821                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved       1447538                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    114609928                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.498674                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.243633                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           109600123                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.147456                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.646715                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                20981522                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles             77286866                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                  8861450                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles              1818601                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles                651683                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved              621495                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred                29133                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts              64563390                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts                88112                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles                651683                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                21851256                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               51776932                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      17156942                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                  9742291                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles              8421017                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts              62086646                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents               197170                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents               2004328                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                218757                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents               4545100                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands           41879351                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups             74952395                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups        74819888                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups           123702                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             34134806                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                 7744545                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts           1440211                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts        234687                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 12404512                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads             9945616                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores            6151141                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1474462                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores          959878                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                  54892526                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1879962                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                 53219239                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued            73531                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined        9606336                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined      4159079                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved       1308684                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    109600123                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.485576                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.229164                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0           91405720     79.75%     79.75% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1            9883367      8.62%     88.38% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2            4163005      3.63%     92.01% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            2977529      2.60%     94.61% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            3083312      2.69%     97.30% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5            1549770      1.35%     98.65% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6            1029487      0.90%     99.55% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7             389877      0.34%     99.89% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8             127861      0.11%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0           87964311     80.26%     80.26% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1            9240201      8.43%     88.69% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2            3866881      3.53%     92.22% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            2775272      2.53%     94.75% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            2892547      2.64%     97.39% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5            1421694      1.30%     98.69% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6             953270      0.87%     99.56% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7             366394      0.33%     99.89% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8             119553      0.11%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      114609928                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      109600123                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                 177461     15.95%     15.95% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     0      0.00%     15.95% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     15.95% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     15.95% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     15.95% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     15.95% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     15.95% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     15.95% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     15.95% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     15.95% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     15.95% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     15.95% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     15.95% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     15.95% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     15.95% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     15.95% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     15.95% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     15.95% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     15.95% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     15.95% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     15.95% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     15.95% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     15.95% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     15.95% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     15.95% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     15.95% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     15.95% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     15.95% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     15.95% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                577417     51.89%     67.83% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite               357940     32.17%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                 170160     16.71%     16.71% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     1      0.00%     16.71% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     16.71% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     16.71% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     16.71% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     16.71% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     16.71% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     16.71% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     16.71% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     16.71% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     16.71% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     16.71% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     16.71% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     16.71% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     16.71% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     16.71% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     16.71% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     16.71% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     16.71% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     16.71% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     16.71% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     16.71% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     16.71% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     16.71% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     16.71% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     16.71% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     16.71% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     16.71% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     16.71% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                520319     51.11%     67.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite               327644     32.18%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass             3316      0.01%      0.01% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             38903396     68.07%     68.07% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               60002      0.10%     68.18% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.18% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd              28431      0.05%     68.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv               1656      0.00%     68.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead            10881663     19.04%     87.27% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite            6404122     11.21%     98.48% # Type of FU issued
-system.cpu0.iq.FU_type_0::IprAccess            870425      1.52%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass             2537      0.00%      0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             36500931     68.59%     68.59% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               56437      0.11%     68.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd              25510      0.05%     68.74% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.74% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.74% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.74% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv               1267      0.00%     68.75% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.75% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.75% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.75% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.75% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.75% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.75% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.75% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.75% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.75% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.75% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.75% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.75% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.75% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.75% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.75% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.75% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.75% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.75% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.75% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.75% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.75% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead             9976302     18.75%     87.49% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite            5867670     11.03%     98.52% # Type of FU issued
+system.cpu0.iq.FU_type_0::IprAccess            788585      1.48%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total              57153011                       # Type of FU issued
-system.cpu0.iq.rate                          0.474974                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                    1112818                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.019471                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         229452003                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes         71724793                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     55161872                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads             661591                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes            320309                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       299753                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses              57905331                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                 357182                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          649944                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total              53219239                       # Type of FU issued
+system.cpu0.iq.rate                          0.462657                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                    1018124                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.019131                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         216556534                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes         66119650                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     51474452                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads             573722                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes            277081                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       260310                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses              53925009                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                 309817                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          608784                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      2311061                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         3974                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        19354                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores       772397                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      1996070                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         4265                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        18313                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores       688901                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads        18463                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked       400325                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads        18448                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked       363376                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles                736793                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles               48901711                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles               778245                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts           65010536                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts           175759                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts             10872978                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts             6724173                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts           1839088                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 42617                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents               533932                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         19354                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        209386                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       582195                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              791581                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             56370431                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts             10457447                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           782580                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles                651683                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles               48679015                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles               759858                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts           60350483                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts           162315                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts              9945616                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts             6151141                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts           1664805                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 40490                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents               518912                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         18313                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        186521                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       513145                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              699666                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             52530190                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts              9602772                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           689049                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                      3845970                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    16790279                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                 8937296                       # Number of branches executed
-system.cpu0.iew.exec_stores                   6332832                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.468470                       # Inst execution rate
-system.cpu0.iew.wb_sent                      55678100                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     55461625                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 28192926                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 39039520                       # num instructions consuming a value
-system.cpu0.iew.wb_rate                      0.460918                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.722164                       # average fanout of values written-back
-system.cpu0.commit.commitSquashedInsts       11448425                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls         627395                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           706831                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    112623597                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.474128                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.409611                       # Number of insts commited each cycle
+system.cpu0.iew.exec_nop                      3577995                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    15404618                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                 8349417                       # Number of branches executed
+system.cpu0.iew.exec_stores                   5801846                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.456667                       # Inst execution rate
+system.cpu0.iew.wb_sent                      51922146                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     51734762                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 26504573                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 36648490                       # num instructions consuming a value
+system.cpu0.iew.wb_rate                      0.449752                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.723211                       # average fanout of values written-back
+system.cpu0.commit.commitSquashedInsts       10116425                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls         571278                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           623596                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    107842796                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.464314                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.394503                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0     93749029     83.24%     83.24% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1      7554104      6.71%     89.95% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      4011836      3.56%     93.51% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      2145505      1.91%     95.42% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4      1663134      1.48%     96.89% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5       616876      0.55%     97.44% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6       455080      0.40%     97.84% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       507934      0.45%     98.30% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1920099      1.70%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0     90117032     83.56%     83.56% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1      7061240      6.55%     90.11% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      3809100      3.53%     93.64% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      2021336      1.87%     95.52% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      1578999      1.46%     96.98% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5       575276      0.53%     97.52% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6       421394      0.39%     97.91% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       458654      0.43%     98.33% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1799765      1.67%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    112623597                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            53398017                       # Number of instructions committed
-system.cpu0.commit.committedOps              53398017                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    107842796                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            50072886                       # Number of instructions committed
+system.cpu0.commit.committedOps              50072886                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      14513693                       # Number of memory references committed
-system.cpu0.commit.loads                      8561917                       # Number of loads committed
-system.cpu0.commit.membars                     214579                       # Number of memory barriers committed
-system.cpu0.commit.branches                   8068022                       # Number of branches committed
-system.cpu0.commit.fp_insts                    288973                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 49410509                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls              696168                       # Number of function calls committed.
-system.cpu0.commit.op_class_0::No_OpClass      3098426      5.80%      5.80% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu        34606705     64.81%     70.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult          58588      0.11%     70.72% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv               0      0.00%     70.72% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd         27960      0.05%     70.77% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     70.77% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     70.77% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     70.77% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv          1656      0.00%     70.78% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     70.78% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     70.78% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     70.78% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     70.78% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     70.78% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     70.78% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     70.78% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     70.78% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     70.78% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     70.78% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     70.78% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     70.78% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     70.78% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     70.78% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     70.78% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     70.78% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     70.78% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     70.78% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     70.78% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     70.78% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     70.78% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead        8776496     16.44%     87.21% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite       5957761     11.16%     98.37% # Class of committed instruction
-system.cpu0.commit.op_class_0::IprAccess       870425      1.63%    100.00% # Class of committed instruction
+system.cpu0.commit.refs                      13411786                       # Number of memory references committed
+system.cpu0.commit.loads                      7949546                       # Number of loads committed
+system.cpu0.commit.membars                     194670                       # Number of memory barriers committed
+system.cpu0.commit.branches                   7579863                       # Number of branches committed
+system.cpu0.commit.fp_insts                    251347                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                 46348996                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls              640938                       # Number of function calls committed.
+system.cpu0.commit.op_class_0::No_OpClass      2909270      5.81%      5.81% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu        32681197     65.27%     71.08% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult          55117      0.11%     71.19% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv               0      0.00%     71.19% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd         25038      0.05%     71.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     71.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     71.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     71.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv          1267      0.00%     71.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     71.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     71.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     71.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     71.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     71.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     71.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     71.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     71.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     71.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     71.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     71.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     71.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     71.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     71.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     71.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     71.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     71.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     71.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     71.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     71.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     71.24% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead        8144216     16.26%     87.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite       5468196     10.92%     98.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::IprAccess       788585      1.57%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total         53398017                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events              1920099                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                   175358628                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  131681344                       # The number of ROB writes
-system.cpu0.timesIdled                         541437                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                        5718744                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  3694399415                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   50302904                       # Number of Instructions Simulated
-system.cpu0.committedOps                     50302904                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              2.392082                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        2.392082                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.418046                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.418046                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                73576817                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               40321383                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                   142542                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                  152983                       # number of floating regfile writes
-system.cpu0.misc_regfile_reads                1859375                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                873240                       # number of misc regfile writes
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements          1336574                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          505.845930                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           11809421                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1336976                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs             8.832934                       # Average number of references to valid blocks.
+system.cpu0.commit.op_class_0::total         50072886                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events              1799765                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                   166055766                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  122136916                       # The number of ROB writes
+system.cpu0.timesIdled                         488999                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                        5429418                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  3697477415                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   47166151                       # Number of Instructions Simulated
+system.cpu0.committedOps                     47166151                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              2.438816                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        2.438816                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.410035                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.410035                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                68768616                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               37693548                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                   122704                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                  131478                       # number of floating regfile writes
+system.cpu0.misc_regfile_reads                1676808                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                792469                       # number of misc regfile writes
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.tags.replacements          1260860                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          506.428743                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           10814422                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1261290                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs             8.574096                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         26822500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   505.845930                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.987980                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.987980                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          402                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2          399                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024     0.785156                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         62763513                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        62763513                       # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data      7501117                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        7501117                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3904271                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       3904271                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       200075                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       200075                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       202804                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       202804                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     11405388                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        11405388                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     11405388                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       11405388                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      1695209                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1695209                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1829361                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1829361                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        22067                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        22067                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data          927                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total          927                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      3524570                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       3524570                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      3524570                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      3524570                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  40549578500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  40549578500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  77276130293                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  77276130293                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    333041000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    333041000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data      6753500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total      6753500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 117825708793                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 117825708793                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 117825708793                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 117825708793                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      9196326                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      9196326                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      5733632                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      5733632                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       222142                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       222142                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       203731                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       203731                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     14929958                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     14929958                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     14929958                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     14929958                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.184335                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.184335                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.319058                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.319058                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.099337                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.099337                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.004550                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.004550                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.236074                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.236074                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.236074                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.236074                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23920.105721                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 23920.105721                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42242.143728                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 42242.143728                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15092.264467                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15092.264467                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  7285.329018                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  7285.329018                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33429.810954                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 33429.810954                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33429.810954                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 33429.810954                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs      4313991                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets         8795                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs           119168                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets            132                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    36.200918                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    66.628788                       # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks       791920                       # number of writebacks
-system.cpu0.dcache.writebacks::total           791920                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       639925                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       639925                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1556053                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1556053                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         6507                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total         6507                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      2195978                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      2195978                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      2195978                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      2195978                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      1055284                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      1055284                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       273308                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       273308                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        15560                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total        15560                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data          926                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total          926                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      1328592                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      1328592                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      1328592                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      1328592                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data         7032                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total         7032                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data         9755                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total         9755                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        16787                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        16787                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  30284931500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  30284931500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  12180596213                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  12180596213                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    192236000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    192236000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data      5827500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      5827500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  42465527713                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  42465527713                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  42465527713                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  42465527713                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1566422000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1566422000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   1566422000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1566422000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.114751                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.114751                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.047668                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.047668                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.070045                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.070045                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.004545                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.004545                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.088988                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.088988                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.088988                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.088988                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28698.370770                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28698.370770                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44567.287503                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44567.287503                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12354.498715                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12354.498715                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  6293.196544                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  6293.196544                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31962.805521                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31962.805521                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31962.805521                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31962.805521                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222756.257110                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222756.257110                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93311.610175                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93311.610175                       # average overall mshr uncacheable latency
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements          1014611                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          509.545427                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs            8173897                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1015123                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs             8.052125                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      28452447500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   509.545427                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.995206                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.995206                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          495                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3           17                       # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         10266395                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        10266395                       # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst      8173897                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total        8173897                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst      8173897                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total         8173897                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst      8173897                       # number of overall hits
-system.cpu0.icache.overall_hits::total        8173897                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      1077136                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1077136                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      1077136                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1077136                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      1077136                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1077136                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  15255278493                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  15255278493                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  15255278493                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  15255278493                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  15255278493                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  15255278493                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst      9251033                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total      9251033                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst      9251033                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total      9251033                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst      9251033                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total      9251033                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.116434                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.116434                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.116434                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.116434                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.116434                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.116434                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14162.815553                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 14162.815553                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14162.815553                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 14162.815553                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14162.815553                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 14162.815553                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         5826                       # number of cycles access was blocked
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   506.428743                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.989119                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.989119                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          430                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2          412                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::3           18                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024     0.839844                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses         57625075                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        57625075                       # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.ReadReq_hits::cpu0.data      6881291                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        6881291                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3568585                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       3568585                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       177059                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       177059                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       182551                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       182551                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     10449876                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        10449876                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     10449876                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       10449876                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      1562512                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1562512                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1693924                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1693924                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        20209                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        20209                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data         2828                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         2828                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      3256436                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       3256436                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      3256436                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      3256436                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  38980676000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  38980676000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  74553561151                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  74553561151                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    291267500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    291267500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     15945500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total     15945500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 113534237151                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 113534237151                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 113534237151                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 113534237151                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      8443803                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      8443803                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      5262509                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      5262509                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       197268                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       197268                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       185379                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       185379                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     13706312                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     13706312                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     13706312                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     13706312                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.185048                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.185048                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.321885                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.321885                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.102444                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.102444                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.015255                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.015255                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.237587                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.237587                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.237587                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.237587                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24947.441044                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 24947.441044                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44012.341257                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 44012.341257                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14412.761641                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14412.761641                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  5638.437058                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  5638.437058                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34864.568857                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 34864.568857                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34864.568857                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 34864.568857                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs      4192146                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets         2471                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs           109181                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets             83                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    38.396296                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    29.771084                       # average number of cycles each access was blocked
+system.cpu0.dcache.writebacks::writebacks       743371                       # number of writebacks
+system.cpu0.dcache.writebacks::total           743371                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       555767                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       555767                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1440437                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1440437                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         5460                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total         5460                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1996204                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1996204                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1996204                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1996204                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      1006745                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      1006745                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       253487                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       253487                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        14749                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total        14749                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         2828                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total         2828                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      1260232                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      1260232                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      1260232                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      1260232                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data         7013                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total         7013                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        10003                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        10003                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        17016                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        17016                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  29619600000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  29619600000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  11703772725                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  11703772725                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    170858500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    170858500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     13117500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     13117500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  41323372725                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  41323372725                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  41323372725                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  41323372725                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1563340000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1563340000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   1563340000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1563340000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.119229                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.119229                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.048168                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.048168                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.074766                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.074766                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.015255                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.015255                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.091945                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.091945                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.091945                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.091945                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29421.154314                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29421.154314                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46171.096447                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46171.096447                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11584.412503                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11584.412503                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  4638.437058                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  4638.437058                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32790.289982                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32790.289982                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32790.289982                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32790.289982                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222920.290888                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222920.290888                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 91874.706159                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 91874.706159                       # average overall mshr uncacheable latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.tags.replacements           908505                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          509.512047                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs            7601055                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           909016                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs             8.361850                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      28452405500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   509.512047                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.995141                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.995141                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          498                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3           13                       # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses          9473645                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses         9473645                       # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.ReadReq_hits::cpu0.inst      7601055                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total        7601055                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst      7601055                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total         7601055                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst      7601055                       # number of overall hits
+system.cpu0.icache.overall_hits::total        7601055                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       963326                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       963326                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       963326                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        963326                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       963326                       # number of overall misses
+system.cpu0.icache.overall_misses::total       963326                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  13819823495                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  13819823495                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  13819823495                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  13819823495                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  13819823495                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  13819823495                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst      8564381                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total      8564381                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst      8564381                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total      8564381                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst      8564381                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total      8564381                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.112481                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.112481                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.112481                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.112481                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.112481                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.112481                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14345.946746                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 14345.946746                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14345.946746                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 14345.946746                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14345.946746                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 14345.946746                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         6257                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              231                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              203                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    25.220779                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    30.822660                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks      1014611                       # number of writebacks
-system.cpu0.icache.writebacks::total          1014611                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        61774                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        61774                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        61774                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        61774                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        61774                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        61774                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1015362                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1015362                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      1015362                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1015362                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      1015362                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1015362                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  13566878495                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  13566878495                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  13566878495                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  13566878495                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  13566878495                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  13566878495                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.109757                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.109757                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.109757                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.109757                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.109757                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.109757                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13361.617330                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13361.617330                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13361.617330                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 13361.617330                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13361.617330                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 13361.617330                       # average overall mshr miss latency
-system.cpu1.branchPred.lookups                2716012                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted          2349135                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect            64284                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups             1339574                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                 486642                       # Number of BTB hits
+system.cpu0.icache.writebacks::writebacks       908505                       # number of writebacks
+system.cpu0.icache.writebacks::total           908505                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        54062                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        54062                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        54062                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        54062                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        54062                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        54062                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       909264                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       909264                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       909264                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       909264                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       909264                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       909264                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12278033496                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  12278033496                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12278033496                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  12278033496                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12278033496                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  12278033496                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.106168                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.106168                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.106168                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.106168                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.106168                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.106168                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13503.265824                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13503.265824                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13503.265824                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 13503.265824                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13503.265824                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 13503.265824                       # average overall mshr miss latency
+system.cpu1.branchPred.lookups                4250134                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted          3659200                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           108723                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups             2354380                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                 849662                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            36.328116                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                 131116                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect              4300                       # Number of incorrect RAS predictions.
-system.cpu1.branchPred.indirectLookups         740387                       # Number of indirect predictor lookups.
-system.cpu1.branchPred.indirectHits            107863                       # Number of indirect target hits.
-system.cpu1.branchPred.indirectMisses          632524                       # Number of indirect misses.
-system.cpu1.branchPredindirectMispredicted        18463                       # Number of mispredicted indirect branches.
+system.cpu1.branchPred.BTBHitPct            36.088567                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                 217108                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect              8204                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.indirectLookups        1308734                       # Number of indirect predictor lookups.
+system.cpu1.branchPred.indirectHits            157441                       # Number of indirect target hits.
+system.cpu1.branchPred.indirectMisses         1151293                       # Number of indirect misses.
+system.cpu1.branchPredindirectMispredicted        37897                       # Number of mispredicted indirect branches.
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     1491854                       # DTB read hits
-system.cpu1.dtb.read_misses                     11707                       # DTB read misses
-system.cpu1.dtb.read_acv                           49                       # DTB read access violations
-system.cpu1.dtb.read_accesses                  336889                       # DTB read accesses
-system.cpu1.dtb.write_hits                     824931                       # DTB write hits
-system.cpu1.dtb.write_misses                     2806                       # DTB write misses
-system.cpu1.dtb.write_acv                          46                       # DTB write access violations
-system.cpu1.dtb.write_accesses                 126281                       # DTB write accesses
-system.cpu1.dtb.data_hits                     2316785                       # DTB hits
-system.cpu1.dtb.data_misses                     14513                       # DTB misses
-system.cpu1.dtb.data_acv                           95                       # DTB access violations
-system.cpu1.dtb.data_accesses                  463170                       # DTB accesses
-system.cpu1.itb.fetch_hits                     477856                       # ITB hits
-system.cpu1.itb.fetch_misses                     2662                       # ITB misses
-system.cpu1.itb.fetch_acv                          96                       # ITB acv
-system.cpu1.itb.fetch_accesses                 480518                       # ITB accesses
+system.cpu1.dtb.read_hits                     2331871                       # DTB read hits
+system.cpu1.dtb.read_misses                     15400                       # DTB read misses
+system.cpu1.dtb.read_acv                           73                       # DTB read access violations
+system.cpu1.dtb.read_accesses                  429786                       # DTB read accesses
+system.cpu1.dtb.write_hits                    1381774                       # DTB write hits
+system.cpu1.dtb.write_misses                     3743                       # DTB write misses
+system.cpu1.dtb.write_acv                          71                       # DTB write access violations
+system.cpu1.dtb.write_accesses                 161427                       # DTB write accesses
+system.cpu1.dtb.data_hits                     3713645                       # DTB hits
+system.cpu1.dtb.data_misses                     19143                       # DTB misses
+system.cpu1.dtb.data_acv                          144                       # DTB access violations
+system.cpu1.dtb.data_accesses                  591213                       # DTB accesses
+system.cpu1.itb.fetch_hits                     662529                       # ITB hits
+system.cpu1.itb.fetch_misses                     3380                       # ITB misses
+system.cpu1.itb.fetch_acv                         133                       # ITB acv
+system.cpu1.itb.fetch_accesses                 665909                       # ITB accesses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
@@ -970,580 +986,572 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numPwrStateTransitions               4646                       # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples         2323                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean    818936669.177787                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev   339506423.560652                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1000-5e+10         2323    100.00%    100.00% # Distribution of time spent in the clock gated state
+system.cpu1.numPwrStateTransitions               4980                       # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples         2490                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean    762354971.285141                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev   386526411.344669                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10         2490    100.00%    100.00% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::min_value       400000                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::max_value    975573000                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total           2323                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON     5282220000                       # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 1902389882500                       # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles                        10566764                       # number of cpu cycles simulated
+system.cpu1.pwrStateClkGateDist::max_value    975501000                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total           2490                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON     8269651500                       # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 1898263878500                       # Cumulative time (in ticks) in various power states
+system.cpu1.numCycles                        16541794                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles           3825216                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                      10675597                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                    2716012                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches            725621                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                      5983543                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                 229964                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.MiscStallCycles               23815                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles        51735                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles        41039                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles           40                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                  1221851                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes                48225                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples          10040370                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.063267                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.470833                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles           6749073                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                      16895090                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                    4250134                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches           1224211                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                      8698208                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                 363130                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.MiscStallCycles               26231                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles        65753                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles        47571                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles           39                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                  1900929                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes                80768                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples          15768440                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.071450                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.476995                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                 8168289     81.35%     81.35% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                  102687      1.02%     82.38% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                  210133      2.09%     84.47% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                  146343      1.46%     85.93% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                  249317      2.48%     88.41% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                   97935      0.98%     89.39% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                  113554      1.13%     90.52% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                   71548      0.71%     91.23% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                  880564      8.77%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                12797159     81.16%     81.16% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                  186632      1.18%     82.34% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                  321640      2.04%     84.38% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                  225512      1.43%     85.81% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                  384419      2.44%     88.25% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                  144313      0.92%     89.16% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                  169042      1.07%     90.24% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                  202635      1.29%     91.52% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                 1337088      8.48%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total            10040370                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.257033                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       1.010300                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                 3212898                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles              5233388                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                  1306839                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles               176592                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles                110652                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved               87490                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred                 4477                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts               8611500                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts                14236                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles                110652                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                 3332108                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                 534859                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles       3861101                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                  1363516                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles               838132                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts               8128723                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                  840                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                 81504                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                 20811                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents                431912                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands            5442265                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups              9792683                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups         9760108                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups            27875                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps              4220598                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                 1221659                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts            323796                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts         24055                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                  1462372                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads             1548375                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores             895151                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads           190303                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores          111620                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                   7151730                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded             356002                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                  6823456                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued            19520                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined        1627236                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined       806919                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        274884                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples     10040370                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.679602                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.404814                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total            15768440                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.256933                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       1.021358                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                 5523877                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles              7693314                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                  2103455                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles               273251                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles                174542                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved              146034                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred                 7171                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              13792543                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts                22640                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles                174542                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                 5705734                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                 782365                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles       5725411                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                  2195690                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles              1184696                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              13060888                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                 4153                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                107025                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                 30497                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents                586772                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands            8670673                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups             15585724                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups        15521516                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups            57730                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps              6788049                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                 1882616                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts            491915                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts         50500                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                  2201368                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads             2434805                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            1482534                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads           303562                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores          164759                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  11452007                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded             560044                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 10991859                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            27120                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined        2468765                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined      1174488                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        414117                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples     15768440                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.697080                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.421678                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0            7219551     71.91%     71.91% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1            1226248     12.21%     84.12% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2             523144      5.21%     89.33% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3             383300      3.82%     93.15% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4             329501      3.28%     96.43% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5             173963      1.73%     98.16% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6             102712      1.02%     99.18% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7              58679      0.58%     99.77% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8              23272      0.23%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           11265469     71.44%     71.44% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1            1937394     12.29%     83.73% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2             827410      5.25%     88.98% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3             596936      3.79%     92.76% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4             547934      3.47%     96.24% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5             289502      1.84%     98.07% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6             188780      1.20%     99.27% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7              83209      0.53%     99.80% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8              31806      0.20%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total       10040370                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total       15768440                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                  25321     11.84%     11.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     0      0.00%     11.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%     11.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     11.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     11.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     11.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     11.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     11.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     11.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     11.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     11.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     11.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     11.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     11.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     11.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     11.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     11.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     11.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     11.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     11.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     11.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     11.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     11.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     11.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     11.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     11.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     11.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     11.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     11.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead                118979     55.64%     67.48% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite                69548     32.52%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                  32091     10.27%     10.27% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     0      0.00%     10.27% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%     10.27% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     10.27% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     10.27% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     10.27% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%     10.27% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     10.27% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     10.27% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     10.27% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     10.27% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     10.27% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     10.27% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     10.27% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     10.27% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%     10.27% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     10.27% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%     10.27% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     10.27% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     10.27% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     10.27% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     10.27% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     10.27% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     10.27% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     10.27% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     10.27% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     10.27% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     10.27% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     10.27% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead                173932     55.66%     65.93% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite               106485     34.07%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass             3973      0.06%      0.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu              4192346     61.44%     61.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               10770      0.16%     61.66% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     61.66% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd              10332      0.15%     61.81% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     61.81% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     61.81% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     61.81% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv               1986      0.03%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead             1560504     22.87%     84.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite             845461     12.39%     97.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::IprAccess            198084      2.90%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass             4751      0.04%      0.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu              6803980     61.90%     61.94% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               16523      0.15%     62.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     62.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd              13867      0.13%     62.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     62.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     62.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     62.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv               2375      0.02%     62.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     62.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     62.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     62.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     62.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     62.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     62.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     62.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     62.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     62.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     62.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     62.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     62.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     62.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     62.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     62.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     62.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     62.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     62.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     62.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     62.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead             2450394     22.29%     84.53% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite            1410696     12.83%     97.37% # Type of FU issued
+system.cpu1.iq.FU_type_0::IprAccess            289273      2.63%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total               6823456                       # Type of FU issued
-system.cpu1.iq.rate                          0.645747                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                     213848                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.031340                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads          23830038                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes          9093503                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses      6518367                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads              90611                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes             45521                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses        43008                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses               6985974                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                  47357                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads           77493                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total              10991859                       # Type of FU issued
+system.cpu1.iq.rate                          0.664490                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                     312508                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.028431                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads          37874505                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         14381418                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     10489971                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads             217280                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes            104295                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses       101356                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses              11183979                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                 115637                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads          113432                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads       335188                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses          932                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation         4197                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores       122462                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads       527848                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses         1066                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation         5067                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores       174171                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads          439                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked        72925                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads          475                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked        99025                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles                110652                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                 347034                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles               152695                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts            7850434                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts            37055                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts              1548375                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts              895151                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            329794                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                  4928                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents               146829                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents          4197                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect         25483                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect        92224                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              117707                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts              6707770                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts              1507715                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts           115685                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles                174542                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                 497039                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles               226226                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           12632900                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts            57966                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts              2434805                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts             1482534                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            508876                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                  6584                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents               218362                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents          5067                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect         44763                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect       141821                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              186584                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             10809707                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts              2356029                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           182151                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       342702                       # number of nop insts executed
-system.cpu1.iew.exec_refs                     2339108                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                  982956                       # Number of branches executed
-system.cpu1.iew.exec_stores                    831393                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.634799                       # Inst execution rate
-system.cpu1.iew.wb_sent                       6597173                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                      6561375                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                  3197425                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                  4464974                       # num instructions consuming a value
-system.cpu1.iew.wb_rate                      0.620945                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.716113                       # average fanout of values written-back
-system.cpu1.commit.commitSquashedInsts        1594434                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls          81118                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           100274                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples      9755465                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.627758                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.585985                       # Number of insts commited each cycle
+system.cpu1.iew.exec_nop                       620849                       # number of nop insts executed
+system.cpu1.iew.exec_refs                     3747857                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                 1612675                       # Number of branches executed
+system.cpu1.iew.exec_stores                   1391828                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.653479                       # Inst execution rate
+system.cpu1.iew.wb_sent                      10644010                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     10591327                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                  5073681                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                  7144079                       # num instructions consuming a value
+system.cpu1.iew.wb_rate                      0.640277                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.710194                       # average fanout of values written-back
+system.cpu1.commit.commitSquashedInsts        2479122                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         145927                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           162123                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples     15327061                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.652859                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.628724                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0      7484983     76.73%     76.73% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1      1079374     11.06%     87.79% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2       367183      3.76%     91.55% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3       234920      2.41%     93.96% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4       168491      1.73%     95.69% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5        74517      0.76%     96.45% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6        76064      0.78%     97.23% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7        56824      0.58%     97.82% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8       213109      2.18%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     11704556     76.37%     76.37% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1      1675096     10.93%     87.29% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2       596024      3.89%     91.18% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3       370132      2.41%     93.60% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4       281840      1.84%     95.44% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5       119415      0.78%     96.22% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6       109784      0.72%     96.93% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       115974      0.76%     97.69% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8       354240      2.31%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total      9755465                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts             6124073                       # Number of instructions committed
-system.cpu1.commit.committedOps               6124073                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total     15327061                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts            10006417                       # Number of instructions committed
+system.cpu1.commit.committedOps              10006417                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                       1985876                       # Number of memory references committed
-system.cpu1.commit.loads                      1213187                       # Number of loads committed
-system.cpu1.commit.membars                      22586                       # Number of memory barriers committed
-system.cpu1.commit.branches                    866488                       # Number of branches committed
-system.cpu1.commit.fp_insts                     41227                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                  5722327                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls               95129                       # Number of function calls committed.
-system.cpu1.commit.op_class_0::No_OpClass       247554      4.04%      4.04% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu         3646853     59.55%     63.59% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult          10597      0.17%     63.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv               0      0.00%     63.76% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd         10326      0.17%     63.93% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     63.93% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     63.93% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     63.93% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv          1986      0.03%     63.97% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     63.97% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     63.97% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     63.97% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     63.97% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     63.97% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     63.97% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     63.97% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     63.97% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     63.97% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     63.97% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     63.97% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     63.97% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     63.97% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     63.97% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     63.97% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     63.97% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     63.97% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     63.97% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     63.97% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     63.97% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     63.97% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead        1235773     20.18%     84.14% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite        772900     12.62%     96.77% # Class of committed instruction
-system.cpu1.commit.op_class_0::IprAccess       198084      3.23%    100.00% # Class of committed instruction
+system.cpu1.commit.refs                       3215320                       # Number of memory references committed
+system.cpu1.commit.loads                      1906957                       # Number of loads committed
+system.cpu1.commit.membars                      46297                       # Number of memory barriers committed
+system.cpu1.commit.branches                   1432968                       # Number of branches committed
+system.cpu1.commit.fp_insts                     99355                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                  9296453                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls              155642                       # Number of function calls committed.
+system.cpu1.commit.op_class_0::No_OpClass       467886      4.68%      4.68% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu         5954632     59.51%     64.18% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult          16225      0.16%     64.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv               0      0.00%     64.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd         13860      0.14%     64.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     64.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     64.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     64.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv          2375      0.02%     64.51% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     64.51% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     64.51% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     64.51% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     64.51% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     64.51% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     64.51% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     64.51% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     64.51% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     64.51% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     64.51% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     64.51% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     64.51% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     64.51% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     64.51% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     64.51% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     64.51% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     64.51% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     64.51% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     64.51% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     64.51% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     64.51% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead        1953254     19.52%     84.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite       1308912     13.08%     97.11% # Class of committed instruction
+system.cpu1.commit.op_class_0::IprAccess       289273      2.89%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total          6124073                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events               213109                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                    17170417                       # The number of ROB reads
-system.cpu1.rob.rob_writes                   15719262                       # The number of ROB writes
-system.cpu1.timesIdled                          71397                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                         526394                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  3804777442                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                    5880491                       # Number of Instructions Simulated
-system.cpu1.committedOps                      5880491                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.796919                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.796919                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.556508                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.556508                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                 8685381                       # number of integer regfile reads
-system.cpu1.int_regfile_writes                4740732                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                    27201                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                   25643                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads                 310247                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                141917                       # number of misc regfile writes
-system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.tags.replacements            65099                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          463.722972                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            1848833                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs            65611                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            28.178705                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     1879972526500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   463.722972                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.905709                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.905709                       # Average percentage of cache occupancy
+system.cpu1.commit.op_class_0::total         10006417                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events               354240                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                    27350454                       # The number of ROB reads
+system.cpu1.rob.rob_writes                   25410376                       # The number of ROB writes
+system.cpu1.timesIdled                         127916                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                         773354                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  3796525267                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                    9543281                       # Number of Instructions Simulated
+system.cpu1.committedOps                      9543281                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              1.733345                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.733345                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.576919                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.576919                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                13915898                       # number of integer regfile reads
+system.cpu1.int_regfile_writes                7574327                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                    57027                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                   56084                       # number of floating regfile writes
+system.cpu1.misc_regfile_reads                 548336                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                233992                       # number of misc regfile writes
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.tags.replacements           125899                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          488.643443                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            2930828                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           126411                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            23.184913                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle      47496090500                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   488.643443                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.954382                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.954382                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0          238                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0          239                       # Occupied blocks per task id
 system.cpu1.dcache.tags.age_task_id_blocks_1024::1          225                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           49                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           48                       # Occupied blocks per task id
 system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses          8556411                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses         8556411                       # Number of data accesses
-system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.ReadReq_hits::cpu1.data      1222356                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        1222356                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data       588321                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total        588321                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        17437                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        17437                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        16296                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        16296                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      1810677                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         1810677                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      1810677                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        1810677                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       112363                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       112363                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       161965                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       161965                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         1793                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total         1793                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data          891                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total          891                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       274328                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        274328                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       274328                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       274328                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1482127500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   1482127500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   7331574147                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   7331574147                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     19537500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total     19537500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data      6718500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total      6718500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data        34500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total        34500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data   8813701647                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   8813701647                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data   8813701647                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   8813701647                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      1334719                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      1334719                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data       750286                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total       750286                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        19230                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        19230                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        17187                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        17187                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      2085005                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      2085005                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      2085005                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      2085005                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.084185                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.084185                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.215871                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.215871                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.093240                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.093240                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.051842                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.051842                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.131572                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.131572                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.131572                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.131572                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13190.529801                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 13190.529801                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 45266.410317                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 45266.410317                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10896.542108                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10896.542108                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  7540.404040                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  7540.404040                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 32128.334137                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 32128.334137                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 32128.334137                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 32128.334137                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs       454264                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets          482                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs            15527                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets             10                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs    29.256392                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets    48.200000                       # average number of cycles each access was blocked
-system.cpu1.dcache.writebacks::writebacks        38456                       # number of writebacks
-system.cpu1.dcache.writebacks::total            38456                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        66033                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total        66033                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       137281                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total       137281                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data          379                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total          379                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data       203314                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total       203314                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data       203314                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total       203314                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data        46330                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total        46330                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        24684                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        24684                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         1414                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         1414                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data          891                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total          891                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data        71014                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total        71014                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data        71014                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total        71014                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data          162                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total          162                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2639                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2639                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         2801                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total         2801                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data    590183000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total    590183000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1153615997                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1153615997                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     13566500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     13566500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      5828500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total      5828500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data        33500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total        33500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   1743798997                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   1743798997                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   1743798997                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   1743798997                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     32350500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     32350500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data     32350500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total     32350500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.034711                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.034711                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.032899                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.032899                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.073531                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.073531                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.051842                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.051842                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.034059                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.034059                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.034059                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.034059                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12738.679042                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12738.679042                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46735.375020                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 46735.375020                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  9594.413013                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  9594.413013                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  6541.526375                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  6541.526375                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24555.707283                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24555.707283                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24555.707283                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24555.707283                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 199694.444444                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 199694.444444                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 11549.625134                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 11549.625134                       # average overall mshr uncacheable latency
-system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.cpu1.icache.tags.replacements           129926                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          466.448190                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs            1084325                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           130435                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs             8.313144                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     1880575078500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   466.448190                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.911032                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.911032                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.tag_accesses         13906652                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        13906652                       # Number of data accesses
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.ReadReq_hits::cpu1.data      1865609                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        1865609                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data       981966                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total        981966                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        38120                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        38120                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        34857                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        34857                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      2847575                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         2847575                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      2847575                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        2847575                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       231819                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       231819                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       282423                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       282423                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         5078                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total         5078                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data         2912                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total         2912                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       514242                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        514242                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       514242                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       514242                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   3027811000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   3027811000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  10676531998                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  10676531998                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     51207500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total     51207500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     16199500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total     16199500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  13704342998                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  13704342998                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  13704342998                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  13704342998                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      2097428                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      2097428                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      1264389                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      1264389                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        43198                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        43198                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        37769                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        37769                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      3361817                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      3361817                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      3361817                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      3361817                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.110525                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.110525                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.223367                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.223367                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.117552                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.117552                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.077100                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.077100                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.152965                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.152965                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.152965                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.152965                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13061.099392                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 13061.099392                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37803.337540                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 37803.337540                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10084.186688                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10084.186688                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  5563.015110                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  5563.015110                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26649.598823                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 26649.598823                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26649.598823                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 26649.598823                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs       625764                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets          300                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs            24254                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets             19                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs    25.800445                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets    15.789474                       # average number of cycles each access was blocked
+system.cpu1.dcache.writebacks::writebacks        81179                       # number of writebacks
+system.cpu1.dcache.writebacks::total            81179                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       142547                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total       142547                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       235954                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total       235954                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data          779                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total          779                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data       378501                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total       378501                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data       378501                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total       378501                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data        89272                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total        89272                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        46469                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        46469                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4299                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4299                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         2912                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total         2912                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       135741                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       135741                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       135741                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       135741                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data          182                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total          182                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         3016                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total         3016                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         3198                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total         3198                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1142608000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1142608000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1700967690                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1700967690                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     38610000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     38610000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     13287500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     13287500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   2843575690                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   2843575690                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   2843575690                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   2843575690                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     35749500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     35749500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data     35749500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total     35749500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.042563                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.042563                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.036752                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.036752                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.099518                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.099518                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.077100                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.077100                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.040377                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.040377                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.040377                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.040377                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12799.175553                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12799.175553                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36604.353225                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 36604.353225                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  8981.158409                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8981.158409                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  4563.015110                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  4563.015110                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20948.539424                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20948.539424                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20948.539424                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20948.539424                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 196425.824176                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 196425.824176                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 11178.705441                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 11178.705441                       # average overall mshr uncacheable latency
+system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.cpu1.icache.tags.replacements           243897                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          471.203096                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs            1645008                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           244406                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs             6.730637                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     1879506005500                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   471.203096                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.920319                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.920319                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          509                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::1           24                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          419                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          420                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024     0.994141                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses          1352346                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses         1352346                       # Number of data accesses
-system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.cpu1.icache.ReadReq_hits::cpu1.inst      1084325                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        1084325                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst      1084325                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         1084325                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst      1084325                       # number of overall hits
-system.cpu1.icache.overall_hits::total        1084325                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       137526                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       137526                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       137526                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        137526                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       137526                       # number of overall misses
-system.cpu1.icache.overall_misses::total       137526                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   1969078999                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   1969078999                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   1969078999                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   1969078999                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   1969078999                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   1969078999                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst      1221851                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total      1221851                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst      1221851                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total      1221851                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst      1221851                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total      1221851                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.112555                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.112555                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.112555                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.112555                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.112555                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.112555                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14317.867160                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 14317.867160                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14317.867160                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 14317.867160                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14317.867160                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 14317.867160                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs          342                       # number of cycles access was blocked
+system.cpu1.icache.tags.tag_accesses          2145410                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses         2145410                       # Number of data accesses
+system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.cpu1.icache.ReadReq_hits::cpu1.inst      1645008                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        1645008                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst      1645008                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total         1645008                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst      1645008                       # number of overall hits
+system.cpu1.icache.overall_hits::total        1645008                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       255921                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       255921                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       255921                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        255921                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       255921                       # number of overall misses
+system.cpu1.icache.overall_misses::total       255921                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   3476894499                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   3476894499                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   3476894499                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   3476894499                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   3476894499                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   3476894499                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst      1900929                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      1900929                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst      1900929                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total      1900929                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst      1900929                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total      1900929                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.134629                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.134629                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.134629                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.134629                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.134629                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.134629                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13585.811633                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13585.811633                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13585.811633                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13585.811633                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13585.811633                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13585.811633                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs          470                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs               30                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs               38                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs    11.400000                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs    12.368421                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.writebacks::writebacks       129926                       # number of writebacks
-system.cpu1.icache.writebacks::total           129926                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst         7031                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total         7031                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst         7031                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total         7031                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst         7031                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total         7031                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       130495                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       130495                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       130495                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       130495                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       130495                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       130495                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   1753458499                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   1753458499                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   1753458499                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   1753458499                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   1753458499                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   1753458499                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.106801                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.106801                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.106801                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.106801                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.106801                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.106801                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13436.978421                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13436.978421                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13436.978421                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 13436.978421                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13436.978421                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 13436.978421                       # average overall mshr miss latency
+system.cpu1.icache.writebacks::writebacks       243897                       # number of writebacks
+system.cpu1.icache.writebacks::total           243897                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        11440                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total        11440                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst        11440                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total        11440                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst        11440                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total        11440                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       244481                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       244481                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       244481                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       244481                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       244481                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       244481                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3131245499                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   3131245499                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3131245499                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   3131245499                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3131245499                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   3131245499                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.128611                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.128611                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.128611                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.128611                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.128611                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.128611                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12807.725341                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12807.725341                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12807.725341                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 12807.725341                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12807.725341                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 12807.725341                       # average overall mshr miss latency
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
@@ -1556,13 +1564,13 @@ system.disk2.dma_read_txs                           0                       # Nu
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.iobus.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq                 7367                       # Transaction distribution
-system.iobus.trans_dist::ReadResp                7367                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               53946                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              53946                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        10580                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1006                       # Packet count per connected master and slave (bytes)
+system.iobus.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.iobus.trans_dist::ReadReq                 7374                       # Transaction distribution
+system.iobus.trans_dist::ReadResp                7374                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               54571                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              54571                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        11828                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1010                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
@@ -1570,12 +1578,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        1814
 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         2468                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        39176                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  122626                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        42320                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2717                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        40428                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83462                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::total        83462                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  123890                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        47312                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2733                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
@@ -1583,74 +1591,74 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9074
 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         9852                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        68530                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2730138                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             10859000                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::total        73538                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661656                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::total      2661656                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2735194                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             12271500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               821000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               818000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                11000                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy                10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer22.occupancy              178000                       # Layer occupancy (ticks)
+system.iobus.reqLayer22.occupancy              178500                       # Layer occupancy (ticks)
 system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            14076000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            14105000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer24.occupancy             2828000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy             6060001                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy             6057000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy               90500                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           216164058                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           216200796                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            26782000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            27409000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            41946000                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            41958000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements                41693                       # number of replacements
-system.iocache.tags.tagsinuse                0.508375                       # Cycle average of tags in use
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.replacements                41699                       # number of replacements
+system.iocache.tags.tagsinuse                0.499134                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                41709                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                41715                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1712300354000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     0.508375                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.031773                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.031773                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1712299837000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     0.499134                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.031196                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.031196                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
-system.iocache.tags.data_accesses              375525                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
+system.iocache.tags.tag_accesses               375579                       # Number of tag accesses
+system.iocache.tags.data_accesses              375579                       # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.iocache.ReadReq_misses::tsunami.ide          179                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              179                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
-system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
-system.iocache.overall_misses::total            41725                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     21862383                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     21862383                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::tsunami.ide   4858655675                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4858655675                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide   4880518058                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   4880518058                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide   4880518058                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   4880518058                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::tsunami.ide        41731                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             41731                       # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide        41731                       # number of overall misses
+system.iocache.overall_misses::total            41731                       # number of overall misses
+system.iocache.ReadReq_miss_latency::tsunami.ide     22562883                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     22562883                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::tsunami.ide   4858746913                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4858746913                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide   4881309796                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   4881309796                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide   4881309796                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   4881309796                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::tsunami.ide          179                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            179                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::tsunami.ide        41731                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           41731                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide        41731                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          41731                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
@@ -1659,38 +1667,38 @@ system.iocache.demand_miss_rate::tsunami.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126372.156069                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 126372.156069                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116929.526256                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 116929.526256                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 116968.677244                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 116968.677244                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 116968.677244                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 116968.677244                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126049.625698                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 126049.625698                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116931.722011                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 116931.722011                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 116970.832139                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 116970.832139                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 116970.832139                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 116970.832139                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs            10                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    2                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs            5                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.writebacks::writebacks           41520                       # number of writebacks
 system.iocache.writebacks::total                41520                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::tsunami.ide          179                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          179                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::tsunami.ide        41552                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        41552                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide        41725                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13212383                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     13212383                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   2778666661                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2778666661                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide   2791879044                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   2791879044                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide   2791879044                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   2791879044                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::tsunami.ide        41731                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        41731                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide        41731                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        41731                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13612883                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     13612883                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   2778734565                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2778734565                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide   2792347448                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   2792347448                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide   2792347448                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   2792347448                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1699,463 +1707,452 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76372.156069                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 76372.156069                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66872.031695                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66872.031695                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66911.421067                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 66911.421067                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66911.421067                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 66911.421067                       # average overall mshr miss latency
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements                   344445                       # number of replacements
-system.l2c.tags.tagsinuse                65257.633522                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    4040340                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   409472                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     9.867195                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle               7589084000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   53236.660660                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     5305.017555                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     6468.149046                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      210.708528                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data       37.097733                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.812327                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.080948                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.098696                       # Average percentage of cache occupancy
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-system.l2c.tags.occ_percent::cpu1.data       0.000566                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.995752                       # Average percentage of cache occupancy
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-system.l2c.tags.age_task_id_blocks_1024::0          238                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1         3644                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2937                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5880                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        52328                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.992233                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 38778519                       # Number of tag accesses
-system.l2c.tags.data_accesses                38778519                       # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.l2c.WritebackDirty_hits::writebacks       830376                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total          830376                       # number of WritebackDirty hits
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-system.l2c.WritebackClean_hits::total          866904                       # number of WritebackClean hits
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-system.l2c.UpgradeReq_hits::cpu1.data              78                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 255                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data            93                       # number of SCUpgradeReq hits
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-system.l2c.overall_hits::total                2132258                       # number of overall hits
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-system.l2c.UpgradeReq_misses::total              3132                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data           74                       # number of SCUpgradeReq misses
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-system.l2c.overall_misses::cpu1.data             9209                       # number of overall misses
-system.l2c.overall_misses::total               410120                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data      1461500                       # number of UpgradeReq miss cycles
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-system.l2c.UpgradeReq_miss_latency::total      2970500                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data       588500                       # number of SCUpgradeReq miss cycles
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-system.l2c.overall_miss_latency::cpu1.data   1020478000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    32519612500                       # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks       830376                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total       830376                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackClean_accesses::writebacks       866904                       # number of WritebackClean accesses(hits+misses)
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-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.934004                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.889362                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.924712                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.443114                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.796875                       # miss rate for SCUpgradeReq accesses
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-system.l2c.ReadExReq_miss_rate::cpu0.data     0.400353                       # miss rate for ReadExReq accesses
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-system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.013264                       # miss rate for ReadCleanReq accesses
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-system.l2c.ReadCleanReq_miss_rate::total     0.013377                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.260010                       # miss rate for ReadSharedReq accesses
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-system.l2c.ReadSharedReq_miss_rate::total     0.250706                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.013264                       # miss rate for demand accesses
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-system.l2c.overall_miss_rate::cpu0.inst      0.013264                       # miss rate for overall accesses
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-system.l2c.overall_miss_rate::total          0.161314                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   583.433134                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2406.698565                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   948.435504                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  7952.702703                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   578.431373                       # average SCUpgradeReq miss latency
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-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 89289.172020                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 112521.241050                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 90907.458667                       # average ReadExReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 84368.325288                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 84935.483871                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 84437.161501                       # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 73855.884793                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 93546.441496                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 73915.352724                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 84368.325288                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 78335.663121                       # average overall miss latency
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-system.l2c.demand_avg_miss_latency::cpu1.data 110813.117602                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 79292.920365                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::cpu0.data 78335.663121                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::cpu1.data 110813.117602                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 79292.920365                       # average overall miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76049.625698                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 76049.625698                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66873.665889                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66873.665889                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66913.025041                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 66913.025041                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66913.025041                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 66913.025041                       # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.l2c.tags.replacements                   345621                       # number of replacements
+system.l2c.tags.tagsinuse                65429.949099                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    4347999                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   411104                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    10.576397                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle               5987439000                       # Cycle when the warmup percentage was hit.
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 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
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 system.l2c.CleanEvict_mshr_misses::writebacks           10                       # number of CleanEvict MSHR misses
 system.l2c.CleanEvict_mshr_misses::total           10                       # number of CleanEvict MSHR misses
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+system.l2c.overall_mshr_misses::cpu1.data        12805                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          411102                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_uncacheable::cpu0.data         7013                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data          182                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total         7195                       # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu0.data        10003                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data         3016                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total        13019                       # number of WriteReq MSHR uncacheable
+system.l2c.overall_mshr_uncacheable_misses::cpu0.data        17016                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data         3198                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total        20214                       # number of overall MSHR uncacheable misses
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data       274500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data        57500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total       332000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data        18500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total        18500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   8703194500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1171449500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   9874644000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst   1039194500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst     96887500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total   1136082000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  17432939000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    133569000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total  17566508000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst   1039194500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  26136133500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst     96887500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   1305018500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  28577234000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   1039194500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  26136133500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst     96887500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   1305018500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  28577234000                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1475661000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     33474500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   1509135500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   1475661000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data     33474500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   1509135500                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.934004                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.889362                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.924712                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.443114                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.796875                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.596610                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.400353                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.375213                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.398493                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.013264                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.014127                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.013362                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.260010                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.019567                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.250706                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.013264                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.289464                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.014127                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.142329                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.161307                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.013264                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.289464                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.014127                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.142329                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.161307                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20051.297405                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20180.223285                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20077.107280                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19831.081081                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19696.078431                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 19752.840909                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79289.154186                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 102521.241050                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 80907.442075                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 74368.288229                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 75045.578405                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 74449.830285                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 63878.339425                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 83545.839566                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63937.737723                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74368.288229                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68351.594731                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75045.578405                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 100813.063416                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 69308.157973                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74368.288229                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68351.594731                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75045.578405                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 100813.063416                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 69308.157973                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210253.697383                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187182.098765                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209734.153461                       # average ReadReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 88074.343242                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 10825.955016                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 77028.154993                       # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests        844318                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       393480                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests          433                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.002107                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.002137                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.002117                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.002247                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.001093                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.427024                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.271164                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.405440                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.015404                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.005220                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.013246                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.272862                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.019084                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.253523                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.015404                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.304432                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005220                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.103313                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.162131                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.015404                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.304432                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005220                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.103313                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.162131                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        45750                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19166.666667                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 36888.888889                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        18500                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        18500                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79104.848165                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 104314.292075                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 81439.691219                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 74206.976578                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 75930.642633                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 74350.916230                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 63857.855060                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 84805.714286                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63978.016615                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74206.976578                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68237.528621                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75930.642633                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 101914.759859                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 69513.731385                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74206.976578                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68237.528621                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75930.642633                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 101914.759859                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 69513.731385                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210417.938115                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 183925.824176                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209747.810980                       # average ReadReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 86721.967560                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 10467.323327                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 74657.935094                       # average overall mshr uncacheable latency
+system.membus.snoop_filter.tot_requests        850516                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests       398567                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests          435                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq                7194                       # Transaction distribution
-system.membus.trans_dist::ReadResp             297120                       # Transaction distribution
-system.membus.trans_dist::WriteReq              12394                       # Transaction distribution
-system.membus.trans_dist::WriteResp             12394                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       122579                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           262673                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             5556                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq           1697                       # Transaction distribution
+system.membus.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadReq                7195                       # Transaction distribution
+system.membus.trans_dist::ReadResp             297176                       # Transaction distribution
+system.membus.trans_dist::WriteReq              13019                       # Transaction distribution
+system.membus.trans_dist::WriteResp             13019                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       123513                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           262911                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             6111                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq           4826                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               3                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            120271                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           120125                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        289973                       # Transaction distribution
-system.membus.trans_dist::BadAddressError           47                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            121549                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           121146                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        290030                       # Transaction distribution
+system.membus.trans_dist::BadAddressError           49                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        39176                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1170427                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio           94                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      1209697                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83433                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        83433                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1293130                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        68530                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     31401600                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     31470130                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        40428                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1177677                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio           98                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      1218203                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83445                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        83445                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1301648                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        73538                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     31530048                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     31603586                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2658240                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2658240                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                34128370                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             4361                       # Total snoops (count)
-system.membus.snoopTraffic                      28480                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            478637                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.001444                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.037968                       # Request fanout histogram
+system.membus.pkt_size::total                34261826                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                            11676                       # Total snoops (count)
+system.membus.snoopTraffic                      28672                       # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples            484282                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.001355                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.036780                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  477946     99.86%     99.86% # Request fanout histogram
-system.membus.snoop_fanout::1                     691      0.14%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  483626     99.86%     99.86% # Request fanout histogram
+system.membus.snoop_fanout::1                     656      0.14%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              478637                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            34935499                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              484282                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            36370000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1350989532                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1352579532                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy               59500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy               62000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2172548749                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2178718000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy             925113                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy             960113                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests      5110475                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      2554732                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests       342217                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops           1055                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops          987                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.snoop_filter.tot_requests      5113699                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      2556514                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests       337557                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops           1071                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops         1003                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops           68                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadReq               7194                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2261145                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             12394                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            12394                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty       911435                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean      1144537                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict          834683                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            5633                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq          1816                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           7449                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp            1                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           302973                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          302973                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq       1145857                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      1108145                       # Transaction distribution
-system.toL2Bus.trans_dist::BadAddressError           47                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq          240                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      3045120                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      4050284                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       390880                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       209583                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               7695867                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    129904512                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    135990364                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     16664640                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side      6622614                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              289182130                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          363206                       # Total snoops (count)
-system.toL2Bus.snoopTraffic                   6121792                       # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples          2928698                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.120181                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.325532                       # Request fanout histogram
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.trans_dist::ReadReq               7195                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2265500                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             13019                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            13019                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty       906543                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean      1152402                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          825837                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           10249                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq          5740                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          15989                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           300358                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          300358                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq       1153745                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      1104612                       # Transaction distribution
+system.toL2Bus.trans_dist::BadAddressError           49                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq          203                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2726862                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3834313                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       732820                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       401077                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               7695072                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    116326272                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    128153608                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     31253696                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     13151546                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              288885122                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          379909                       # Total snoops (count)
+system.toL2Bus.snoopTraffic                   6725760                       # Total snoop traffic (bytes)
+system.toL2Bus.snoop_fanout::samples          2940742                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.121053                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.326514                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                2577056     87.99%     87.99% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 351320     12.00%     99.99% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                    312      0.01%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                     10      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                2585068     87.91%     87.91% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 355364     12.08%     99.99% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                    309      0.01%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3                      1      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              3                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            2928698                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         4546181919                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            2940742                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         4550461413                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           291385                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           301885                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        1524803969                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        1365446887                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        2026499354                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        1921756875                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         197300876                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy         368286347                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         108970290                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy         208891088                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
+system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -2187,185 +2184,194 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
-system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1907672102500                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
+system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1906533530000                       # Cumulative time (in ticks) in various power states
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    6366                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    197565                       # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0                   70781     40.59%     40.59% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21                    131      0.08%     40.66% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22                   1927      1.10%     41.77% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30                     20      0.01%     41.78% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                 101534     58.22%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              174393                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    69444     49.27%     49.27% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21                     131      0.09%     49.36% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22                    1927      1.37%     50.73% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30                      20      0.01%     50.74% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   69424     49.26%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total               140946                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1863377945500     97.69%     97.69% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               65817500      0.00%     97.70% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              580544500      0.03%     97.73% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30               11361000      0.00%     97.73% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            43328343000      2.27%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1907364011500                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.981111                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.quiesce                    6504                       # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei                    179089                       # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0                   63660     40.34%     40.34% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21                    131      0.08%     40.42% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22                   1926      1.22%     41.64% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30                    175      0.11%     41.75% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                  91921     58.25%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              157813                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0                    62631     49.19%     49.19% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21                     131      0.10%     49.30% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22                    1926      1.51%     50.81% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30                     175      0.14%     50.95% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31                   62456     49.05%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total               127319                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0            1863112245000     97.74%     97.74% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               65536000      0.00%     97.74% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              577434000      0.03%     97.77% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30               84972500      0.00%     97.78% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            42413276000      2.22%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1906253463500                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0                 0.983836                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.683751                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.808209                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.syscall::2                         8      3.76%      3.76% # number of syscalls executed
-system.cpu0.kern.syscall::3                        18      8.45%     12.21% # number of syscalls executed
-system.cpu0.kern.syscall::4                         4      1.88%     14.08% # number of syscalls executed
-system.cpu0.kern.syscall::6                        32     15.02%     29.11% # number of syscalls executed
-system.cpu0.kern.syscall::12                        1      0.47%     29.58% # number of syscalls executed
-system.cpu0.kern.syscall::17                        8      3.76%     33.33% # number of syscalls executed
-system.cpu0.kern.syscall::19                       10      4.69%     38.03% # number of syscalls executed
-system.cpu0.kern.syscall::20                        6      2.82%     40.85% # number of syscalls executed
-system.cpu0.kern.syscall::23                        1      0.47%     41.31% # number of syscalls executed
-system.cpu0.kern.syscall::24                        3      1.41%     42.72% # number of syscalls executed
-system.cpu0.kern.syscall::33                        6      2.82%     45.54% # number of syscalls executed
-system.cpu0.kern.syscall::41                        2      0.94%     46.48% # number of syscalls executed
-system.cpu0.kern.syscall::45                       33     15.49%     61.97% # number of syscalls executed
-system.cpu0.kern.syscall::47                        3      1.41%     63.38% # number of syscalls executed
-system.cpu0.kern.syscall::48                       10      4.69%     68.08% # number of syscalls executed
-system.cpu0.kern.syscall::54                       10      4.69%     72.77% # number of syscalls executed
-system.cpu0.kern.syscall::58                        1      0.47%     73.24% # number of syscalls executed
-system.cpu0.kern.syscall::59                        6      2.82%     76.06% # number of syscalls executed
-system.cpu0.kern.syscall::71                       21      9.86%     85.92% # number of syscalls executed
-system.cpu0.kern.syscall::73                        3      1.41%     87.32% # number of syscalls executed
-system.cpu0.kern.syscall::74                        5      2.35%     89.67% # number of syscalls executed
-system.cpu0.kern.syscall::87                        1      0.47%     90.14% # number of syscalls executed
-system.cpu0.kern.syscall::90                        3      1.41%     91.55% # number of syscalls executed
-system.cpu0.kern.syscall::92                        9      4.23%     95.77% # number of syscalls executed
-system.cpu0.kern.syscall::97                        2      0.94%     96.71% # number of syscalls executed
-system.cpu0.kern.syscall::98                        2      0.94%     97.65% # number of syscalls executed
-system.cpu0.kern.syscall::132                       1      0.47%     98.12% # number of syscalls executed
-system.cpu0.kern.syscall::144                       2      0.94%     99.06% # number of syscalls executed
-system.cpu0.kern.syscall::147                       2      0.94%    100.00% # number of syscalls executed
-system.cpu0.kern.syscall::total                   213                       # number of syscalls executed
+system.cpu0.kern.ipl_used::31                0.679453                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.806771                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.syscall::2                         7      3.93%      3.93% # number of syscalls executed
+system.cpu0.kern.syscall::3                        15      8.43%     12.36% # number of syscalls executed
+system.cpu0.kern.syscall::4                         4      2.25%     14.61% # number of syscalls executed
+system.cpu0.kern.syscall::6                        26     14.61%     29.21% # number of syscalls executed
+system.cpu0.kern.syscall::12                        1      0.56%     29.78% # number of syscalls executed
+system.cpu0.kern.syscall::17                        6      3.37%     33.15% # number of syscalls executed
+system.cpu0.kern.syscall::19                        7      3.93%     37.08% # number of syscalls executed
+system.cpu0.kern.syscall::20                        4      2.25%     39.33% # number of syscalls executed
+system.cpu0.kern.syscall::23                        1      0.56%     39.89% # number of syscalls executed
+system.cpu0.kern.syscall::24                        3      1.69%     41.57% # number of syscalls executed
+system.cpu0.kern.syscall::33                        6      3.37%     44.94% # number of syscalls executed
+system.cpu0.kern.syscall::41                        2      1.12%     46.07% # number of syscalls executed
+system.cpu0.kern.syscall::45                       29     16.29%     62.36% # number of syscalls executed
+system.cpu0.kern.syscall::47                        3      1.69%     64.04% # number of syscalls executed
+system.cpu0.kern.syscall::48                        8      4.49%     68.54% # number of syscalls executed
+system.cpu0.kern.syscall::54                        8      4.49%     73.03% # number of syscalls executed
+system.cpu0.kern.syscall::59                        6      3.37%     76.40% # number of syscalls executed
+system.cpu0.kern.syscall::71                       17      9.55%     85.96% # number of syscalls executed
+system.cpu0.kern.syscall::73                        3      1.69%     87.64% # number of syscalls executed
+system.cpu0.kern.syscall::74                        4      2.25%     89.89% # number of syscalls executed
+system.cpu0.kern.syscall::87                        1      0.56%     90.45% # number of syscalls executed
+system.cpu0.kern.syscall::90                        2      1.12%     91.57% # number of syscalls executed
+system.cpu0.kern.syscall::92                        7      3.93%     95.51% # number of syscalls executed
+system.cpu0.kern.syscall::97                        2      1.12%     96.63% # number of syscalls executed
+system.cpu0.kern.syscall::98                        2      1.12%     97.75% # number of syscalls executed
+system.cpu0.kern.syscall::132                       1      0.56%     98.31% # number of syscalls executed
+system.cpu0.kern.syscall::144                       1      0.56%     98.88% # number of syscalls executed
+system.cpu0.kern.syscall::147                       2      1.12%    100.00% # number of syscalls executed
+system.cpu0.kern.syscall::total                   178                       # number of syscalls executed
 system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir                  120      0.07%      0.07% # number of callpals executed
-system.cpu0.kern.callpal::wrmces                    1      0.00%      0.07% # number of callpals executed
-system.cpu0.kern.callpal::wrfen                     1      0.00%      0.07% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.07% # number of callpals executed
-system.cpu0.kern.callpal::swpctx                 3815      2.08%      2.15% # number of callpals executed
-system.cpu0.kern.callpal::tbi                      51      0.03%      2.18% # number of callpals executed
-system.cpu0.kern.callpal::wrent                     7      0.00%      2.18% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               167656     91.61%     93.80% # number of callpals executed
-system.cpu0.kern.callpal::rdps                   6177      3.38%     97.17% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp                     1      0.00%     97.17% # number of callpals executed
-system.cpu0.kern.callpal::wrusp                     2      0.00%     97.17% # number of callpals executed
-system.cpu0.kern.callpal::rdusp                     9      0.00%     97.18% # number of callpals executed
-system.cpu0.kern.callpal::whami                     2      0.00%     97.18% # number of callpals executed
-system.cpu0.kern.callpal::rti                    4658      2.55%     99.72% # number of callpals executed
-system.cpu0.kern.callpal::callsys                 369      0.20%     99.93% # number of callpals executed
-system.cpu0.kern.callpal::imb                     136      0.07%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                183007                       # number of callpals executed
-system.cpu0.kern.mode_switch::kernel             7158                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1253                       # number of protection mode switches
+system.cpu0.kern.callpal::wripir                  278      0.17%      0.17% # number of callpals executed
+system.cpu0.kern.callpal::wrmces                    1      0.00%      0.17% # number of callpals executed
+system.cpu0.kern.callpal::wrfen                     1      0.00%      0.17% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.17% # number of callpals executed
+system.cpu0.kern.callpal::swpctx                 3399      2.05%      2.22% # number of callpals executed
+system.cpu0.kern.callpal::tbi                      48      0.03%      2.25% # number of callpals executed
+system.cpu0.kern.callpal::wrent                     7      0.00%      2.26% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               151231     91.28%     93.54% # number of callpals executed
+system.cpu0.kern.callpal::rdps                   5900      3.56%     97.10% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp                     1      0.00%     97.10% # number of callpals executed
+system.cpu0.kern.callpal::wrusp                     2      0.00%     97.10% # number of callpals executed
+system.cpu0.kern.callpal::rdusp                     8      0.00%     97.10% # number of callpals executed
+system.cpu0.kern.callpal::whami                     2      0.00%     97.11% # number of callpals executed
+system.cpu0.kern.callpal::rti                    4349      2.63%     99.73% # number of callpals executed
+system.cpu0.kern.callpal::callsys                 315      0.19%     99.92% # number of callpals executed
+system.cpu0.kern.callpal::imb                     132      0.08%    100.00% # number of callpals executed
+system.cpu0.kern.callpal::total                165676                       # number of callpals executed
+system.cpu0.kern.mode_switch::kernel             6738                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1097                       # number of protection mode switches
 system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1253                      
-system.cpu0.kern.mode_good::user                 1253                      
+system.cpu0.kern.mode_good::kernel               1097                      
+system.cpu0.kern.mode_good::user                 1097                      
 system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch_good::kernel     0.175049                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel     0.162808                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.297943                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1905453819000     99.90%     99.90% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          1901068000      0.10%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total     0.280026                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel      1904214078500     99.91%     99.91% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          1672761500      0.09%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    3816                       # number of times the context was actually changed
+system.cpu0.kern.swap_context                    3400                       # number of times the context was actually changed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2323                       # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei                     40320                       # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0                   10930     33.84%     33.84% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22                   1925      5.96%     39.80% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30                    120      0.37%     40.18% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31                  19320     59.82%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total               32295                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0                    10890     45.94%     45.94% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22                    1925      8.12%     54.06% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30                     120      0.51%     54.57% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31                   10770     45.43%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total                23705                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1876314481500     98.36%     98.36% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22              564739500      0.03%     98.39% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30               58247500      0.00%     98.39% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            30733817000      1.61%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1907671285500                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0                 0.996340                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce                    2490                       # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei                     60423                       # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0                   18641     37.27%     37.27% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22                   1925      3.85%     41.12% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30                    278      0.56%     41.67% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31                  29176     58.33%    100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total               50020                       # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0                    18293     47.50%     47.50% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22                    1925      5.00%     52.50% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30                     278      0.72%     53.22% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31                   18016     46.78%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total                38512                       # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0            1873859043000     98.29%     98.29% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22              564907000      0.03%     98.32% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30              133677500      0.01%     98.32% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31            31975089500      1.68%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total        1906532717000                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0                 0.981331                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31                0.557453                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total             0.734015                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.syscall::3                        12     10.62%     10.62% # number of syscalls executed
-system.cpu1.kern.syscall::6                        10      8.85%     19.47% # number of syscalls executed
-system.cpu1.kern.syscall::15                        1      0.88%     20.35% # number of syscalls executed
-system.cpu1.kern.syscall::17                        7      6.19%     26.55% # number of syscalls executed
-system.cpu1.kern.syscall::23                        3      2.65%     29.20% # number of syscalls executed
-system.cpu1.kern.syscall::24                        3      2.65%     31.86% # number of syscalls executed
-system.cpu1.kern.syscall::33                        5      4.42%     36.28% # number of syscalls executed
-system.cpu1.kern.syscall::45                       21     18.58%     54.87% # number of syscalls executed
-system.cpu1.kern.syscall::47                        3      2.65%     57.52% # number of syscalls executed
-system.cpu1.kern.syscall::59                        1      0.88%     58.41% # number of syscalls executed
-system.cpu1.kern.syscall::71                       33     29.20%     87.61% # number of syscalls executed
-system.cpu1.kern.syscall::74                       11      9.73%     97.35% # number of syscalls executed
-system.cpu1.kern.syscall::132                       3      2.65%    100.00% # number of syscalls executed
-system.cpu1.kern.syscall::total                   113                       # number of syscalls executed
+system.cpu1.kern.ipl_used::31                0.617494                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total             0.769932                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.syscall::2                         1      0.68%      0.68% # number of syscalls executed
+system.cpu1.kern.syscall::3                        15     10.14%     10.81% # number of syscalls executed
+system.cpu1.kern.syscall::6                        16     10.81%     21.62% # number of syscalls executed
+system.cpu1.kern.syscall::15                        1      0.68%     22.30% # number of syscalls executed
+system.cpu1.kern.syscall::17                        9      6.08%     28.38% # number of syscalls executed
+system.cpu1.kern.syscall::19                        3      2.03%     30.41% # number of syscalls executed
+system.cpu1.kern.syscall::20                        2      1.35%     31.76% # number of syscalls executed
+system.cpu1.kern.syscall::23                        3      2.03%     33.78% # number of syscalls executed
+system.cpu1.kern.syscall::24                        3      2.03%     35.81% # number of syscalls executed
+system.cpu1.kern.syscall::33                        5      3.38%     39.19% # number of syscalls executed
+system.cpu1.kern.syscall::45                       25     16.89%     56.08% # number of syscalls executed
+system.cpu1.kern.syscall::47                        3      2.03%     58.11% # number of syscalls executed
+system.cpu1.kern.syscall::48                        2      1.35%     59.46% # number of syscalls executed
+system.cpu1.kern.syscall::54                        2      1.35%     60.81% # number of syscalls executed
+system.cpu1.kern.syscall::58                        1      0.68%     61.49% # number of syscalls executed
+system.cpu1.kern.syscall::59                        1      0.68%     62.16% # number of syscalls executed
+system.cpu1.kern.syscall::71                       37     25.00%     87.16% # number of syscalls executed
+system.cpu1.kern.syscall::74                       12      8.11%     95.27% # number of syscalls executed
+system.cpu1.kern.syscall::90                        1      0.68%     95.95% # number of syscalls executed
+system.cpu1.kern.syscall::92                        2      1.35%     97.30% # number of syscalls executed
+system.cpu1.kern.syscall::132                       3      2.03%     99.32% # number of syscalls executed
+system.cpu1.kern.syscall::144                       1      0.68%    100.00% # number of syscalls executed
+system.cpu1.kern.syscall::total                   148                       # number of syscalls executed
 system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir                   20      0.06%      0.06% # number of callpals executed
-system.cpu1.kern.callpal::wrmces                    1      0.00%      0.07% # number of callpals executed
-system.cpu1.kern.callpal::wrfen                     1      0.00%      0.07% # number of callpals executed
-system.cpu1.kern.callpal::swpctx                  449      1.34%      1.41% # number of callpals executed
-system.cpu1.kern.callpal::tbi                       3      0.01%      1.42% # number of callpals executed
-system.cpu1.kern.callpal::wrent                     7      0.02%      1.44% # number of callpals executed
-system.cpu1.kern.callpal::swpipl                27672     82.56%     84.00% # number of callpals executed
-system.cpu1.kern.callpal::rdps                   2585      7.71%     91.71% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp                     1      0.00%     91.71% # number of callpals executed
-system.cpu1.kern.callpal::wrusp                     5      0.01%     91.73% # number of callpals executed
-system.cpu1.kern.callpal::whami                     3      0.01%     91.74% # number of callpals executed
-system.cpu1.kern.callpal::rti                    2577      7.69%     99.42% # number of callpals executed
-system.cpu1.kern.callpal::callsys                 148      0.44%     99.87% # number of callpals executed
-system.cpu1.kern.callpal::imb                      44      0.13%    100.00% # number of callpals executed
+system.cpu1.kern.callpal::wripir                  175      0.33%      0.34% # number of callpals executed
+system.cpu1.kern.callpal::wrmces                    1      0.00%      0.34% # number of callpals executed
+system.cpu1.kern.callpal::wrfen                     1      0.00%      0.34% # number of callpals executed
+system.cpu1.kern.callpal::swpctx                 1166      2.23%      2.57% # number of callpals executed
+system.cpu1.kern.callpal::tbi                       5      0.01%      2.58% # number of callpals executed
+system.cpu1.kern.callpal::wrent                     7      0.01%      2.59% # number of callpals executed
+system.cpu1.kern.callpal::swpipl                44628     85.35%     87.94% # number of callpals executed
+system.cpu1.kern.callpal::rdps                   2858      5.47%     93.41% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp                     1      0.00%     93.41% # number of callpals executed
+system.cpu1.kern.callpal::wrusp                     5      0.01%     93.42% # number of callpals executed
+system.cpu1.kern.callpal::rdusp                     1      0.00%     93.42% # number of callpals executed
+system.cpu1.kern.callpal::whami                     3      0.01%     93.43% # number of callpals executed
+system.cpu1.kern.callpal::rti                    3189      6.10%     99.52% # number of callpals executed
+system.cpu1.kern.callpal::callsys                 200      0.38%     99.91% # number of callpals executed
+system.cpu1.kern.callpal::imb                      48      0.09%    100.00% # number of callpals executed
 system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::total                 33518                       # number of callpals executed
-system.cpu1.kern.mode_switch::kernel              911                       # number of protection mode switches
-system.cpu1.kern.mode_switch::user                493                       # number of protection mode switches
-system.cpu1.kern.mode_switch::idle               2088                       # number of protection mode switches
-system.cpu1.kern.mode_good::kernel                538                      
-system.cpu1.kern.mode_good::user                  493                      
-system.cpu1.kern.mode_good::idle                   45                      
-system.cpu1.kern.mode_switch_good::kernel     0.590560                       # fraction of useful protection mode switches
+system.cpu1.kern.callpal::total                 52290                       # number of callpals executed
+system.cpu1.kern.mode_switch::kernel             1624                       # number of protection mode switches
+system.cpu1.kern.mode_switch::user                640                       # number of protection mode switches
+system.cpu1.kern.mode_switch::idle               2399                       # number of protection mode switches
+system.cpu1.kern.mode_good::kernel                844                      
+system.cpu1.kern.mode_good::user                  640                      
+system.cpu1.kern.mode_good::idle                  204                      
+system.cpu1.kern.mode_switch_good::kernel     0.519704                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle      0.021552                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total     0.308133                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel        2257888000      0.12%      0.12% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user           790670500      0.04%      0.16% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1904622719000     99.84%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context                     450                       # number of times the context was actually changed
+system.cpu1.kern.mode_switch_good::idle      0.085035                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total     0.361999                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel        4862135000      0.26%      0.26% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user          1013458000      0.05%      0.31% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle        1900657116000     99.69%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context                    1167                       # number of times the context was actually changed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
index 39a06dc53..f5019500b 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
@@ -1,113 +1,113 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.876794                       # Number of seconds simulated
-sim_ticks                                1876794488000                       # Number of ticks simulated
-final_tick                               1876794488000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.862042                       # Number of seconds simulated
+sim_ticks                                1862042063000                       # Number of ticks simulated
+final_tick                               1862042063000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 152079                       # Simulator instruction rate (inst/s)
-host_op_rate                                   152079                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5387044029                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 330796                       # Number of bytes of host memory used
-host_seconds                                   348.39                       # Real time elapsed on the host
-sim_insts                                    52982943                       # Number of instructions simulated
-sim_ops                                      52982943                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 137297                       # Simulator instruction rate (inst/s)
+host_op_rate                                   137297                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4825772422                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 338492                       # Number of bytes of host memory used
+host_seconds                                   385.85                       # Real time elapsed on the host
+sim_insts                                    52976505                       # Number of instructions simulated
+sim_ops                                      52976505                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst            961728                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24880448                       # Number of bytes read from this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.inst            963392                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24881792                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             25843136                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       961728                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          961728                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7527680                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7527680                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              15027                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             388757                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             25846144                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       963392                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          963392                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7528832                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7528832                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              15053                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             388778                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                403799                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          117620                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               117620                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               512431                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             13256885                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide               512                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13769827                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          512431                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             512431                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4010924                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4010924                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4010924                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              512431                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            13256885                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide              512                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17780751                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        403799                       # Number of read requests accepted
-system.physmem.writeReqs                       117620                       # Number of write requests accepted
-system.physmem.readBursts                      403799                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     117620                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 25835776                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      7360                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7525824                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  25843136                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7527680                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      115                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_reads::total                403846                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          117638                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               117638                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               517385                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             13362637                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide               516                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                13880537                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          517385                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             517385                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4043320                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4043320                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4043320                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              517385                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            13362637                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide              516                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               17923857                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        403846                       # Number of read requests accepted
+system.physmem.writeReqs                       117638                       # Number of write requests accepted
+system.physmem.readBursts                      403846                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     117638                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 25839232                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      6912                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7527104                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  25846144                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7528832                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      108                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               25625                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               25421                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25559                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               25464                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               25431                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               24732                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               24935                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               25090                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               24946                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               25020                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25560                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              24886                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              24460                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25266                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25703                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25586                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7949                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7513                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                7969                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7485                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7367                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6667                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6767                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6715                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7150                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6697                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7421                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6978                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7150                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7899                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8060                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7804                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               25618                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25426                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25537                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               25512                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25419                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               24740                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               24937                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               25096                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               24930                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               25035                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25569                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              24892                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              24450                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              25273                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              25713                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25591                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7930                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7514                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                7945                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7523                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7351                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6673                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6769                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6726                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7138                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6708                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7428                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6991                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7147                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7895                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8063                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7810                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           9                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1876789160500                       # Total gap between requests
+system.physmem.numWrRetry                          12                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1862036687500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  403799                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  403846                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 117620                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    315619                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     35764                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     28247                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     23961                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        77                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         7                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 117638                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    315267                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     36112                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     28338                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     23939                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        68                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         5                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
@@ -149,192 +149,195 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1594                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2968                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4960                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4449                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6132                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6001                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5883                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6430                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     6949                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6473                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8556                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8916                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7560                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     8166                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     8427                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7602                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6731                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5823                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      313                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      176                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      107                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      111                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      152                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      158                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      100                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      153                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      145                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      161                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1560                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2800                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     3376                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4390                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5897                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6646                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7683                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     9037                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7269                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     7983                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     8709                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     7918                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7106                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7375                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     7621                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5960                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6241                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5674                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      291                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      196                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      199                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      189                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      164                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      163                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      177                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      175                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      137                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      188                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      212                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      160                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::45                      167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      200                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      238                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      157                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      252                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      198                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      131                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      111                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       81                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       70                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       45                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       79                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       69                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       43                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       24                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       30                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        62139                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      536.886657                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     331.247155                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     411.697741                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          13677     22.01%     22.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        10478     16.86%     38.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4968      7.99%     46.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2775      4.47%     51.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2441      3.93%     55.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1588      2.56%     57.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         3776      6.08%     63.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1174      1.89%     65.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        21262     34.22%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          62139                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5217                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        77.374545                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2903.927058                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           5214     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::46                      141                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      205                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      216                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      154                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      175                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      112                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      129                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      123                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      110                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      119                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      104                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       74                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       73                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       63                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       74                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       35                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       32                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        61611                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      541.558358                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     333.246769                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     417.180517                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          13396     21.74%     21.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        10505     17.05%     38.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5359      8.70%     47.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2621      4.25%     51.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2461      3.99%     55.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1425      2.31%     58.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1507      2.45%     60.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1351      2.19%     62.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        22986     37.31%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          61611                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5236                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        77.104660                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2917.579007                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           5233     99.94%     99.94% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5217                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5217                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        22.539965                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       19.244136                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       20.635763                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23            4619     88.54%     88.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31              29      0.56%     89.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39              25      0.48%     89.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47              38      0.73%     90.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55             214      4.10%     94.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63               9      0.17%     94.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71              11      0.21%     94.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79              34      0.65%     95.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87             184      3.53%     98.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-95               5      0.10%     99.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103              5      0.10%     99.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111             4      0.08%     99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135             6      0.12%     99.35% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total            5236                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5236                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        22.461994                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       19.033018                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       22.013556                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23            4631     88.45%     88.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31              42      0.80%     89.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39             243      4.64%     93.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47              21      0.40%     94.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55               6      0.11%     94.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63              10      0.19%     94.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71               6      0.11%     94.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79               2      0.04%     94.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87              20      0.38%     95.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95              23      0.44%     95.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103            185      3.53%     99.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111             2      0.04%     99.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119             3      0.06%     99.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127             1      0.02%     99.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135             7      0.13%     99.35% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::136-143             1      0.02%     99.37% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::144-151             1      0.02%     99.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-167             4      0.08%     99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-175             8      0.15%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183             4      0.08%     99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-191             3      0.06%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-199             2      0.04%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-207             2      0.04%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-215             6      0.12%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-263             2      0.04%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-279             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5217                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     4201005000                       # Total ticks spent queuing
-system.physmem.totMemAccLat               11770080000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2018420000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10406.67                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::152-159             3      0.06%     99.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167             2      0.04%     99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175            11      0.21%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183             1      0.02%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191             1      0.02%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199             2      0.04%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215             3      0.06%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231             7      0.13%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::264-271             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5236                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     3726058000                       # Total ticks spent queuing
+system.physmem.totMemAccLat               11296145500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2018690000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        9228.90                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29156.67                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          13.77                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           4.01                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       13.77                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        4.01                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  27978.90                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          13.88                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           4.04                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       13.88                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        4.04                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.98                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.46                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     363845                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     95291                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   90.13                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  81.02                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3599387.75                       # Average gap between requests
-system.physmem.pageHitRate                      88.07                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  233399880                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  127351125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1577604600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                378639360                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           122582793840                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            61740410985                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1071915840750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1258556040540                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              670.589641                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   1783024934000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     62670140000                       # Time in different power states
+system.physmem.avgWrQLen                        25.95                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     364089                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     95648                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   90.18                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  81.31                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3570649.70                       # Average gap between requests
+system.physmem.pageHitRate                      88.18                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  230882400                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  125977500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1577823000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                378632880                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           121619072640                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            56327619735                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1067810937000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1248070945155                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              670.272471                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   1776230272500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     62177440000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     31095099750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     23627517500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  236370960                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  128972250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1571130600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                383350320                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           122582793840                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            61477234290                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1072146705750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1258526558010                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              670.573928                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   1783410314000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     62670140000                       # Time in different power states
+system.physmem_1.actEnergy                  234896760                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  128167875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1571286600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                383486400                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           121619072640                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            56258103960                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1067871924000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1248066938235                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              670.270314                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   1776335363750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     62177440000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     30709733500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     23523591750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups                19569408                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          16632311                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            593173                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             12870136                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 5420664                       # Number of BTB hits
+system.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups                19539848                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          16614646                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            591620                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             12579114                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 5416634                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             42.118156                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1123230                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              42865                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups         6372302                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits             563108                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses          5809194                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted       264983                       # Number of mispredicted indirect branches.
+system.cpu.branchPred.BTBHitPct             43.060537                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1121926                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              41569                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         6087322                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits             563395                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses          5523927                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted       264320                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     11131372                       # DTB read hits
-system.cpu.dtb.read_misses                      49301                       # DTB read misses
-system.cpu.dtb.read_acv                           623                       # DTB read access violations
-system.cpu.dtb.read_accesses                   996761                       # DTB read accesses
-system.cpu.dtb.write_hits                     6776847                       # DTB write hits
-system.cpu.dtb.write_misses                     12217                       # DTB write misses
-system.cpu.dtb.write_acv                          418                       # DTB write access violations
-system.cpu.dtb.write_accesses                  345142                       # DTB write accesses
-system.cpu.dtb.data_hits                     17908219                       # DTB hits
-system.cpu.dtb.data_misses                      61518                       # DTB misses
-system.cpu.dtb.data_acv                          1041                       # DTB access violations
-system.cpu.dtb.data_accesses                  1341903                       # DTB accesses
-system.cpu.itb.fetch_hits                     1817383                       # ITB hits
-system.cpu.itb.fetch_misses                     10321                       # ITB misses
-system.cpu.itb.fetch_acv                          767                       # ITB acv
-system.cpu.itb.fetch_accesses                 1827704                       # ITB accesses
+system.cpu.dtb.read_hits                     11126873                       # DTB read hits
+system.cpu.dtb.read_misses                      49288                       # DTB read misses
+system.cpu.dtb.read_acv                           612                       # DTB read access violations
+system.cpu.dtb.read_accesses                   995471                       # DTB read accesses
+system.cpu.dtb.write_hits                     6773971                       # DTB write hits
+system.cpu.dtb.write_misses                     12183                       # DTB write misses
+system.cpu.dtb.write_acv                          423                       # DTB write access violations
+system.cpu.dtb.write_accesses                  345274                       # DTB write accesses
+system.cpu.dtb.data_hits                     17900844                       # DTB hits
+system.cpu.dtb.data_misses                      61471                       # DTB misses
+system.cpu.dtb.data_acv                          1035                       # DTB access violations
+system.cpu.dtb.data_accesses                  1340745                       # DTB accesses
+system.cpu.itb.fetch_hits                     1815480                       # ITB hits
+system.cpu.itb.fetch_misses                     10441                       # ITB misses
+system.cpu.itb.fetch_acv                          750                       # ITB acv
+system.cpu.itb.fetch_accesses                 1825921                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -347,148 +350,148 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numPwrStateTransitions               12876                       # Number of power state transitions
-system.cpu.pwrStateClkGateDist::samples          6438                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::mean     279467835.818577                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::stdev    439243252.658256                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1000-5e+10         6438    100.00%    100.00% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::min_value        81000                       # Distribution of time spent in the clock gated state
+system.cpu.numPwrStateTransitions               12878                       # Number of power state transitions
+system.cpu.pwrStateClkGateDist::samples          6439                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean     279534848.967231                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev    439378966.267034                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1000-5e+10         6439    100.00%    100.00% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::min_value        96000                       # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::max_value   2000000000                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::total            6438                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateResidencyTicks::ON     77580561000                       # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::CLK_GATED 1799213927000                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                        155167561                       # number of cpu cycles simulated
+system.cpu.pwrStateClkGateDist::total            6439                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateResidencyTicks::ON     62117170500                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 1799924892500                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                        124240781                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           30150844                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       85742172                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    19569408                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            7107002                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     116772481                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1681668                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                         87                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                29150                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        207083                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       421165                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          751                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   9930605                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                406777                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.icacheStallCycles           30188704                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       85612379                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    19539848                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            7101955                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      86725868                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1678156                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                         61                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                31498                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        207275                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       432547                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          339                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                   9909625                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                405389                       # Number of outstanding Icache misses that were squashed
 system.cpu.fetch.ItlbSquashes                       1                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          148422395                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.577690                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.864310                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples          118425370                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.722923                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.060283                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                132578342     89.33%     89.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1033201      0.70%     90.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  2106811      1.42%     91.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                   971505      0.65%     92.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2908700      1.96%     94.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                   663530      0.45%     94.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   808471      0.54%     95.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1037122      0.70%     95.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  6314713      4.25%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                102607090     86.64%     86.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1029926      0.87%     87.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  2106958      1.78%     89.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                   967243      0.82%     90.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2899427      2.45%     92.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                   665654      0.56%     93.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   809857      0.68%     93.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1032032      0.87%     94.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  6307183      5.33%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            148422395                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.126118                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.552578                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 24118440                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             111208587                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  10245196                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               2044112                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 806059                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved               738327                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 35573                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts               74062953                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                114064                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                 806059                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 25129468                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                79314805                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       20217508                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  11209636                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              11744917                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts               71031430                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                202187                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2134257                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 304114                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                7385918                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands            47856784                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups              85577316                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups         85396639                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            168224                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps              38182032                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  9674744                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            1729903                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         277398                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13945265                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             11667584                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             7222268                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1740236                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1128330                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   62719117                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2208284                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  60532785                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             94680                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        11944453                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined      5319004                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved        1547012                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     148422395                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.407841                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.141989                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            118425370                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.157274                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.689084                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 24239485                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              81100635                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  10246732                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               2034421                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 804096                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved               734883                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 35786                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts               73972445                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                113808                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 804096                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 25248689                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                52456334                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       19565246                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  11202200                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               9148803                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts               70966243                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                196842                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2117370                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 228092                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                4881037                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands            47806174                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups              85505184                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups         85324382                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            168350                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              38176913                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                  9629253                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            1728484                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         276268                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13926032                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             11656323                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             7221031                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1724354                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1093863                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   62666856                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2206869                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  60507866                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             96262                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        11897215                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined      5284366                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved        1545682                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     118425370                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.510937                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.257755                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           123871811     83.46%     83.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            10428219      7.03%     90.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             4419616      2.98%     93.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             3188761      2.15%     95.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             3243069      2.19%     97.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             1605515      1.08%     98.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1096686      0.74%     99.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              430660      0.29%     99.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              138058      0.09%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            93896241     79.29%     79.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            10410761      8.79%     88.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             4424184      3.74%     91.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             3178503      2.68%     94.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             3240709      2.74%     97.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             1606797      1.36%     98.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1097474      0.93%     99.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              434045      0.37%     99.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              136656      0.12%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       148422395                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       118425370                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  206261     16.62%     16.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     16.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     16.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     16.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     16.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     16.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     16.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     16.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     16.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     16.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     16.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     16.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     16.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     16.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     16.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     16.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     16.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     16.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     16.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     16.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     16.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     16.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     16.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     16.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     16.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     16.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     16.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     16.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     16.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 637065     51.34%     67.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                397617     32.04%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  206587     16.63%     16.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     16.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     16.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     16.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     16.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     16.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     16.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     16.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     16.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     16.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     16.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     16.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     16.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     16.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     16.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     16.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     16.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     16.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     16.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     16.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     16.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     16.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     16.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     16.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     16.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     16.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     16.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     16.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     16.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 638209     51.38%     68.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                397270     31.98%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass              7280      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              40910867     67.58%     67.60% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                62087      0.10%     67.70% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass              7277      0.01%      0.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              40893641     67.58%     67.60% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                62155      0.10%     67.70% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd               38559      0.06%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd               38558      0.06%     67.76% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.76% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.76% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.76% # Type of FU issued
@@ -514,95 +517,95 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.77% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.77% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.77% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.77% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             11677582     19.29%     87.06% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             6883616     11.37%     98.43% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess             949158      1.57%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             11671611     19.29%     87.06% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             6881999     11.37%     98.43% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess             948989      1.57%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               60532785                       # Type of FU issued
-system.cpu.iq.rate                           0.390112                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     1240943                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.020500                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          270086631                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes          76534291                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     58304379                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads              736956                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             359180                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       336827                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               61370896                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  395552                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           686477                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               60507866                       # Type of FU issued
+system.cpu.iq.rate                           0.487021                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     1242066                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.020527                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          240042364                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes          76433076                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     58286910                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads              737065                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             359346                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       336745                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               61347086                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  395569                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           690461                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      2574541                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         4210                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        22293                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       843973                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      2564224                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         3975                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        22069                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       843181                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        18024                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        466103                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        17987                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        463704                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 806059                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                75493298                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1202730                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts            68906340                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            204916                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              11667584                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              7222268                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1958885                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  46577                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                953145                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          22293                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         228745                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       630471                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               859216                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              59676170                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              11213777                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            856614                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 804096                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                49123510                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                920451                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts            68850753                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            204809                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              11656323                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              7221031                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1958834                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  45972                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                671584                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          22069                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         229357                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       628132                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               857489                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              59656852                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              11208773                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            851013                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       3978939                       # number of nop insts executed
-system.cpu.iew.exec_refs                     18023142                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                  9384066                       # Number of branches executed
-system.cpu.iew.exec_stores                    6809365                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.384592                       # Inst execution rate
-system.cpu.iew.wb_sent                       58885265                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      58641206                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  29760600                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  41260135                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       0.377922                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.721292                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts        12542077                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls          661272                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            769434                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    146251910                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.384089                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.283290                       # Number of insts commited each cycle
+system.cpu.iew.exec_nop                       3977028                       # number of nop insts executed
+system.cpu.iew.exec_refs                     18015122                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                  9379233                       # Number of branches executed
+system.cpu.iew.exec_stores                    6806349                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.480171                       # Inst execution rate
+system.cpu.iew.wb_sent                       58867691                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      58623655                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  29756177                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  41250197                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       0.471855                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.721358                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts        12492004                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls          661187                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            767634                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    116265516                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.483093                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.421972                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    126403677     86.43%     86.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      7969213      5.45%     91.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4187918      2.86%     94.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2256490      1.54%     96.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1756984      1.20%     97.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       633259      0.43%     97.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       482491      0.33%     98.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       524954      0.36%     98.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      2036924      1.39%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     96403146     82.92%     82.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      7978599      6.86%     89.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4192375      3.61%     93.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2264506      1.95%     95.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1757271      1.51%     96.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       632678      0.54%     97.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       482043      0.41%     97.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       513720      0.44%     98.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      2041178      1.76%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    146251910                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts             56173766                       # Number of instructions committed
-system.cpu.commit.committedOps               56173766                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    116265516                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts             56167063                       # Number of instructions committed
+system.cpu.commit.committedOps               56167063                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       15471338                       # Number of memory references committed
-system.cpu.commit.loads                       9093043                       # Number of loads committed
-system.cpu.commit.membars                      226379                       # Number of memory barriers committed
-system.cpu.commit.branches                    8441154                       # Number of branches committed
+system.cpu.commit.refs                       15469949                       # Number of memory references committed
+system.cpu.commit.loads                       9092099                       # Number of loads committed
+system.cpu.commit.membars                      226348                       # Number of memory barriers committed
+system.cpu.commit.branches                    8440307                       # Number of branches committed
 system.cpu.commit.fp_insts                     324384                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                  52023017                       # Number of committed integer instructions.
-system.cpu.commit.function_calls               740601                       # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass      3198096      5.69%      5.69% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu         36220454     64.48%     70.17% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult           60663      0.11%     70.28% # Class of committed instruction
+system.cpu.commit.int_insts                  52016709                       # Number of committed integer instructions.
+system.cpu.commit.function_calls               740521                       # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass      3197831      5.69%      5.69% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         36215597     64.48%     70.17% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult           60674      0.11%     70.28% # Class of committed instruction
 system.cpu.commit.op_class_0::IntDiv                0      0.00%     70.28% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd          38085      0.07%     70.35% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp              0      0.00%     70.35% # Class of committed instruction
@@ -630,554 +633,544 @@ system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     70.35% #
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     70.35% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     70.35% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead         9319422     16.59%     86.95% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite        6384252     11.37%     98.31% # Class of committed instruction
-system.cpu.commit.op_class_0::IprAccess        949158      1.69%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead         9318447     16.59%     86.94% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite        6383804     11.37%     98.31% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess        948989      1.69%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total          56173766                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               2036924                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    212681294                       # The number of ROB reads
-system.cpu.rob.rob_writes                   139606986                       # The number of ROB writes
-system.cpu.timesIdled                          557347                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         6745166                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   3598421416                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                    52982943                       # Number of Instructions Simulated
-system.cpu.committedOps                      52982943                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               2.928632                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.928632                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.341456                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.341456                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                 77864960                       # number of integer regfile reads
-system.cpu.int_regfile_writes                42584488                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                    166613                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   175794                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                 2001927                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 939529                       # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements           1405900                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.992670                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            12627832                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1406412                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              8.978757                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          36569500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.992670                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999986                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999986                       # Average percentage of cache occupancy
+system.cpu.commit.op_class_0::total          56167063                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               2041178                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    182633884                       # The number of ROB reads
+system.cpu.rob.rob_writes                   139481914                       # The number of ROB writes
+system.cpu.timesIdled                          555871                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         5815411                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   3599843346                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                    52976505                       # Number of Instructions Simulated
+system.cpu.committedOps                      52976505                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               2.345205                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.345205                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.426402                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.426402                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                 77842014                       # number of integer regfile reads
+system.cpu.int_regfile_writes                42572961                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                    166584                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   175742                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                 2001057                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 939419                       # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements           1405448                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.994324                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            12624146                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1405960                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              8.979022                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          26885500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.994324                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999989                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999989                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          414                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           57                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           41                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          415                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           95                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          67144149                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         67144149                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data      8017767                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         8017767                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      4181578                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4181578                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       212474                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       212474                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       215675                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       215675                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      12199345                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         12199345                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     12199345                       # number of overall hits
-system.cpu.dcache.overall_hits::total        12199345                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1817411                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1817411                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1966241                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1966241                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        23192                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        23192                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data           96                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total           96                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      3783652                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3783652                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3783652                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3783652                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  57696836500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  57696836500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 116764719993                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 116764719993                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    411714000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    411714000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data      1875000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total      1875000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 174461556493                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 174461556493                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 174461556493                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 174461556493                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data      9835178                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9835178                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6147819                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6147819                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       235666                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       235666                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       215771                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       215771                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15982997                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15982997                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15982997                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15982997                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.184787                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.184787                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.319827                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.319827                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.098410                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.098410                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000445                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000445                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.236730                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.236730                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.236730                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.236730                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31746.719097                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 31746.719097                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59384.744796                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 59384.744796                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17752.414626                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17752.414626                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19531.250000                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19531.250000                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 46109.302994                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 46109.302994                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 46109.302994                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 46109.302994                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs      7149027                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets         5119                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs            133846                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets              35                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    53.412332                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets   146.257143                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks       843569                       # number of writebacks
-system.cpu.dcache.writebacks::total            843569                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       717041                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       717041                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1676919                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1676919                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         6351                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total         6351                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      2393960                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      2393960                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      2393960                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      2393960                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1100370                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1100370                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       289322                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       289322                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        16841                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        16841                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           96                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total           96                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1389692                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1389692                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1389692                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1389692                       # number of overall MSHR misses
+system.cpu.dcache.tags.tag_accesses          67117469                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         67117469                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data      8015814                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         8015814                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4179783                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4179783                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       212605                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       212605                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       215671                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       215671                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      12195597                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         12195597                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     12195597                       # number of overall hits
+system.cpu.dcache.overall_hits::total        12195597                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1813103                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1813103                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1967603                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1967603                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        23208                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        23208                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data           90                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total           90                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      3780706                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3780706                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3780706                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3780706                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  42125006500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  42125006500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  80961387023                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  80961387023                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    351774000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    351774000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data      1258000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total      1258000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 123086393523                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 123086393523                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 123086393523                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 123086393523                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data      9828917                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9828917                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6147386                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6147386                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       235813                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       235813                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       215761                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       215761                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     15976303                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15976303                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15976303                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15976303                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.184466                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.184466                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.320071                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.320071                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.098417                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.098417                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000417                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000417                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.236645                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.236645                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.236645                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.236645                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23233.653300                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 23233.653300                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41147.216701                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 41147.216701                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15157.445708                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15157.445708                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13977.777778                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13977.777778                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 32556.457319                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 32556.457319                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 32556.457319                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 32556.457319                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs      4549830                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets         3359                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs            133574                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              36                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    34.062243                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    93.305556                       # average number of cycles each access was blocked
+system.cpu.dcache.writebacks::writebacks       843871                       # number of writebacks
+system.cpu.dcache.writebacks::total            843871                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       713283                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       713283                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1678038                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1678038                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         6508                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total         6508                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      2391321                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      2391321                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      2391321                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2391321                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1099820                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1099820                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       289565                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       289565                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        16700                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        16700                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           90                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total           90                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1389385                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1389385                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1389385                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1389385                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9599                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total         9599                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16529                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total        16529                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  44732838000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  44732838000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  18336828964                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  18336828964                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    214607500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    214607500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data      1779000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total      1779000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  63069666964                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  63069666964                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  63069666964                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  63069666964                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1528639000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1528639000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   1528639000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   1528639000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.111881                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.111881                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.047061                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.047061                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.071461                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.071461                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000445                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000445                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.086948                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.086948                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.086948                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.086948                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40652.542327                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40652.542327                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63378.619545                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63378.619545                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12743.156582                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12743.156582                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 18531.250000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 18531.250000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45383.917418                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 45383.917418                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45383.917418                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 45383.917418                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220582.828283                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220582.828283                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92482.243330                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92482.243330                       # average overall mshr uncacheable latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements           1074186                       # number of replacements
-system.cpu.icache.tags.tagsinuse           507.868793                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs             8786985                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1074694                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              8.176267                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       42323300500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   507.868793                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.991931                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.991931                       # Average percentage of cache occupancy
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9598                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total         9598                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16528                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total        16528                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  30901101000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  30901101000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12647974805                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  12647974805                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    208768500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    208768500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data      1168000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total      1168000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  43549075805                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  43549075805                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  43549075805                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  43549075805                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1535163500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1535163500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   1535163500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   1535163500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.111896                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.111896                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.047104                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.047104                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.070819                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.070819                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000417                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000417                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.086965                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.086965                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.086965                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.086965                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28096.507610                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28096.507610                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43679.225062                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43679.225062                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12501.107784                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12501.107784                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12977.777778                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12977.777778                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31344.138453                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 31344.138453                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31344.138453                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 31344.138453                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221524.314574                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221524.314574                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92882.593175                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92882.593175                       # average overall mshr uncacheable latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements           1075014                       # number of replacements
+system.cpu.icache.tags.tagsinuse           509.176961                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs             8765751                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1075522                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              8.150229                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       28399256500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   509.176961                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.994486                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.994486                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          508                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           73                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           69                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          366                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          135                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          300                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.992188                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          11005600                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         11005600                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst      8786985                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         8786985                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst       8786985                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          8786985                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst      8786985                       # number of overall hits
-system.cpu.icache.overall_hits::total         8786985                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1143615                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1143615                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1143615                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1143615                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1143615                       # number of overall misses
-system.cpu.icache.overall_misses::total       1143615                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  17001547978                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  17001547978                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  17001547978                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  17001547978                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  17001547978                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  17001547978                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst      9930600                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      9930600                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst      9930600                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      9930600                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst      9930600                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      9930600                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.115161                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.115161                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.115161                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.115161                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.115161                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.115161                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14866.496136                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14866.496136                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14866.496136                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14866.496136                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14866.496136                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14866.496136                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        12933                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          10985459                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         10985459                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst      8765751                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         8765751                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst       8765751                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total          8765751                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst      8765751                       # number of overall hits
+system.cpu.icache.overall_hits::total         8765751                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1143868                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1143868                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1143868                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1143868                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1143868                       # number of overall misses
+system.cpu.icache.overall_misses::total       1143868                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  15979138992                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  15979138992                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  15979138992                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  15979138992                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  15979138992                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  15979138992                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst      9909619                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      9909619                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst      9909619                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      9909619                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst      9909619                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      9909619                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.115430                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.115430                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.115430                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.115430                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.115430                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.115430                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13969.390692                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13969.390692                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13969.390692                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13969.390692                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13969.390692                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13969.390692                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         7656                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               342                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               228                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    37.815789                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    33.578947                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks      1074186                       # number of writebacks
-system.cpu.icache.writebacks::total           1074186                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        68615                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        68615                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        68615                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        68615                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        68615                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        68615                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1075000                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1075000                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1075000                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1075000                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1075000                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1075000                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  14900351984                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  14900351984                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  14900351984                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  14900351984                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  14900351984                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  14900351984                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.108251                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.108251                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.108251                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.108251                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.108251                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.108251                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13860.792543                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13860.792543                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13860.792543                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13860.792543                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13860.792543                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13860.792543                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements           338591                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65285.567334                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4253578                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           403759                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            10.534943                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       9186566000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 53024.055616                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  5255.268427                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  7006.243291                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.809083                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.080189                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.106907                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.996179                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65168                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          492                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3471                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3347                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2431                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55427                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994385                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         40379667                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        40379667                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackDirty_hits::writebacks       843569                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       843569                       # number of WritebackDirty hits
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-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data           88                       # number of SCUpgradeReq hits
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-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.562500                       # miss rate for UpgradeReq accesses
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-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 68437.500000                       # average SCUpgradeReq miss latency
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-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134753.460208                       # average ReadCleanReq miss latency
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-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128755.139234                       # average overall miss latency
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+system.cpu.l2cache.overall_misses::cpu.data       389226                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       404281                       # number of overall misses
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       387500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total       387500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10326275500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  10326275500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1274090500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total   1274090500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  20279625500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  20279625500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   1274090500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  30605901000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  31879991500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   1274090500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  30605901000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  31879991500                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks       843871                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total       843871                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks      1074552                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total      1074552                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data           82                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total           82                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data           90                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::total           90                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       300066                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       300066                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1075468                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total      1075468                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1105940                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      1105940                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst      1075468                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1406006                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2481474                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst      1075468                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1406006                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2481474                       # number of overall (read+write) accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.097561                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.097561                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.382246                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.382246                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.013999                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.013999                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.248230                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.248230                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.013999                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.276831                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.162920                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.013999                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.276831                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.162920                       # miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 48437.500000                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 48437.500000                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90029.342017                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90029.342017                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84629.060113                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84629.060113                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73871.151107                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73871.151107                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84629.060113                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78632.724946                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 78856.022173                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84629.060113                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78632.724946                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 78856.022173                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks        76108                       # number of writebacks
-system.cpu.l2cache.writebacks::total            76108                       # number of writebacks
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           45                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total           45                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            8                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            8                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       114791                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       114791                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        15028                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        15028                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       274518                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       274518                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        15028                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       389309                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       404337                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        15028                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       389309                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       404337                       # number of overall MSHR misses
+system.cpu.l2cache.writebacks::writebacks        76126                       # number of writebacks
+system.cpu.l2cache.writebacks::total            76126                       # number of writebacks
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total            1                       # number of overall MSHR hits
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            8                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total            8                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       114699                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       114699                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        15054                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        15054                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       274527                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       274527                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        15054                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       389226                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       404280                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        15054                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       389226                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       404280                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data         9599                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total         9599                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        16529                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total        16529                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      3100000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      3100000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       546000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       546000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  14869460001                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  14869460001                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1874795000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1874795000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  31368563001                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  31368563001                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1874795000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  46238023002                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  48112818002                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1874795000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  46238023002                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  48112818002                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1442000500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1442000500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   1442000500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   1442000500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.562500                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.562500                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.083333                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.083333                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.382857                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.382857                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.013984                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.013984                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.248067                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.248067                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.013984                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.276801                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.162968                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.013984                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.276801                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.162968                       # mshr miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68888.888889                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68888.888889                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        68250                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        68250                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129535.068089                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129535.068089                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124753.460208                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124753.460208                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114267.782080                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114267.782080                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124753.460208                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118769.468474                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118991.875594                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124753.460208                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118769.468474                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118991.875594                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208080.880231                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208080.880231                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87240.637667                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87240.637667                       # average overall mshr uncacheable latency
-system.cpu.toL2Bus.snoop_filter.tot_requests      4961718                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2480443                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         2186                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         1198                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1198                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data         9598                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::total         9598                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        16528                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total        16528                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       307500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       307500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   9179285500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   9179285500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1123478500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1123478500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  17540240000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  17540240000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1123478500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  26719525500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  27843004000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1123478500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  26719525500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  27843004000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1448524000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1448524000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   1448524000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   1448524000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.097561                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.097561                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.382246                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.382246                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.013998                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.013998                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.248230                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.248230                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.013998                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.276831                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.162919                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.013998                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.276831                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.162919                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 38437.500000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 38437.500000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80029.342017                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80029.342017                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74629.899030                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74629.899030                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63892.586157                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63892.586157                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74629.899030                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68647.843412                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68870.594637                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74629.899030                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68647.843412                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68870.594637                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209022.222222                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 209022.222222                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87640.609874                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87640.609874                       # average overall mshr uncacheable latency
+system.cpu.toL2Bus.snoop_filter.tot_requests      4962480                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2480820                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         2159                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops          950                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops          950                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadReq           6930                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2188672                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq          9599                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp         9599                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       961198                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean      1074186                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       824987                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           80                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq           96                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp          176                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       299827                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       299827                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      1075000                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1106802                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError           43                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq        41552                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3223811                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4252378                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7476189                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    137523904                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    144052988                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          281576892                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      422541                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic               7562240                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples      2920171                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.001264                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.035530                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp       2188821                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq          9598                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp         9598                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       919997                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      1075014                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       824089                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq           82                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq           90                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp          172                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       300066                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       300066                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1075840                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1106100                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError           45                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq          254                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3226322                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4251016                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7477338                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    137630848                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    144043380                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          281674228                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      339580                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic               4905856                       # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples      2837598                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.001208                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.034736                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            2916480     99.87%     99.87% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               3691      0.13%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2834170     99.88%     99.88% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               3428      0.12%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        2920171                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4411678000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        2837598                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4413188000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy       291883                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1613546403                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1614811393                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2121618679                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2121037981                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -1191,12 +1184,12 @@ system.disk2.dma_read_txs                           0                       # Nu
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.iobus.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
+system.iobus.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
 system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
 system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               51151                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              51151                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5054                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::WriteReq               51150                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              51150                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5052                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1006                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
@@ -1205,11 +1198,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        1812
 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        33058                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        33056                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  116508                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20216                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  116506                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20208                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2717                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
@@ -1218,50 +1211,50 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9060
 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        44156                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total        44148                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2705764                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              5364000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  2705756                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy              5361000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               818000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               820500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer6.occupancy                11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer22.occupancy              177000                       # Layer occupancy (ticks)
+system.iobus.reqLayer22.occupancy              177500                       # Layer occupancy (ticks)
 system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            14181000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            14040000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy             2178000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy             2177500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy             6052000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy             6050500                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy               91500                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           215700163                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           216173801                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            23459000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            23458000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer1.occupancy            41946000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
 system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.249213                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.258860                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1726973394000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.249213                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.078076                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.078076                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1712294555000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.258860                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.078679                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.078679                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
 system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
 system.iocache.tags.data_accesses              375525                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
+system.iocache.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
 system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
@@ -1270,14 +1263,14 @@ system.iocache.demand_misses::tsunami.ide        41725                       # n
 system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
 system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
 system.iocache.overall_misses::total            41725                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     21828883                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     21828883                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::tsunami.ide   5246443280                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   5246443280                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide   5268272163                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   5268272163                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide   5268272163                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   5268272163                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::tsunami.ide     21845883                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     21845883                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::tsunami.ide   4858784918                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4858784918                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide   4880630801                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   4880630801                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide   4880630801                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   4880630801                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
@@ -1294,19 +1287,19 @@ system.iocache.demand_miss_rate::tsunami.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126178.514451                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 126178.514451                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126262.112052                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 126262.112052                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 126261.765440                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 126261.765440                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 126261.765440                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 126261.765440                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             7                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126276.780347                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 126276.780347                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116932.636648                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 116932.636648                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 116971.379293                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 116971.379293                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 116971.379293                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 116971.379293                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs             8                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    1                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs            7                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs            8                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.writebacks::writebacks           41512                       # number of writebacks
 system.iocache.writebacks::total                41512                       # number of writebacks
@@ -1318,14 +1311,14 @@ system.iocache.demand_mshr_misses::tsunami.ide        41725
 system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13178883                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     13178883                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   3167048471                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   3167048471                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide   3180227354                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   3180227354                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide   3180227354                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   3180227354                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13195883                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     13195883                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   2778792164                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2778792164                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide   2791988047                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   2791988047                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide   2791988047                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   2791988047                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1334,70 +1327,75 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76178.514451                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 76178.514451                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76218.917766                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76218.917766                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76218.750246                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 76218.750246                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76218.750246                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 76218.750246                       # average overall mshr miss latency
-system.membus.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76276.780347                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 76276.780347                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66875.052079                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66875.052079                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66914.033481                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 66914.033481                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66914.033481                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 66914.033481                       # average overall mshr miss latency
+system.membus.snoop_filter.tot_requests        825555                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests       380464                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests          414                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
+system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadReq                6930                       # Transaction distribution
-system.membus.trans_dist::ReadResp             296606                       # Transaction distribution
-system.membus.trans_dist::WriteReq               9599                       # Transaction distribution
-system.membus.trans_dist::WriteResp              9599                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       117620                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           261864                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              278                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              8                       # Transaction distribution
+system.membus.trans_dist::ReadResp             296639                       # Transaction distribution
+system.membus.trans_dist::WriteReq               9598                       # Transaction distribution
+system.membus.trans_dist::WriteResp              9598                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       117638                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           261892                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              135                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               3                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            114558                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           114558                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        289719                       # Transaction distribution
-system.membus.trans_dist::BadAddressError           43                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            114572                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           114572                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        289754                       # Transaction distribution
+system.membus.trans_dist::BadAddressError           45                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33058                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1145930                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           86                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1179074                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33056                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1145919                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           90                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1179065                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83425                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total        83425                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1262499                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44156                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30713088                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30757244                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total                1262490                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44148                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30717248                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30761396                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2657728                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2657728                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                33414972                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                33419124                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              438                       # Total snoops (count)
 system.membus.snoopTraffic                      27840                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            842137                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::samples            462541                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.001500                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.038706                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  842137    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  461847     99.85%     99.85% # Request fanout histogram
+system.membus.snoop_fanout::1                     694      0.15%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              842137                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            28883000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              462541                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            28740000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1314388710                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1314155780                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy               54000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy               57000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2138626000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2139053000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 system.membus.respLayer2.occupancy             918617                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
-system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
-system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
-system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
-system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -1429,52 +1427,52 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
-system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
-system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
-system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1876794488000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
+system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1862042063000                       # Cumulative time (in ticks) in various power states
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     6438                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     211036                       # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0                    74670     40.97%     40.97% # number of times we switched to this ipl
+system.cpu.kern.inst.quiesce                     6439                       # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei                     210996                       # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0                    74658     40.97%     40.97% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::21                     131      0.07%     41.04% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22                    1881      1.03%     42.07% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  105584     57.93%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               182266                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73303     49.32%     49.32% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count::22                    1880      1.03%     42.07% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31                  105558     57.93%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               182227                       # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0                     73291     49.32%     49.32% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::21                      131      0.09%     49.41% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22                     1881      1.27%     50.68% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73303     49.32%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                148618                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1818987792000     96.92%     96.92% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                67503500      0.00%     96.92% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               563118000      0.03%     96.95% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             57175249500      3.05%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1876793663000                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981693                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_good::22                     1880      1.27%     50.68% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::31                    73291     49.32%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total                148593                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0             1818067214500     97.64%     97.64% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                67498000      0.00%     97.64% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               564111500      0.03%     97.67% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             43342412500      2.33%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1862041236500                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0                  0.981690                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.694262                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.815391                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.694320                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.815428                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -1513,29 +1511,29 @@ system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # nu
 system.cpu.kern.callpal::swpctx                  4176      2.18%      2.18% # number of callpals executed
 system.cpu.kern.callpal::tbi                       54      0.03%      2.21% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.21% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175147     91.23%     93.43% # number of callpals executed
-system.cpu.kern.callpal::rdps                    6785      3.53%     96.97% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175110     91.22%     93.43% # number of callpals executed
+system.cpu.kern.callpal::rdps                    6784      3.53%     96.97% # number of callpals executed
 system.cpu.kern.callpal::wrkgp                      1      0.00%     96.97% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
 system.cpu.kern.callpal::rdusp                      9      0.00%     96.98% # number of callpals executed
 system.cpu.kern.callpal::whami                      2      0.00%     96.98% # number of callpals executed
-system.cpu.kern.callpal::rti                     5106      2.66%     99.64% # number of callpals executed
+system.cpu.kern.callpal::rti                     5105      2.66%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 191994                       # number of callpals executed
-system.cpu.kern.mode_switch::kernel              5854                       # number of protection mode switches
-system.cpu.kern.mode_switch::user                1740                       # number of protection mode switches
-system.cpu.kern.mode_switch::idle                2094                       # number of protection mode switches
-system.cpu.kern.mode_good::kernel                1910                      
-system.cpu.kern.mode_good::user                  1740                      
+system.cpu.kern.callpal::total                 191955                       # number of callpals executed
+system.cpu.kern.mode_switch::kernel              5851                       # number of protection mode switches
+system.cpu.kern.mode_switch::user                1739                       # number of protection mode switches
+system.cpu.kern.mode_switch::idle                2096                       # number of protection mode switches
+system.cpu.kern.mode_good::kernel                1909                      
+system.cpu.kern.mode_good::user                  1739                      
 system.cpu.kern.mode_good::idle                   170                      
-system.cpu.kern.mode_switch_good::kernel     0.326273                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::kernel     0.326269                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.081184                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.394302                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        30164955000      1.61%      1.61% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           2918722500      0.16%      1.76% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1843709977500     98.24%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_switch_good::idle       0.081107                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      0.394177                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        29461996000      1.58%      1.58% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           2701361000      0.15%      1.73% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1829877871500     98.27%    100.00% # number of ticks spent at the given mode
 system.cpu.kern.swap_context                     4177                       # number of times the context was actually changed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
index d7da6ec5c..848d1d5ab 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
@@ -1,132 +1,132 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.841599                       # Number of seconds simulated
-sim_ticks                                1841599161000                       # Number of ticks simulated
-final_tick                               1841599161000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.842573                       # Number of seconds simulated
+sim_ticks                                1842573194000                       # Number of ticks simulated
+final_tick                               1842573194000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 220916                       # Simulator instruction rate (inst/s)
-host_op_rate                                   220916                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             6097623299                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 332848                       # Number of bytes of host memory used
-host_seconds                                   302.02                       # Real time elapsed on the host
-sim_insts                                    66720805                       # Number of instructions simulated
-sim_ops                                      66720805                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 206946                       # Simulator instruction rate (inst/s)
+host_op_rate                                   206946                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5715573944                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 339016                       # Number of bytes of host memory used
+host_seconds                                   322.38                       # Real time elapsed on the host
+sim_insts                                    66714903                       # Number of instructions simulated
+sim_ops                                      66714903                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.inst           472448                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         20115392                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           147008                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          2145088                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst           298752                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          2611904                       # Number of bytes read from this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu0.inst           469248                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         20132864                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           150208                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          2123008                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst           298368                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          2617024                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             25791552                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       472448                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       147008                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst       298752                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          918208                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7488832                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7488832                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst              7382                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            314303                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              2297                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             33517                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst              4668                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data             40811                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             25791680                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       469248                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       150208                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst       298368                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          917824                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7488960                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7488960                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst              7332                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            314576                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              2347                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             33172                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst              4662                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data             40891                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                402993                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          117013                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               117013                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              256542                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            10922785                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               79826                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             1164796                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst              162224                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data             1418280                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::total                402995                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          117015                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               117015                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              254670                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            10926493                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               81521                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             1152197                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst              161930                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data             1420309                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::tsunami.ide               521                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                14004976                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         256542                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          79826                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst         162224                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             498593                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4066483                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4066483                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4066483                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             256542                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           10922785                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              79826                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            1164796                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst             162224                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data            1418280                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                13997642                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         254670                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          81521                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst         161930                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             498121                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4064403                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4064403                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4064403                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             254670                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           10926493                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              81521                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            1152197                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst             161930                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data            1420309                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::tsunami.ide              521                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               18071459                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         81308                       # Number of read requests accepted
-system.physmem.writeReqs                        46917                       # Number of write requests accepted
-system.physmem.readBursts                       81308                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      46917                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  5202560                       # Total number of bytes read from DRAM
+system.physmem.bw_total::total               18062045                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         81087                       # Number of read requests accepted
+system.physmem.writeReqs                        46731                       # Number of write requests accepted
+system.physmem.readBursts                       81087                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      46731                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  5188416                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                      1152                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   3000896                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   5203712                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                3002688                       # Total written bytes from the system interface side
+system.physmem.bytesWritten                   2989056                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   5189568                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                2990784                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                       18                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                4879                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                4860                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                4840                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                5116                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                5145                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                5201                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                5134                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                5033                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                5242                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                4887                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               5474                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               5136                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               4904                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               4973                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                4742                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                4753                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                4837                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                5252                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                5163                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                5213                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                5141                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                5015                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                5238                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                4880                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               5475                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               5008                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               4911                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               4972                       # Per bank write bursts
 system.physmem.perBankRdBursts::14               5564                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               4902                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                2770                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                2825                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                2866                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                3058                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                2994                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                2828                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                3105                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                2723                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                3290                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                2741                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               4905                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                2655                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                2725                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                2864                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                3189                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                3009                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                2838                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                3113                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                2705                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                3288                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                2746                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               3262                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               2912                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               2689                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               2734                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               3349                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               2743                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               2782                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               2699                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               2735                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               3348                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               2746                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           6                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1840587284000                       # Total gap between requests
+system.physmem.numWrRetry                           3                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1841561317000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   81308                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   81087                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  46917                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     63682                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      7542                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      5539                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      4493                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        24                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  46731                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     63494                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      7529                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      5570                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      4444                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        22                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
@@ -154,14 +154,14 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                        78                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                        56                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                        79                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                        57                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::2                        50                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::3                        45                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::4                        44                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::5                        42                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::6                        42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                        37                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                        38                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::8                        36                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::9                        36                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::10                       36                       # What write queue length does an incoming req see
@@ -169,191 +169,189 @@ system.physmem.wrQLenPdf::11                       36                       # Wh
 system.physmem.wrQLenPdf::12                       36                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                       36                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      762                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1293                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     1745                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      774                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1344                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     1705                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::18                     1920                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     2366                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     2522                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     2976                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     3539                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     2746                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     3095                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     3372                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     3090                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     2791                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     2903                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     2624                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     2247                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     2267                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     2163                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      143                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       94                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       60                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       83                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       74                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                       67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       51                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                       72                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                       83                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      102                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     2365                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::24                     3153                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     3420                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     3068                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     2749                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     2819                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     2602                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     2211                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     2272                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     2180                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      109                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       90                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       58                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                       49                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                       48                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                       54                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                       49                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::41                       50                       # What write queue length does an incoming req see
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 system.physmem.wrQLenPdf::44                       89                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       40                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       68                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       69                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       85                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       61                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       46                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       39                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       29                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       34                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       26                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       13                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        21624                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      379.368110                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     215.960357                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     378.240859                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127           7179     33.20%     33.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         4878     22.56%     55.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         1948      9.01%     64.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1045      4.83%     69.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          873      4.04%     73.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          450      2.08%     75.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          417      1.93%     77.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          373      1.72%     79.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         4461     20.63%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          21624                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          2049                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        39.666179                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      981.071588                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           2047     99.90%     99.90% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::45                       66                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                       70                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                       78                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       62                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       64                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       37                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       35                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       35                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       32                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       31                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       34                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       26                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       36                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       12                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        7                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        21474                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      380.808047                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     217.054900                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     378.494212                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           7105     33.09%     33.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         4792     22.32%     55.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         1974      9.19%     64.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1058      4.93%     69.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          851      3.96%     73.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          468      2.18%     75.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          396      1.84%     77.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          380      1.77%     79.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         4450     20.72%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          21474                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          2032                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        39.890256                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      985.167686                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           2030     99.90%     99.90% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-4095            1      0.05%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::43008-45055            1      0.05%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            2049                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          2049                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        22.883846                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.590123                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       22.999579                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                33      1.61%      1.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                 8      0.39%      2.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11                1      0.05%      2.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15               3      0.15%      2.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            1695     82.72%     84.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              48      2.34%     87.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              10      0.49%     87.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              15      0.73%     88.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              91      4.44%     92.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39               8      0.39%     93.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43               1      0.05%     93.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               4      0.20%     93.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51               2      0.10%     93.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               3      0.15%     93.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               2      0.10%     93.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               2      0.10%     94.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67               2      0.10%     94.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               1      0.05%     94.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               2      0.10%     94.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              13      0.63%     94.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               4      0.20%     95.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99              77      3.76%     98.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.05%     98.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             2      0.10%     98.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             2      0.10%     99.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.05%     99.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             2      0.10%     99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.05%     99.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.05%     99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             1      0.05%     99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.05%     99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             1      0.05%     99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             4      0.20%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-187             1      0.05%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             1      0.05%     99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::196-199             1      0.05%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-227             4      0.20%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            2049                       # Writes before turning the bus around for reads
-system.physmem.totQLat                      885699750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                2409887250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    406450000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10895.56                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            2032                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          2032                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        22.984252                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.590209                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       23.991562                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                34      1.67%      1.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                 7      0.34%      2.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11                3      0.15%      2.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15               2      0.10%      2.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            1678     82.58%     84.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              43      2.12%     86.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              12      0.59%     87.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              18      0.89%     88.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             100      4.92%     93.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39               2      0.10%     93.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43               5      0.25%     93.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               3      0.15%     93.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51               1      0.05%     93.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               2      0.10%     94.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               1      0.05%     94.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               2      0.10%     94.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67               2      0.10%     94.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               1      0.05%     94.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               1      0.05%     94.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               7      0.34%     94.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               2      0.10%     94.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               2      0.10%     94.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99              82      4.04%     98.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.05%     98.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             2      0.10%     99.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             2      0.10%     99.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             1      0.05%     99.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             2      0.10%     99.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.05%     99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             2      0.10%     99.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-187             1      0.05%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             1      0.05%     99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::220-223             1      0.05%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227             7      0.34%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::248-251             1      0.05%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            2032                       # Writes before turning the bus around for reads
+system.physmem.totQLat                      878117500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                2398161250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    405345000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10831.73                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29645.56                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.83                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.63                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.83                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.63                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29581.73                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.82                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.62                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.82                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.62                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.14                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         7.69                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      69553                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     37002                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   85.56                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  78.87                       # Row buffer hit rate for writes
-system.physmem.avgGap                     14354355.89                       # Average gap between requests
-system.physmem.pageHitRate                      83.11                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                   80733240                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                   43918875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 313622400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                150135120                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            89060552880                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            35737868835                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           798596823000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             923983654350                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              667.983586                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   1308907007000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     45531980000                       # Time in different power states
+system.physmem.avgWrQLen                         7.72                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      69338                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     36961                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   85.53                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  79.09                       # Row buffer hit rate for writes
+system.physmem.avgGap                     14407683.71                       # Average gap between requests
+system.physmem.pageHitRate                      83.18                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                   80173800                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                   43646625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 312904800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                149675040                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            89124122880                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            35767572390                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           797968033500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             923446129035                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.080170                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   1309854007000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     45564480000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      9262769000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      9260985250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                   82744200                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                   44962500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 320439600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                153705600                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            89060552880                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            35470252125                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           802756182000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             927888838905                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              667.649647                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   1309307344000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     45531980000                       # Time in different power states
+system.physmem_1.actEnergy                   82169640                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                   44677875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 319433400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                152966880                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            89124122880                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            35452017540                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           802163554500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             927338942715                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              667.741345                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   1310300112750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     45564480000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      8896844750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      8843530000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dtb.fetch_hits                          0                       # ITB hits
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     4808616                       # DTB read hits
-system.cpu0.dtb.read_misses                      6111                       # DTB read misses
+system.cpu0.dtb.read_hits                     4806164                       # DTB read hits
+system.cpu0.dtb.read_misses                      6050                       # DTB read misses
 system.cpu0.dtb.read_acv                          122                       # DTB read access violations
-system.cpu0.dtb.read_accesses                  428608                       # DTB read accesses
-system.cpu0.dtb.write_hits                    3411554                       # DTB write hits
-system.cpu0.dtb.write_misses                      685                       # DTB write misses
+system.cpu0.dtb.read_accesses                  427464                       # DTB read accesses
+system.cpu0.dtb.write_hits                    3411517                       # DTB write hits
+system.cpu0.dtb.write_misses                      679                       # DTB write misses
 system.cpu0.dtb.write_acv                          84                       # DTB write access violations
-system.cpu0.dtb.write_accesses                 164458                       # DTB write accesses
-system.cpu0.dtb.data_hits                     8220170                       # DTB hits
-system.cpu0.dtb.data_misses                      6796                       # DTB misses
+system.cpu0.dtb.write_accesses                 163616                       # DTB write accesses
+system.cpu0.dtb.data_hits                     8217681                       # DTB hits
+system.cpu0.dtb.data_misses                      6729                       # DTB misses
 system.cpu0.dtb.data_acv                          206                       # DTB access violations
-system.cpu0.dtb.data_accesses                  593066                       # DTB accesses
-system.cpu0.itb.fetch_hits                    2729287                       # ITB hits
-system.cpu0.itb.fetch_misses                     3056                       # ITB misses
+system.cpu0.dtb.data_accesses                  591080                       # DTB accesses
+system.cpu0.itb.fetch_hits                    2722802                       # ITB hits
+system.cpu0.itb.fetch_misses                     3018                       # ITB misses
 system.cpu0.itb.fetch_acv                         101                       # ITB acv
-system.cpu0.itb.fetch_accesses                2732343                       # ITB accesses
+system.cpu0.itb.fetch_accesses                2725820                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -366,42 +364,42 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numPwrStateTransitions               6508                       # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples         3254                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean    553026714.363860                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev   1352809149.832599                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10         3254    100.00%    100.00% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::min_value       213500                       # Distribution of time spent in the clock gated state
+system.cpu0.numPwrStateTransitions               6514                       # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples         3257                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean    552798033.019036                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev   1352688826.519808                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10         3257    100.00%    100.00% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::min_value       142000                       # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::max_value   3905515000                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total           3254                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON    42050232460                       # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 1799548928540                       # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles                       928788202                       # number of cpu cycles simulated
+system.cpu0.pwrStateClkGateDist::total           3257                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON    42110000457                       # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 1800463193543                       # Cumulative time (in ticks) in various power states
+system.cpu0.numCycles                       928783152                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    6425                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    211368                       # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0                   74795     40.97%     40.97% # number of times we switched to this ipl
+system.cpu0.kern.inst.quiesce                    6426                       # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei                    211388                       # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0                   74798     40.97%     40.97% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::21                    203      0.11%     41.08% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22                   1878      1.03%     42.11% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                 105681     57.89%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              182557                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    73428     49.30%     49.30% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_count::22                   1879      1.03%     42.11% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                 105692     57.89%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              182572                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0                    73431     49.30%     49.30% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::21                     203      0.14%     49.44% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22                    1878      1.26%     50.70% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   73428     49.30%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total               148937                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1818752965500     98.76%     98.76% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               39793500      0.00%     98.76% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              370197000      0.02%     98.78% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            22435471000      1.22%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1841598427000                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.981723                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_good::22                    1879      1.26%     50.70% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31                   73431     49.30%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total               148944                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0            1819731049500     98.76%     98.76% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               39465000      0.00%     98.76% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              370305500      0.02%     98.78% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            22431640000      1.22%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1842572460000                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0                 0.981724                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.694808                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.815838                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31                0.694764                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.815810                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.syscall::2                         8      2.45%      2.45% # number of syscalls executed
 system.cpu0.kern.syscall::3                        30      9.20%     11.66% # number of syscalls executed
 system.cpu0.kern.syscall::4                         4      1.23%     12.88% # number of syscalls executed
@@ -440,500 +438,498 @@ system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.00% # nu
 system.cpu0.kern.callpal::swpctx                 4175      2.17%      2.17% # number of callpals executed
 system.cpu0.kern.callpal::tbi                      54      0.03%      2.20% # number of callpals executed
 system.cpu0.kern.callpal::wrent                     7      0.00%      2.21% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               175300     91.20%     93.41% # number of callpals executed
-system.cpu0.kern.callpal::rdps                   6782      3.53%     96.94% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               175313     91.20%     93.41% # number of callpals executed
+system.cpu0.kern.callpal::rdps                   6783      3.53%     96.94% # number of callpals executed
 system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.94% # number of callpals executed
 system.cpu0.kern.callpal::wrusp                     7      0.00%     96.94% # number of callpals executed
 system.cpu0.kern.callpal::rdusp                     9      0.00%     96.94% # number of callpals executed
 system.cpu0.kern.callpal::whami                     2      0.00%     96.95% # number of callpals executed
-system.cpu0.kern.callpal::rti                    5175      2.69%     99.64% # number of callpals executed
+system.cpu0.kern.callpal::rti                    5176      2.69%     99.64% # number of callpals executed
 system.cpu0.kern.callpal::callsys                 515      0.27%     99.91% # number of callpals executed
 system.cpu0.kern.callpal::imb                     181      0.09%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                192212                       # number of callpals executed
+system.cpu0.kern.callpal::total                192227                       # number of callpals executed
 system.cpu0.kern.mode_switch::kernel             5922                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1737                       # number of protection mode switches
-system.cpu0.kern.mode_switch::idle               2094                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1906                      
-system.cpu0.kern.mode_good::user                 1737                      
+system.cpu0.kern.mode_switch::user               1738                       # number of protection mode switches
+system.cpu0.kern.mode_switch::idle               2095                       # number of protection mode switches
+system.cpu0.kern.mode_good::kernel               1907                      
+system.cpu0.kern.mode_good::user                 1738                      
 system.cpu0.kern.mode_good::idle                  169                      
-system.cpu0.kern.mode_switch_good::kernel     0.321851                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel     0.322020                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::idle      0.080707                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.390854                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel       29766458500      1.62%      1.62% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          2570000000      0.14%      1.76% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::idle        1809261966500     98.24%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::idle      0.080668                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::total     0.390979                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel       29732108000      1.61%      1.61% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          2585852000      0.14%      1.75% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::idle        1810254498000     98.25%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.swap_context                    4176                       # number of times the context was actually changed
-system.cpu0.committedInsts                   30028359                       # Number of instructions committed
-system.cpu0.committedOps                     30028359                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             27949209                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                163605                       # Number of float alu accesses
-system.cpu0.num_func_calls                     796078                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      3573160                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    27949209                       # number of integer instructions
-system.cpu0.num_fp_insts                       163605                       # number of float instructions
-system.cpu0.num_int_register_reads           38472094                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          20603467                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads               84586                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes              86140                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                      8249833                       # number of memory refs
-system.cpu0.num_load_insts                    4829697                       # Number of load instructions
-system.cpu0.num_store_insts                   3420136                       # Number of store instructions
-system.cpu0.num_idle_cycles              907169648.432742                       # Number of idle cycles
-system.cpu0.num_busy_cycles              21618553.567258                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.023276                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.976724                       # Percentage of idle cycles
-system.cpu0.Branches                          4625246                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass              1572413      5.24%      5.24% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 19517057     64.98%     70.22% # Class of executed instruction
-system.cpu0.op_class::IntMult                   31821      0.11%     70.32% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     70.32% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                  12868      0.04%     70.36% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     70.36% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     70.36% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     70.36% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                   1602      0.01%     70.37% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     70.37% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     70.37% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     70.37% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     70.37% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     70.37% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     70.37% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     70.37% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     70.37% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     70.37% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     70.37% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     70.37% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     70.37% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     70.37% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     70.37% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     70.37% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     70.37% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     70.37% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc                 0      0.00%     70.37% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     70.37% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     70.37% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     70.37% # Class of executed instruction
-system.cpu0.op_class::MemRead                 4960051     16.51%     86.88% # Class of executed instruction
-system.cpu0.op_class::MemWrite                3423231     11.40%     98.28% # Class of executed instruction
-system.cpu0.op_class::IprAccess                516318      1.72%    100.00% # Class of executed instruction
+system.cpu0.committedInsts                   30003730                       # Number of instructions committed
+system.cpu0.committedOps                     30003730                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             27925731                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                163756                       # Number of float alu accesses
+system.cpu0.num_func_calls                     796110                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      3567009                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    27925731                       # number of integer instructions
+system.cpu0.num_fp_insts                       163756                       # number of float instructions
+system.cpu0.num_int_register_reads           38434691                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          20585928                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads               84641                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes              86208                       # number of times the floating registers were written
+system.cpu0.num_mem_refs                      8247251                       # number of memory refs
+system.cpu0.num_load_insts                    4827160                       # Number of load instructions
+system.cpu0.num_store_insts                   3420091                       # Number of store instructions
+system.cpu0.num_idle_cycles              907147772.055444                       # Number of idle cycles
+system.cpu0.num_busy_cycles              21635379.944556                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.023294                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.976706                       # Percentage of idle cycles
+system.cpu0.Branches                          4619076                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass              1571431      5.24%      5.24% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 19496987     64.97%     70.20% # Class of executed instruction
+system.cpu0.op_class::IntMult                   31839      0.11%     70.31% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     70.31% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                  12846      0.04%     70.35% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     70.35% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     70.35% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     70.35% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                   1596      0.01%     70.36% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     70.36% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     70.36% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     70.36% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     70.36% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     70.36% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     70.36% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     70.36% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     70.36% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     70.36% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     70.36% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     70.36% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     70.36% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     70.36% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     70.36% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     70.36% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     70.36% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     70.36% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc                 0      0.00%     70.36% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     70.36% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     70.36% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     70.36% # Class of executed instruction
+system.cpu0.op_class::MemRead                 4957504     16.52%     86.88% # Class of executed instruction
+system.cpu0.op_class::MemWrite                3423190     11.41%     98.28% # Class of executed instruction
+system.cpu0.op_class::IprAccess                515272      1.72%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  30035361                       # Class of executed instruction
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements          1394566                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.997816                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           13521910                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1395078                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs             9.692583                       # Average number of references to valid blocks.
+system.cpu0.op_class::total                  30010665                       # Class of executed instruction
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.tags.replacements          1394329                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.997818                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           13513290                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1394841                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs             9.688050                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         10840000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   257.707457                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data    77.564418                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data   176.725941                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.503335                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.151493                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.345168                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   257.899506                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data    77.334042                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data   176.764270                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.503710                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.151043                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data     0.345243                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999996                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0          187                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          257                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          256                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         64423039                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        64423039                       # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data      3984765                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      1069804                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data      2772856                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        7827425                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3123452                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data       820342                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data      1358314                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       5302108                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       113859                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        19272                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        59831                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       192962                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       122665                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data        21310                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu2.data        55350                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       199325                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      7108217                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data      1890146                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data      4131170                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        13129533                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      7108217                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data      1890146                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data      4131170                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       13129533                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       711198                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data        95313                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data       558903                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1365414                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       164044                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data        43456                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data       643142                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       850642                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9353                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         2169                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         7565                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        19087                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data            1                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu2.data           26                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total           27                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       875242                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data       138769                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data      1202045                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       2216056                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       875242                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data       138769                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data      1202045                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2216056                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2254809000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   8236813000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  10491622000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1752799000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  19370305557                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  21123104557                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     28695000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    118437000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    147132000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data       416000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total       416000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data   4007608000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data  27607118557                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  31614726557                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data   4007608000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data  27607118557                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  31614726557                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      4695963                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      1165117                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data      3331759                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      9192839                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      3287496                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data       863798                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data      2001456                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      6152750                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       123212                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        21441                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        67396                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       212049                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       122666                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        21310                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        55376                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       199352                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data      7983459                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data      2028915                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data      5333215                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     15345589                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data      7983459                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data      2028915                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data      5333215                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     15345589                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.151449                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.081806                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.167750                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.148530                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.049899                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.050308                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.321337                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.138254                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.075910                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.101161                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.112247                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.090012                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000008                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000470                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000135                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.109632                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.068396                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.225388                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.144410                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.109632                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.068396                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.225388                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.144410                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23656.888357                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14737.464283                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total  7683.839480                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40335.028535                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30118.240695                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 24831.955813                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13229.598893                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 15655.915400                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  7708.492691                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data        16000                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15407.407407                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 28879.706563                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 22966.792888                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 14266.212838                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 28879.706563                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 22966.792888                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 14266.212838                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs       997927                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets         2476                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            58775                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets             19                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    16.978766                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets   130.315789                       # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks       836681                       # number of writebacks
-system.cpu0.dcache.writebacks::total           836681                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       289767                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       289767                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       548232                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total       548232                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         2018                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total         2018                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data       837999                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       837999                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data       837999                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       837999                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        95313                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       269136                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       364449                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        43456                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        94910                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       138366                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         2169                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         5547                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         7716                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data           26                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total           26                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       138769                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data       364046                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       502815                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       138769                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data       364046                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       502815                       # number of overall MSHR misses
+system.cpu0.dcache.tags.tag_accesses         64401814                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        64401814                       # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.ReadReq_hits::cpu0.data      3982326                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data      1071245                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data      2765188                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        7818759                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3123296                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data       821204                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu2.data      1357761                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       5302261                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       113724                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        19478                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        59657                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       192859                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       122531                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data        21526                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu2.data        55288                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       199345                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data      7105622                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data      1892449                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu2.data      4122949                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        13121020                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data      7105622                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data      1892449                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu2.data      4122949                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       13121020                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       711284                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data        95061                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu2.data       562348                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1368693                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       164279                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data        43166                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu2.data       643208                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       850653                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9354                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         2180                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         7624                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        19158                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu2.data           15                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total           15                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       875563                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data       138227                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu2.data      1205556                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       2219346                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       875563                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data       138227                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu2.data      1205556                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      2219346                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2249916500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   8280122000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  10530038500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1722737000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  19403438202                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  21126175202                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     28838500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    118651000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    147489500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data       209000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total       209000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data   3972653500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data  27683560202                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  31656213702                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data   3972653500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data  27683560202                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  31656213702                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      4693610                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data      1166306                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data      3327536                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      9187452                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      3287575                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data       864370                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data      2000969                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      6152914                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       123078                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        21658                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        67281                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       212017                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       122531                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        21526                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        55303                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       199360                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data      7981185                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data      2030676                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data      5328505                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     15340366                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data      7981185                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data      2030676                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data      5328505                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     15340366                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.151543                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.081506                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.168998                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.148974                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.049970                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.049939                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.321448                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.138252                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.076001                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.100656                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.113316                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.090361                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000271                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000075                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.109703                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.068069                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.226247                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.144674                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.109703                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.068069                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.226247                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.144674                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23668.134145                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14724.195694                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total  7693.499200                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39909.581615                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30166.661798                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 24835.244456                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13228.669725                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 15562.827912                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  7698.585447                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13933.333333                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13933.333333                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 28740.068872                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 22963.313361                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 14263.757748                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 28740.068872                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 22963.313361                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 14263.757748                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs      1005696                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets         2108                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            59599                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets             18                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    16.874377                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets   117.111111                       # average number of cycles each access was blocked
+system.cpu0.dcache.writebacks::writebacks       837399                       # number of writebacks
+system.cpu0.dcache.writebacks::total           837399                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       293239                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       293239                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       548303                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total       548303                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         2076                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total         2076                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data       841542                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       841542                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data       841542                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       841542                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        95061                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       269109                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       364170                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        43166                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        94905                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       138071                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         2180                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         5548                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         7728                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data           15                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total           15                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       138227                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data       364014                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       502241                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       138227                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data       364014                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       502241                       # number of overall MSHR misses
 system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         1131                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         1724                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total         2855                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         1430                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         2033                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total         3463                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data         2561                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data         3757                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total         6318                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2159496000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   4442371500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6601867500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1709343000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   3045178740                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4754521740                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     26526000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     69860500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     96386500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data       390000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       390000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   3868839000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   7487550240                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  11356389240                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   3868839000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   7487550240                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  11356389240                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    248693500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data    375591500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    624285000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data    248693500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data    375591500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total    624285000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.081806                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.080779                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.039645                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.050308                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.047420                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.022488                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.101161                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.082305                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.036388                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000470                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000130                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.068396                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.068260                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.032766                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.068396                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.068260                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.032766                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 22656.888357                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16506.047129                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 18114.653902                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39335.028535                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32084.909282                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34361.922293                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12229.598893                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12594.285199                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12491.770347                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data        15000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        15000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27879.706563                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20567.593766                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22585.621431                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 27879.706563                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20567.593766                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22585.621431                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 219888.152078                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 217860.498840                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 218663.747811                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 97107.965638                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 99971.120575                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 98810.541311                       # average overall mshr uncacheable latency
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements           969876                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.205246                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           39683030                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           970387                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            40.894025                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      10200405500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   261.920563                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst    65.077972                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst   184.206711                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.511564                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.127105                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.359779                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.998448                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         1713                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total         2844                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         1429                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         2015                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total         3444                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data         2560                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data         3728                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total         6288                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2154855500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   4439209000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6594064500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1679571000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   3050724099                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4730295099                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     26658500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     69598500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     96257000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data       194000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       194000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   3834426500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   7489933099                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  11324359599                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   3834426500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   7489933099                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  11324359599                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    248626500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data    373633000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    622259500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data    248626500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data    373633000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total    622259500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.081506                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.080873                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.039638                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.049939                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.047430                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.022440                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.100656                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.082460                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.036450                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000271                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000075                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.068069                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.068314                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.032740                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.068069                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.068314                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.032740                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 22668.134145                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16495.951455                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 18107.105198                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38909.581615                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32145.030283                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34259.874260                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12228.669725                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12544.790916                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12455.615942                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 12933.333333                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12933.333333                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27740.068872                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20575.947900                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22547.660583                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 27740.068872                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20575.947900                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22547.660583                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 219828.912467                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 218116.170461                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 218797.292546                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 97119.726562                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 100223.444206                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 98959.844148                       # average overall mshr uncacheable latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.tags.replacements           970146                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.204815                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           39666884                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           970657                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            40.866015                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      10200765500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   263.084411                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst    64.947265                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst   183.173139                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.513837                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.126850                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst     0.357760                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.998447                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::2          447                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         41646260                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        41646260                       # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst     29526010                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst      7417850                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst      2739170                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       39683030                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     29526010                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst      7417850                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst      2739170                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        39683030                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     29526010                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst      7417850                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst      2739170                       # number of overall hits
-system.cpu0.icache.overall_hits::total       39683030                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       509351                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       126603                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst       356690                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       992644                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       509351                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       126603                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst       356690                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        992644                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       509351                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       126603                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst       356690                       # number of overall misses
-system.cpu0.icache.overall_misses::total       992644                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1812461000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   4955400483                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   6767861483                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst   1812461000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst   4955400483                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   6767861483                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst   1812461000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst   4955400483                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   6767861483                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     30035361                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst      7544453                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst      3095860                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     40675674                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     30035361                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst      7544453                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst      3095860                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     40675674                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     30035361                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst      7544453                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst      3095860                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     40675674                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016958                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.016781                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.115215                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.024404                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016958                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.016781                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst     0.115215                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.024404                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016958                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.016781                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst     0.115215                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.024404                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14316.098355                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13892.737343                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  6818.014800                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14316.098355                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13892.737343                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  6818.014800                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14316.098355                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13892.737343                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  6818.014800                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         4716                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses         41630359                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        41630359                       # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.ReadReq_hits::cpu0.inst     29500548                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst      7433858                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst      2732478                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       39666884                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     29500548                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst      7433858                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst      2732478                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        39666884                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     29500548                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst      7433858                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst      2732478                       # number of overall hits
+system.cpu0.icache.overall_hits::total       39666884                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       510117                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       127222                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst       355287                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       992626                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       510117                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       127222                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu2.inst       355287                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        992626                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       510117                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       127222                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst       355287                       # number of overall misses
+system.cpu0.icache.overall_misses::total       992626                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1824371000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   4938070984                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   6762441984                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst   1824371000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst   4938070984                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   6762441984                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst   1824371000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst   4938070984                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   6762441984                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     30010665                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst      7561080                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst      3087765                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     40659510                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     30010665                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst      7561080                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu2.inst      3087765                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     40659510                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     30010665                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst      7561080                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst      3087765                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     40659510                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016998                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.016826                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.115063                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.024413                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016998                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.016826                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst     0.115063                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.024413                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016998                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.016826                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst     0.115063                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.024413                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14340.059109                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13898.822597                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  6812.678677                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14340.059109                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13898.822597                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  6812.678677                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14340.059109                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13898.822597                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  6812.678677                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         4393                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              235                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              224                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    20.068085                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    19.611607                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks       969876                       # number of writebacks
-system.cpu0.icache.writebacks::total           969876                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        22058                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        22058                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst        22058                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        22058                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu2.inst        22058                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        22058                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       126603                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       334632                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       461235                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       126603                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst       334632                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       461235                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       126603                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst       334632                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       461235                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1685858000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   4399066985                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   6084924985                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1685858000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   4399066985                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   6084924985                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1685858000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   4399066985                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   6084924985                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.016781                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.108090                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.011339                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.016781                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.108090                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.011339                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.016781                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.108090                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.011339                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13316.098355                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13145.984201                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13192.678320                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13316.098355                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13145.984201                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 13192.678320                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13316.098355                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13145.984201                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 13192.678320                       # average overall mshr miss latency
+system.cpu0.icache.writebacks::writebacks       970146                       # number of writebacks
+system.cpu0.icache.writebacks::total           970146                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        21777                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        21777                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu2.inst        21777                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        21777                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu2.inst        21777                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        21777                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       127222                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       333510                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       460732                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       127222                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst       333510                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       460732                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       127222                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst       333510                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       460732                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1697149000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   4385581487                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   6082730487                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1697149000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   4385581487                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   6082730487                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1697149000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   4385581487                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   6082730487                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.016826                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.108010                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.011331                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.016826                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.108010                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.011331                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.016826                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.108010                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.011331                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13340.059109                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13149.775080                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13202.318239                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13340.059109                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13149.775080                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 13202.318239                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13340.059109                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13149.775080                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 13202.318239                       # average overall mshr miss latency
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     1184324                       # DTB read hits
-system.cpu1.dtb.read_misses                      1316                       # DTB read misses
+system.cpu1.dtb.read_hits                     1185765                       # DTB read hits
+system.cpu1.dtb.read_misses                      1350                       # DTB read misses
 system.cpu1.dtb.read_acv                           34                       # DTB read access violations
-system.cpu1.dtb.read_accesses                  141546                       # DTB read accesses
-system.cpu1.dtb.write_hits                     885341                       # DTB write hits
-system.cpu1.dtb.write_misses                      169                       # DTB write misses
-system.cpu1.dtb.write_acv                          22                       # DTB write access violations
-system.cpu1.dtb.write_accesses                  57820                       # DTB write accesses
-system.cpu1.dtb.data_hits                     2069665                       # DTB hits
-system.cpu1.dtb.data_misses                      1485                       # DTB misses
-system.cpu1.dtb.data_acv                           56                       # DTB access violations
-system.cpu1.dtb.data_accesses                  199366                       # DTB accesses
-system.cpu1.itb.fetch_hits                     852668                       # ITB hits
-system.cpu1.itb.fetch_misses                      656                       # ITB misses
-system.cpu1.itb.fetch_acv                          33                       # ITB acv
-system.cpu1.itb.fetch_accesses                 853324                       # ITB accesses
+system.cpu1.dtb.read_accesses                  142577                       # DTB read accesses
+system.cpu1.dtb.write_hits                     886140                       # DTB write hits
+system.cpu1.dtb.write_misses                      164                       # DTB write misses
+system.cpu1.dtb.write_acv                          19                       # DTB write access violations
+system.cpu1.dtb.write_accesses                  58302                       # DTB write accesses
+system.cpu1.dtb.data_hits                     2071905                       # DTB hits
+system.cpu1.dtb.data_misses                      1514                       # DTB misses
+system.cpu1.dtb.data_acv                           53                       # DTB access violations
+system.cpu1.dtb.data_accesses                  200879                       # DTB accesses
+system.cpu1.itb.fetch_hits                     858318                       # ITB hits
+system.cpu1.itb.fetch_misses                      678                       # ITB misses
+system.cpu1.itb.fetch_acv                          29                       # ITB acv
+system.cpu1.itb.fetch_accesses                 858996                       # ITB accesses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
@@ -946,17 +942,17 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numPwrStateTransitions               2293                       # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples         1147                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean    1553407081.081081                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev   1902806399.455202                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1000-5e+10         1147    100.00%    100.00% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::min_value       400000                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::max_value   6635637500                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total           1147                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON    59841239000                       # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 1781757922000                       # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles                       953375365                       # number of cpu cycles simulated
+system.cpu1.numPwrStateTransitions               2295                       # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples         1148                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean    1552918826.219512                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev   1902969233.500840                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10         1148    100.00%    100.00% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::min_value       123500                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::max_value   6633070500                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total           1148                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON    59822381500                       # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 1782750812500                       # Cumulative time (in ticks) in various power states
+system.cpu1.numCycles                       953371043                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
@@ -976,94 +972,94 @@ system.cpu1.kern.mode_ticks::kernel                 0                       # nu
 system.cpu1.kern.mode_ticks::user                   0                       # number of ticks spent at the given mode
 system.cpu1.kern.mode_ticks::idle                   0                       # number of ticks spent at the given mode
 system.cpu1.kern.swap_context                       0                       # number of times the context was actually changed
-system.cpu1.committedInsts                    7542911                       # Number of instructions committed
-system.cpu1.committedOps                      7542911                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses              7009980                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                 44709                       # Number of float alu accesses
-system.cpu1.num_func_calls                     205791                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts       911955                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                     7009980                       # number of integer instructions
-system.cpu1.num_fp_insts                        44709                       # number of float instructions
-system.cpu1.num_int_register_reads            9753806                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes           5113025                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads               24116                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes              24503                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                      2076660                       # number of memory refs
-system.cpu1.num_load_insts                    1189039                       # Number of load instructions
-system.cpu1.num_store_insts                    887621                       # Number of store instructions
-system.cpu1.num_idle_cycles              923368497.825425                       # Number of idle cycles
-system.cpu1.num_busy_cycles              30006867.174575                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.031474                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.968526                       # Percentage of idle cycles
-system.cpu1.Branches                          1183564                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass               404590      5.36%      5.36% # Class of executed instruction
-system.cpu1.op_class::IntAlu                  4887103     64.78%     70.14% # Class of executed instruction
-system.cpu1.op_class::IntMult                    8470      0.11%     70.25% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     70.25% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                   5131      0.07%     70.32% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     70.32% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     70.32% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     70.32% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                    810      0.01%     70.33% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc                 0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     70.33% # Class of executed instruction
-system.cpu1.op_class::MemRead                 1217523     16.14%     86.47% # Class of executed instruction
-system.cpu1.op_class::MemWrite                 888839     11.78%     98.25% # Class of executed instruction
-system.cpu1.op_class::IprAccess                131986      1.75%    100.00% # Class of executed instruction
+system.cpu1.committedInsts                    7559512                       # Number of instructions committed
+system.cpu1.committedOps                      7559512                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses              7024268                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                 44783                       # Number of float alu accesses
+system.cpu1.num_func_calls                     206891                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts       914000                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                     7024268                       # number of integer instructions
+system.cpu1.num_fp_insts                        44783                       # number of float instructions
+system.cpu1.num_int_register_reads            9773567                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes           5124259                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads               24150                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes              24568                       # number of times the floating registers were written
+system.cpu1.num_mem_refs                      2078876                       # number of memory refs
+system.cpu1.num_load_insts                    1190479                       # Number of load instructions
+system.cpu1.num_store_insts                    888397                       # Number of store instructions
+system.cpu1.num_idle_cycles              923345266.952757                       # Number of idle cycles
+system.cpu1.num_busy_cycles              30025776.047243                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.031494                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.968506                       # Percentage of idle cycles
+system.cpu1.Branches                          1187005                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass               406253      5.37%      5.37% # Class of executed instruction
+system.cpu1.op_class::IntAlu                  4898849     64.79%     70.16% # Class of executed instruction
+system.cpu1.op_class::IntMult                    8443      0.11%     70.27% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     70.27% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                   5163      0.07%     70.34% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     70.34% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     70.34% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     70.34% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                    816      0.01%     70.35% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     70.35% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     70.35% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     70.35% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     70.35% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     70.35% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     70.35% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     70.35% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     70.35% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     70.35% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     70.35% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     70.35% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     70.35% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     70.35% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     70.35% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     70.35% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     70.35% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     70.35% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc                 0      0.00%     70.35% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     70.35% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     70.35% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     70.35% # Class of executed instruction
+system.cpu1.op_class::MemRead                 1219110     16.12%     86.48% # Class of executed instruction
+system.cpu1.op_class::MemWrite                 889613     11.77%     98.24% # Class of executed instruction
+system.cpu1.op_class::IprAccess                132832      1.76%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                   7544452                       # Class of executed instruction
-system.cpu2.branchPred.lookups               10195062                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted          9245801                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect           194837                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups             7645666                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits                5489178                       # Number of BTB hits
+system.cpu1.op_class::total                   7561079                       # Class of executed instruction
+system.cpu2.branchPred.lookups               10182069                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted          9237326                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect           193435                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups             7648921                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits                5487936                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            71.794635                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                 367323                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect             14555                       # Number of incorrect RAS predictions.
-system.cpu2.branchPred.indirectLookups        1840410                       # Number of indirect predictor lookups.
-system.cpu2.branchPred.indirectHits            186758                       # Number of indirect target hits.
-system.cpu2.branchPred.indirectMisses         1653652                       # Number of indirect misses.
-system.cpu2.branchPredindirectMispredicted        86236                       # Number of mispredicted indirect branches.
+system.cpu2.branchPred.BTBHitPct            71.747845                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                 365631                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect             14350                       # Number of incorrect RAS predictions.
+system.cpu2.branchPred.indirectLookups        1844704                       # Number of indirect predictor lookups.
+system.cpu2.branchPred.indirectHits            187088                       # Number of indirect target hits.
+system.cpu2.branchPred.indirectMisses         1657616                       # Number of indirect misses.
+system.cpu2.branchPredindirectMispredicted        85690                       # Number of mispredicted indirect branches.
 system.cpu2.dtb.fetch_hits                          0                       # ITB hits
 system.cpu2.dtb.fetch_misses                        0                       # ITB misses
 system.cpu2.dtb.fetch_acv                           0                       # ITB acv
 system.cpu2.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu2.dtb.read_hits                     3794321                       # DTB read hits
-system.cpu2.dtb.read_misses                     14980                       # DTB read misses
-system.cpu2.dtb.read_acv                          154                       # DTB read access violations
-system.cpu2.dtb.read_accesses                  231448                       # DTB read accesses
-system.cpu2.dtb.write_hits                    2188085                       # DTB write hits
-system.cpu2.dtb.write_misses                     3764                       # DTB write misses
+system.cpu2.dtb.read_hits                     3799673                       # DTB read hits
+system.cpu2.dtb.read_misses                     14845                       # DTB read misses
+system.cpu2.dtb.read_acv                          160                       # DTB read access violations
+system.cpu2.dtb.read_accesses                  231351                       # DTB read accesses
+system.cpu2.dtb.write_hits                    2187859                       # DTB write hits
+system.cpu2.dtb.write_misses                     3782                       # DTB write misses
 system.cpu2.dtb.write_acv                         156                       # DTB write access violations
-system.cpu2.dtb.write_accesses                  84759                       # DTB write accesses
-system.cpu2.dtb.data_hits                     5982406                       # DTB hits
-system.cpu2.dtb.data_misses                     18744                       # DTB misses
-system.cpu2.dtb.data_acv                          310                       # DTB access violations
-system.cpu2.dtb.data_accesses                  316207                       # DTB accesses
-system.cpu2.itb.fetch_hits                     533759                       # ITB hits
-system.cpu2.itb.fetch_misses                     2736                       # ITB misses
-system.cpu2.itb.fetch_acv                         191                       # ITB acv
-system.cpu2.itb.fetch_accesses                 536495                       # ITB accesses
+system.cpu2.dtb.write_accesses                  85049                       # DTB write accesses
+system.cpu2.dtb.data_hits                     5987532                       # DTB hits
+system.cpu2.dtb.data_misses                     18627                       # DTB misses
+system.cpu2.dtb.data_acv                          316                       # DTB access violations
+system.cpu2.dtb.data_accesses                  316400                       # DTB accesses
+system.cpu2.itb.fetch_hits                     533981                       # ITB hits
+system.cpu2.itb.fetch_misses                     2772                       # ITB misses
+system.cpu2.itb.fetch_acv                         207                       # ITB acv
+system.cpu2.itb.fetch_accesses                 536753                       # ITB accesses
 system.cpu2.itb.read_hits                           0                       # DTB read hits
 system.cpu2.itb.read_misses                         0                       # DTB read misses
 system.cpu2.itb.read_acv                            0                       # DTB read access violations
@@ -1076,265 +1072,263 @@ system.cpu2.itb.data_hits                           0                       # DT
 system.cpu2.itb.data_misses                         0                       # DTB misses
 system.cpu2.itb.data_acv                            0                       # DTB access violations
 system.cpu2.itb.data_accesses                       0                       # DTB accesses
-system.cpu2.numPwrStateTransitions               3116                       # Number of power state transitions
-system.cpu2.pwrStateClkGateDist::samples         1558                       # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::mean    289379505.134788                       # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::stdev   445107312.150922                       # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::1000-5e+10         1558    100.00%    100.00% # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::min_value         3000                       # Distribution of time spent in the clock gated state
+system.cpu2.numPwrStateTransitions               3110                       # Number of power state transitions
+system.cpu2.pwrStateClkGateDist::samples         1555                       # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::mean    290577901.929260                       # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::stdev   445615554.555058                       # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::1000-5e+10         1555    100.00%    100.00% # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::min_value        35500                       # Distribution of time spent in the clock gated state
 system.cpu2.pwrStateClkGateDist::max_value   2000000000                       # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::total           1558                       # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateResidencyTicks::ON   1390745892000                       # Cumulative time (in ticks) in various power states
-system.cpu2.pwrStateResidencyTicks::CLK_GATED 450853269000                       # Cumulative time (in ticks) in various power states
-system.cpu2.numCycles                        30327275                       # number of cpu cycles simulated
+system.cpu2.pwrStateClkGateDist::total           1555                       # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateResidencyTicks::ON   1390724556500                       # Cumulative time (in ticks) in various power states
+system.cpu2.pwrStateResidencyTicks::CLK_GATED 451848637500                       # Cumulative time (in ticks) in various power states
+system.cpu2.numCycles                        30294700                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles           9354335                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                      40099246                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                   10195062                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches           6043259                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                     18967134                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                 549482                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles                         7                       # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.MiscStallCycles               11119                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles             1939                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles        54610                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles        90342                       # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles          596                       # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines                  3095865                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes               133552                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes                      1                       # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples          28754585                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.394534                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            2.444600                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles           9331724                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                      40046932                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                   10182069                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches           6040655                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                     18950980                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                 546368                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.MiscStallCycles               10813                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles             1967                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles        55421                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles        90541                       # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles          526                       # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines                  3087771                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes               132437                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples          28714918                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.394639                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            2.444168                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                19879004     69.13%     69.13% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                  339943      1.18%     70.32% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                  516791      1.80%     72.11% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                 4053539     14.10%     86.21% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                  887171      3.09%     89.30% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                  213563      0.74%     90.04% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                  261735      0.91%     90.95% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                  444517      1.55%     92.49% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                 2158322      7.51%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                19847963     69.12%     69.12% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                  338255      1.18%     70.30% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                  516605      1.80%     72.10% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                 4056347     14.13%     86.22% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                  883774      3.08%     89.30% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                  213492      0.74%     90.05% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                  260077      0.91%     90.95% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                  443832      1.55%     92.50% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                 2154573      7.50%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total            28754585                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.336168                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       1.322217                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                 7569976                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles             12996616                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                  7107544                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles               570612                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles                263955                       # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved              225265                       # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred                11264                       # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts              36283979                       # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts                35882                       # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles                263955                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                 7872857                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles                4931794                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles       5918579                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                  7355041                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles              2166486                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts              35279837                       # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents                60983                       # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents                402801                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents                 76926                       # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents               1084115                       # Number of times rename has blocked due to SQ full
-system.cpu2.rename.RenamedOperands           23748051                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups             43586446                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups        43526101                       # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups            56436                       # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps             20540056                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                 3207995                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts            542145                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts         75307                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                  3912291                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads             3917277                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores            2333144                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads           542030                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores          329847                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                  32377023                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded             701408                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                 31676973                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued            27053                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined        3928896                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined      1754776                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved        507029                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples     28754585                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        1.101632                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       1.635117                       # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total            28714918                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.336101                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       1.321912                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                 7553623                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles             12980509                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                  7101757                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles               570685                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles                262482                       # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved              224592                       # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred                11278                       # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts              36245198                       # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts                35745                       # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles                262482                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                 7856240                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles                4908054                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles       5914164                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                  7349808                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles              2178317                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts              35245227                       # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents                60989                       # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents                402200                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents                 73644                       # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents               1098810                       # Number of times rename has blocked due to SQ full
+system.cpu2.rename.RenamedOperands           23726835                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups             43551141                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups        43490937                       # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups            56291                       # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps             20541823                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                 3185012                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts            542390                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts         75158                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                  3906024                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads             3910206                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores            2331407                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads           534571                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores          330323                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                  32351146                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded             700049                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                 31671278                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued            26658                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined        3899534                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined      1737148                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved        505950                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples     28714918                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        1.102956                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       1.635713                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0           17376990     60.43%     60.43% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1            2804831      9.75%     70.19% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2            1408095      4.90%     75.08% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3            4807285     16.72%     91.80% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4            1079199      3.75%     95.55% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5             630267      2.19%     97.75% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6             421060      1.46%     99.21% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7             175258      0.61%     99.82% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8              51600      0.18%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0           17343310     60.40%     60.40% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1            2798035      9.74%     70.14% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2            1407296      4.90%     75.04% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3            4809954     16.75%     91.79% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4            1078748      3.76%     95.55% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5             629909      2.19%     97.74% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6             420699      1.47%     99.21% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7             175678      0.61%     99.82% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8              51289      0.18%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total       28754585                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total       28714918                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                  83759     19.66%     19.66% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     0      0.00%     19.66% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%     19.66% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     19.66% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     19.66% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     19.66% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%     19.66% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     19.66% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     19.66% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     19.66% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     19.66% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     19.66% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     19.66% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     19.66% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     19.66% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%     19.66% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     19.66% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%     19.66% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     19.66% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     19.66% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     19.66% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     19.66% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     19.66% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     19.66% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     19.66% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     19.66% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     19.66% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     19.66% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     19.66% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                210235     49.34%     69.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite               132097     31.00%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                  83963     19.65%     19.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                     0      0.00%     19.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                      0      0.00%     19.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     19.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     19.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     19.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%     19.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     19.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     19.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     19.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     19.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     19.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     19.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     19.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     19.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%     19.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     19.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%     19.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     19.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     19.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     19.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     19.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     19.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     19.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     19.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     19.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     19.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     19.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     19.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead                211212     49.43%     69.08% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite               132122     30.92%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass             2450      0.01%      0.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu             25141274     79.37%     79.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult               20994      0.07%     79.44% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     79.44% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd              20528      0.06%     79.51% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     79.51% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     79.51% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     79.51% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv               1224      0.00%     79.51% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     79.51% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     79.51% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     79.51% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     79.51% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     79.51% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     79.51% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     79.51% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     79.51% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     79.51% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     79.51% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     79.51% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     79.51% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     79.51% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     79.51% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     79.51% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     79.51% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     79.51% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     79.51% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     79.51% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     79.51% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     79.51% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead             3966361     12.52%     92.03% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite            2221145      7.01%     99.04% # Type of FU issued
-system.cpu2.iq.FU_type_0::IprAccess            302997      0.96%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass             2449      0.01%      0.01% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu             25130857     79.35%     79.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult               21000      0.07%     79.42% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     79.42% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd              20519      0.06%     79.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     79.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     79.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     79.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv               1224      0.00%     79.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     79.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     79.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     79.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     79.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     79.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     79.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     79.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     79.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     79.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     79.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     79.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     79.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     79.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     79.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     79.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     79.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     79.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     79.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     79.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     79.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     79.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead             3970834     12.54%     92.03% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite            2221095      7.01%     99.04% # Type of FU issued
+system.cpu2.iq.FU_type_0::IprAccess            303300      0.96%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total              31676973                       # Type of FU issued
-system.cpu2.iq.rate                          1.044504                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                     426091                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.013451                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads          92299555                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes         36885759                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses     30885842                       # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads             262120                       # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes            128344                       # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses       120451                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses              31960571                       # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses                 140043                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads          222851                       # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total              31671278                       # Type of FU issued
+system.cpu2.iq.rate                          1.045440                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                     427297                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.013492                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads          92249666                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes         36829058                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses     30874313                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads             261763                       # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes            128201                       # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses       120289                       # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses              31956268                       # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses                 139858                       # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads          223032                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads       843917                       # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses         1448                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation         6897                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores       272853                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads       835467                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses         1428                       # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation         6657                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores       271687                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads         4760                       # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked       213103                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads         4727                       # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked       223048                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles                263955                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles                4308277                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles               202891                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts           34565468                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts            70386                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts              3917277                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts             2333144                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts            625709                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                 13182                       # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents               148814                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents          6897                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect         76158                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect       205534                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts              281692                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts             31394525                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts              3819678                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts           282448                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles                262482                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles                4297358                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles               190047                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts           34535423                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts            71039                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts              3910206                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts             2331407                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts            624892                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                 12907                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents               136174                       # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents          6657                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect         75410                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect       204692                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts              280102                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts             31389945                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts              3824957                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts           281333                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu2.iew.exec_nop                      1487037                       # number of nop insts executed
-system.cpu2.iew.exec_refs                     6017890                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                 6848661                       # Number of branches executed
-system.cpu2.iew.exec_stores                   2198212                       # Number of stores executed
-system.cpu2.iew.exec_rate                    1.035191                       # Inst execution rate
-system.cpu2.iew.wb_sent                      31083503                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                     31006293                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                 17785830                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                 21615859                       # num instructions consuming a value
-system.cpu2.iew.wb_rate                      1.022390                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.822814                       # average fanout of values written-back
-system.cpu2.commit.commitSquashedInsts        4127890                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls         194379                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts           252373                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples     28042775                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     1.083004                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     1.865926                       # Number of insts commited each cycle
+system.cpu2.iew.exec_nop                      1484228                       # number of nop insts executed
+system.cpu2.iew.exec_refs                     6022953                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                 6845679                       # Number of branches executed
+system.cpu2.iew.exec_stores                   2197996                       # Number of stores executed
+system.cpu2.iew.exec_rate                    1.036153                       # Inst execution rate
+system.cpu2.iew.wb_sent                      31070665                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                     30994602                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                 17781356                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                 21603769                       # num instructions consuming a value
+system.cpu2.iew.wb_rate                      1.023103                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.823067                       # average fanout of values written-back
+system.cpu2.commit.commitSquashedInsts        4096171                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls         194099                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts           251035                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples     28008857                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     1.084369                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     1.866736                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0     18161783     64.76%     64.76% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1      2276613      8.12%     72.88% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2      1151869      4.11%     76.99% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3      4491226     16.02%     93.01% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4       562178      2.00%     95.01% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5       204579      0.73%     95.74% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6       167176      0.60%     96.34% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7       177068      0.63%     96.97% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8       850283      3.03%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0     18128303     64.72%     64.72% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1      2274965      8.12%     72.85% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2      1151627      4.11%     76.96% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3      4494039     16.05%     93.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4       560514      2.00%     95.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5       204888      0.73%     95.74% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6       167574      0.60%     96.33% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7       175902      0.63%     96.96% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8       851045      3.04%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total     28042775                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts            30370432                       # Number of instructions committed
-system.cpu2.commit.committedOps              30370432                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total     28008857                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts            30371950                       # Number of instructions committed
+system.cpu2.commit.committedOps              30371950                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                       5133651                       # Number of memory references committed
-system.cpu2.commit.loads                      3073360                       # Number of loads committed
-system.cpu2.commit.membars                      68499                       # Number of memory barriers committed
-system.cpu2.commit.branches                   6541282                       # Number of branches committed
-system.cpu2.commit.fp_insts                    116010                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                 28852886                       # Number of committed integer instructions.
-system.cpu2.commit.function_calls              241096                       # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass      1223345      4.03%      4.03% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu        23598567     77.70%     81.73% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult          20428      0.07%     81.80% # Class of committed instruction
+system.cpu2.commit.refs                       5134459                       # Number of memory references committed
+system.cpu2.commit.loads                      3074739                       # Number of loads committed
+system.cpu2.commit.membars                      68371                       # Number of memory barriers committed
+system.cpu2.commit.branches                   6541536                       # Number of branches committed
+system.cpu2.commit.fp_insts                    115785                       # Number of committed floating point instructions.
+system.cpu2.commit.int_insts                 28855389                       # Number of committed integer instructions.
+system.cpu2.commit.function_calls              240551                       # Number of function calls committed.
+system.cpu2.commit.op_class_0::No_OpClass      1222737      4.03%      4.03% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu        23599707     77.70%     81.73% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult          20441      0.07%     81.80% # Class of committed instruction
 system.cpu2.commit.op_class_0::IntDiv               0      0.00%     81.80% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd         20084      0.07%     81.86% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd         20074      0.07%     81.86% # Class of committed instruction
 system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     81.86% # Class of committed instruction
 system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     81.86% # Class of committed instruction
 system.cpu2.commit.op_class_0::FloatMult            0      0.00%     81.86% # Class of committed instruction
@@ -1360,29 +1354,29 @@ system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     81.87%
 system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     81.87% # Class of committed instruction
 system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     81.87% # Class of committed instruction
 system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     81.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead        3141859     10.35%     92.21% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite       2061928      6.79%     99.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::IprAccess       302997      1.00%    100.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead        3143110     10.35%     92.21% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite       2061357      6.79%     99.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::IprAccess       303300      1.00%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total         30370432                       # Class of committed instruction
-system.cpu2.commit.bw_lim_events               850283                       # number cycles where commit BW limit reached
-system.cpu2.rob.rob_reads                    61616016                       # The number of ROB reads
-system.cpu2.rob.rob_writes                   69709723                       # The number of ROB writes
-system.cpu2.timesIdled                         166720                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                        1572690                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                  1745481695                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                   29149535                       # Number of Instructions Simulated
-system.cpu2.committedOps                     29149535                       # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi                              1.040403                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        1.040403                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              0.961166                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        0.961166                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads                41087551                       # number of integer regfile reads
-system.cpu2.int_regfile_writes               22005301                       # number of integer regfile writes
-system.cpu2.fp_regfile_reads                    71153                       # number of floating regfile reads
-system.cpu2.fp_regfile_writes                   74234                       # number of floating regfile writes
-system.cpu2.misc_regfile_reads                4377642                       # number of misc regfile reads
-system.cpu2.misc_regfile_writes                272877                       # number of misc regfile writes
+system.cpu2.commit.op_class_0::total         30371950                       # Class of committed instruction
+system.cpu2.commit.bw_lim_events               851045                       # number cycles where commit BW limit reached
+system.cpu2.rob.rob_reads                    61550290                       # The number of ROB reads
+system.cpu2.rob.rob_writes                   69643370                       # The number of ROB writes
+system.cpu2.timesIdled                         166665                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                        1579782                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                  1747467532                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                   29151661                       # Number of Instructions Simulated
+system.cpu2.committedOps                     29151661                       # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi                              1.039210                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        1.039210                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              0.962269                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        0.962269                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads                41082611                       # number of integer regfile reads
+system.cpu2.int_regfile_writes               21995152                       # number of integer regfile writes
+system.cpu2.fp_regfile_reads                    71087                       # number of floating regfile reads
+system.cpu2.fp_regfile_writes                   74140                       # number of floating regfile writes
+system.cpu2.misc_regfile_reads                4380582                       # number of misc regfile reads
+system.cpu2.misc_regfile_writes                272883                       # number of misc regfile writes
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
@@ -1395,12 +1389,12 @@ system.disk2.dma_read_txs                           0                       # Nu
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.iobus.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
+system.iobus.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
 system.iobus.trans_dist::ReadReq                 7317                       # Transaction distribution
 system.iobus.trans_dist::ReadResp                7317                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               51362                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              51362                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5192                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::WriteReq               51363                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              51363                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5194                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1006                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
@@ -1409,11 +1403,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        1825
 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        33908                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        33910                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  117358                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20768                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  117360                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20776                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2717                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
@@ -1422,42 +1416,42 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9128
 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        45568                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total        45576                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2707176                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              2373500                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  2707184                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy              2361000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               135500                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               133500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer22.occupancy               56000                       # Layer occupancy (ticks)
 system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             5872500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             5888500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy             2528000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy             2490000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy            89904673                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy            89817179                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy             9173000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy             9132000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            17468000                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            17450000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
 system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.254561                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.262350                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle         1693898501000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.254561                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.078410                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.078410                       # Average percentage of cache occupancy
+system.iocache.tags.occ_blocks::tsunami.ide     1.262350                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.078897                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.078897                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
 system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
 system.iocache.tags.data_accesses              375525                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
+system.iocache.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
 system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
@@ -1466,14 +1460,14 @@ system.iocache.demand_misses::tsunami.ide        41725                       # n
 system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
 system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
 system.iocache.overall_misses::total            41725                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide      9598462                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total      9598462                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::tsunami.ide   2019796211                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   2019796211                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide   2029394673                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   2029394673                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide   2029394673                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   2029394673                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::tsunami.ide      9479963                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total      9479963                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::tsunami.ide   2017910216                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   2017910216                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide   2027390179                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   2027390179                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide   2027390179                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   2027390179                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
@@ -1490,14 +1484,14 @@ system.iocache.demand_miss_rate::tsunami.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 55482.439306                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 55482.439306                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 48608.880704                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 48608.880704                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 48637.379820                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 48637.379820                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 48637.379820                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 48637.379820                       # average overall miss latency
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54797.473988                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 54797.473988                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 48563.491914                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 48563.491914                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 48589.339221                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 48589.339221                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 48589.339221                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 48589.339221                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
@@ -1506,487 +1500,464 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.writebacks::writebacks           41512                       # number of writebacks
 system.iocache.writebacks::total                41512                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::tsunami.ide           70                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total           70                       # number of ReadReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::tsunami.ide        17280                       # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total        17280                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide        17350                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        17350                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide        17350                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        17350                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide      6098462                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total      6098462                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   1154802593                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   1154802593                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide   1160901055                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1160901055                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide   1160901055                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1160901055                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::tsunami.ide     0.404624                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total     0.404624                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide     0.415864                       # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total     0.415864                       # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::tsunami.ide     0.415818                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     0.415818                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::tsunami.ide     0.415818                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     0.415818                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 87120.885714                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 87120.885714                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66828.853762                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66828.853762                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66910.723631                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 66910.723631                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66910.723631                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 66910.723631                       # average overall mshr miss latency
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements                   337756                       # number of replacements
-system.l2c.tags.tagsinuse                65421.322565                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    4020988                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   402918                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     9.979668                       # Average number of references to valid blocks.
+system.iocache.ReadReq_mshr_misses::tsunami.ide           69                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total           69                       # number of ReadReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::tsunami.ide        17264                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total        17264                       # number of WriteLineReq MSHR misses
+system.iocache.demand_mshr_misses::tsunami.ide        17333                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        17333                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide        17333                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        17333                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide      6029963                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total      6029963                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   1153715348                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   1153715348                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide   1159745311                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1159745311                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide   1159745311                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1159745311                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::tsunami.ide     0.398844                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total     0.398844                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide     0.415479                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total     0.415479                       # mshr miss rate for WriteLineReq accesses
+system.iocache.demand_mshr_miss_rate::tsunami.ide     0.415410                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     0.415410                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::tsunami.ide     0.415410                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     0.415410                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 87390.768116                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 87390.768116                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66827.812095                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66827.812095                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66909.670051                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 66909.670051                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66909.670051                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 66909.670051                       # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
+system.l2c.tags.replacements                   337759                       # number of replacements
+system.l2c.tags.tagsinuse                65519.967313                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    4324806                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   403281                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    10.724051                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                614754000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   54641.026539                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     2330.416055                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2713.129703                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      574.927105                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      600.162086                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst     2250.445944                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data     2311.215132                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.833756                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.035559                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.041399                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.008773                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.009158                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.034339                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.035266                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.998250                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024        65162                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          178                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          987                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         5975                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         2686                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        55336                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.994293                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 38533534                       # Number of tag accesses
-system.l2c.tags.data_accesses                38533534                       # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
-system.l2c.WritebackDirty_hits::writebacks       836681                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total          836681                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks       969577                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total          969577                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data               3                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data               1                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data              10                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                  14                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu2.data            23                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                23                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            90271                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            25531                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data            71080                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               186882                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst        501948                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst        124306                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu2.inst        329876                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total            956130                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       479737                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data        81841                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu2.data       257555                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total           819133                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.inst              501948                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              570008                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              124306                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              107372                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst              329876                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data              328635                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1962145                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst             501948                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             570008                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             124306                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             107372                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst             329876                       # number of overall hits
-system.l2c.overall_hits::cpu2.data             328635                       # number of overall hits
-system.l2c.overall_hits::total                1962145                       # number of overall hits
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-system.l2c.ReadCleanReq_misses::total           14347                       # number of ReadCleanReq misses
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 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.writebacks::writebacks               75501                       # number of writebacks
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 system.l2c.ReadReq_mshr_uncacheable::cpu1.data         1131                       # number of ReadReq MSHR uncacheable
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-system.l2c.overall_mshr_uncacheable_latency::total    588587000                       # number of overall MSHR uncacheable cycles
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.444444                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.258065                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data     0.115385                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.111111                       # mshr miss rate for SCUpgradeReq accesses
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-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.007177                       # mshr miss rate for ReadCleanReq accesses
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-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.029906                       # mshr miss rate for ReadSharedReq accesses
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-system.l2c.overall_mshr_miss_rate::cpu2.data     0.110776                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.034440                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 38437.500000                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 38437.500000                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data        19500                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        19500                       # average SCUpgradeReq mshr miss latency
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-system.l2c.ReadExReq_avg_mshr_miss_latency::total 74003.024218                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72291.902481                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73617.609254                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73180.402010                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 65365.897321                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 65720.457881                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 65550.740605                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72291.902481                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66105.928795                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73617.609254                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 73731.387396                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 70542.653738                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72291.902481                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66105.928795                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73617.609254                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 73731.387396                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 70542.653738                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 207382.404951                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 205358.178654                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 206160.070053                       # average ReadReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 91585.122999                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 94234.096353                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 93160.335549                       # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests        823896                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       379632                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.l2c.ReadReq_mshr_uncacheable::cpu2.data         1713                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total         2844                       # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data         1429                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu2.data         2015                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total         3444                       # number of WriteReq MSHR uncacheable
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data         2560                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu2.data         3728                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total         6288                       # number of overall MSHR uncacheable misses
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       252500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total       252500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1169982000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1904437000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   3074419000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    169945000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst    343393000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total    513338000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   1020767500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data   1116825500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total   2137593000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    169945000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   2190749500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst    343393000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data   3021262500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   5725350000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    169945000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   2190749500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst    343393000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data   3021262500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   5725350000                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    234482500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data    352216500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total    586699000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    234482500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data    352216500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total    586699000                       # number of overall MSHR uncacheable cycles
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.294118                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.172414                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.407099                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.252377                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.137371                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.018448                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.013981                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.007220                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.160920                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.061975                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.029900                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.018448                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.236601                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.013981                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.110912                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.034332                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.018448                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.236601                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.013981                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.110912                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.034332                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data        50500                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total        50500                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66582.176189                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 79447.540778                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 74005.704932                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72409.458884                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73657.872158                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73239.834499                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 65233.096881                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 65633.844617                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 65441.862601                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72409.458884                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65946.703793                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73657.872158                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 73712.701588                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 70495.345745                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72409.458884                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65946.703793                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73657.872158                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 73712.701588                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 70495.345745                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 207323.165340                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 205613.835377                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 206293.600563                       # average ReadReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 91594.726562                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 94478.674893                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 93304.548346                       # average overall mshr uncacheable latency
+system.membus.snoop_filter.tot_requests        823847                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests       379580                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests          408                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadReq                7144                       # Transaction distribution
-system.membus.trans_dist::ReadResp             295138                       # Transaction distribution
-system.membus.trans_dist::WriteReq               9810                       # Transaction distribution
-system.membus.trans_dist::WriteResp              9810                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       117013                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           261704                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              179                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              4                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             113                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            115428                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           115428                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        288010                       # Transaction distribution
-system.membus.trans_dist::BadAddressError           16                       # Transaction distribution
+system.membus.trans_dist::ReadResp             295118                       # Transaction distribution
+system.membus.trans_dist::WriteReq               9811                       # Transaction distribution
+system.membus.trans_dist::WriteResp              9811                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       117015                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           261705                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              133                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp              97                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            115450                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           115450                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        287989                       # Transaction distribution
+system.membus.trans_dist::BadAddressError           15                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
-system.membus.trans_dist::InvalidateResp        24272                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        33908                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1143724                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio           32                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      1177664                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       107800                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       107800                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1285464                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        45568                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     30633664                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     30679232                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2664320                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2664320                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                33343552                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              157                       # Total snoops (count)
-system.membus.snoopTraffic                       9856                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            742227                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.001296                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.035978                       # Request fanout histogram
+system.membus.trans_dist::InvalidateResp        24288                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        33910                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1143669                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio           30                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      1177609                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       107817                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       107817                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1285426                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        45576                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     30634176                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     30679752                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2664384                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2664384                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                33344136                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              152                       # Total snoops (count)
+system.membus.snoopTraffic                       9536                       # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples            742383                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.001299                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.036012                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  741265     99.87%     99.87% # Request fanout histogram
-system.membus.snoop_fanout::1                     962      0.13%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  741419     99.87%     99.87% # Request fanout histogram
+system.membus.snoop_fanout::1                     964      0.13%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              742227                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            10965500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              742383                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            10929000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           390337877                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           389109129                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy               19000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy               19500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          436169750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          434990750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy             370538                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy             365537                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests      4730181                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      2364664                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests         1672                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops           1038                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops         1038                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.snoop_filter.tot_requests      4730225                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      2364683                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests         1647                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops           1041                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops         1041                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
 system.toL2Bus.trans_dist::ReadReq               7144                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2070392                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq              9810                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp             9810                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty       866358                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean       969876                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict          609667                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq              31                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq            27                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp             58                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           302472                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          302472                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq        970586                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      1092680                       # Transaction distribution
-system.toL2Bus.trans_dist::BadAddressError           16                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq           41                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2910960                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      4218835                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               7129795                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    124183936                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    142881728                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              267065664                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          338688                       # Total snoops (count)
-system.toL2Bus.snoopTraffic                   4852416                       # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples          4114055                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.000998                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.031568                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadResp           2070475                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq              9811                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp             9811                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty       866906                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean       970146                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          608698                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq              29                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq            15                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp             44                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           302414                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          302414                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq        970849                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      1092499                       # Transaction distribution
+system.toL2Bus.trans_dist::BadAddressError           15                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq           40                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2911790                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      4218095                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               7129885                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    124220224                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    142912456                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              267132680                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          338659                       # Total snoops (count)
+system.toL2Bus.snoopTraffic                   4850432                       # Total snoop traffic (bytes)
+system.toL2Bus.snoop_fanout::samples          4115169                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.000990                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.031456                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                4109951     99.90%     99.90% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                   4104      0.10%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                4111093     99.90%     99.90% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                   4076      0.10%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            4114055                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         1826321500                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            4115169                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         1824758000                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           100962                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy            98963                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         692196311                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy         691417859                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         770446828                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         769604277                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
-system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
-system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
-system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
+system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
+system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
+system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
+system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -2018,29 +1989,29 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
-system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
-system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
-system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1841599161000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
+system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
+system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
+system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
+system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
 system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 system.cpu2.kern.inst.hwrei                         0                       # number of hwrei instructions executed
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
index 43f49bfd8..14253ba3e 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
@@ -1,161 +1,161 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.647778                       # Number of seconds simulated
-sim_ticks                                2647778082500                       # Number of ticks simulated
-final_tick                               2647778082500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.848172                       # Number of seconds simulated
+sim_ticks                                2848172284000                       # Number of ticks simulated
+final_tick                               2848172284000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 109262                       # Simulator instruction rate (inst/s)
-host_op_rate                                   132319                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2267003011                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 618500                       # Number of bytes of host memory used
-host_seconds                                  1167.96                       # Real time elapsed on the host
-sim_insts                                   127613917                       # Number of instructions simulated
-sim_ops                                     154544077                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 135409                       # Simulator instruction rate (inst/s)
+host_op_rate                                   163982                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3007675070                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 625764                       # Number of bytes of host memory used
+host_seconds                                   946.97                       # Real time elapsed on the host
+sim_insts                                   128228197                       # Number of instructions simulated
+sim_ops                                     155285827                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.dtb.walker         8192                       # Number of bytes read from this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu0.dtb.walker         8960                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          1505216                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          1244784                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher      8319232                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker         1920                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           374976                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           749140                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher       607232                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          1677760                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          1343340                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher      8401088                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker         1408                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           221184                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           660436                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher       438272                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             12811716                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      1505216                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       374976                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1880192                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      9040448                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             12753472                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      1677760                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       221184                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1898944                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      9008896                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9058012                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker          128                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           9026460                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker          140                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             23519                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             19972                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       129988                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker           30                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              5859                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             11726                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher         9488                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             26215                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             21511                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       131267                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker           22                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              3456                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             10340                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher         6848                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                200726                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          141257                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                199815                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          140764                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               145648                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          3094                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker            24                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              568483                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              470124                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher      3141967                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           725                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              141619                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              282932                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       229336                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide              363                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4838667                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         568483                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         141619                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             710102                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3414353                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data               6618                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data                 15                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3420986                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3414353                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         3094                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker           24                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             568483                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             476742                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher      3141967                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          725                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             141619                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             282947                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       229336                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide             363                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                8259653                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        200726                       # Number of read requests accepted
-system.physmem.writeReqs                       145648                       # Number of write requests accepted
-system.physmem.readBursts                      200726                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     145648                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 12837568                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      8896                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   9070080                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  12811716                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                9058012                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      139                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_writes::total               145155                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          3146                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              589065                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              471650                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher      2949642                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           494                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               77658                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              231881                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       153878                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide              337                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4477774                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         589065                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          77658                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             666724                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3163045                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data               6153                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3169211                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3163045                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         3146                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             589065                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             477803                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher      2949642                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          494                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              77658                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             231895                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       153878                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide             337                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                7646985                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        199815                       # Number of read requests accepted
+system.physmem.writeReqs                       145155                       # Number of write requests accepted
+system.physmem.readBursts                      199815                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     145155                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 12777984                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     10176                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   9038976                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  12753472                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                9026460                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      159                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    3896                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               12684                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               12558                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               12677                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               12470                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               15173                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               12439                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               12705                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               12895                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               12483                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               12862                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              12103                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              11319                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              11938                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              12281                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              12069                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              11931                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                9144                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                9177                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                9224                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8920                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                8442                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                8744                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                9263                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                9163                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8908                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                9183                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               8711                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               8187                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8717                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8673                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8851                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               8413                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               12196                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               12508                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               12943                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               12617                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               14662                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               11885                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               12499                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               12704                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               12537                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               12319                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              11826                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              10998                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              12485                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              13119                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              12369                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              11989                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8816                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                9166                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                9495                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                9136                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                8038                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                8411                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8988                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8984                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                9026                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                8762                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               8598                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               8287                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               9114                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               9118                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8888                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               8407                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          30                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2647777471000                       # Total gap between requests
+system.physmem.numWrRetry                          34                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2848171745000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                     553                       # Read request sizes (log2)
+system.physmem.readPktSize::2                     552                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  200145                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  199235                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 141257                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     87468                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     62195                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     11522                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      9750                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      7877                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      6392                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      5324                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      4696                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      3790                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       756                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      271                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      239                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      160                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      134                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        4                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        2                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 140764                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     87471                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     61591                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     11471                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      9741                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      7810                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      6337                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      5222                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      4637                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      3767                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       779                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      267                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      232                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      180                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      139                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        6                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
@@ -185,165 +185,162 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2893                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3869                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4699                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5390                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6259                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6658                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7374                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7875                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8716                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     8796                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    10315                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    10815                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     9202                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     9069                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    10663                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     8820                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     8088                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7749                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      548                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      428                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      304                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      261                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      198                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      181                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      150                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      132                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      173                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      160                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      124                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      142                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      155                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       95                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      135                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       91                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       81                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       85                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       87                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       77                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       86                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      144                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       76                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       44                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       48                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       35                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       50                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       90                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        94963                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      230.695997                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     131.239554                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     294.689609                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          52509     55.29%     55.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        18085     19.04%     74.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6234      6.56%     80.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3686      3.88%     84.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2895      3.05%     87.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1483      1.56%     89.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          908      0.96%     90.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1023      1.08%     91.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8140      8.57%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          94963                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          7063                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        28.398839                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      555.406402                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           7061     99.97%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     2713                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::60                       46                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       50                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       57                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       88                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        88570                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      246.323767                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     141.050118                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     301.878369                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          44937     50.74%     50.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        18529     20.92%     71.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6585      7.43%     79.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3856      4.35%     83.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         3004      3.39%     86.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1517      1.71%     88.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          921      1.04%     89.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1037      1.17%     90.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8184      9.24%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          88570                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          7038                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        28.368144                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      555.266808                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           7037     99.99%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            7063                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          7063                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.065128                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.613340                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       12.212436                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5945     84.17%     84.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             392      5.55%     89.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              71      1.01%     90.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              48      0.68%     91.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             279      3.95%     95.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              27      0.38%     95.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              19      0.27%     96.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              25      0.35%     96.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              16      0.23%     96.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              12      0.17%     96.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               3      0.04%     96.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               7      0.10%     96.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             160      2.27%     99.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               6      0.08%     99.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               4      0.06%     99.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               5      0.07%     99.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               7      0.10%     99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.01%     99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               2      0.03%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             2      0.03%     99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             4      0.06%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             3      0.04%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.01%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             2      0.03%     99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             8      0.11%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.01%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.01%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.03%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             1      0.01%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             2      0.03%     99.90% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total            7038                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          7038                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.067349                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.571017                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       12.392738                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5944     84.46%     84.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             388      5.51%     89.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              60      0.85%     90.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              46      0.65%     91.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             266      3.78%     95.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              21      0.30%     95.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              22      0.31%     95.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              25      0.36%     96.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              15      0.21%     96.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              13      0.18%     96.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               4      0.06%     96.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              13      0.18%     96.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             149      2.12%     98.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               5      0.07%     99.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               7      0.10%     99.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              11      0.16%     99.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               6      0.09%     99.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.01%     99.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               4      0.06%     99.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               7      0.10%     99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.01%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             9      0.13%     99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.01%     99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             8      0.11%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             3      0.04%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.01%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.01%     99.90% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::160-163             4      0.06%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             2      0.03%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::204-207             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            7063                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     5391615341                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9152621591                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1002935000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       26879.19                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::176-179             1      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            7038                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     5532611303                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9276161303                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    998280000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       27710.72                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  45629.19                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           4.85                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.43                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        4.84                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.42                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  46460.72                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           4.49                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.17                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        4.48                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        3.17                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.04                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.24                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.36                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     166580                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     80763                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.05                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  56.97                       # Row buffer hit rate for writes
-system.physmem.avgGap                      7644273.16                       # Average gap between requests
-system.physmem.pageHitRate                      72.25                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  370341720                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  202071375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 808080000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                467058960                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           172939896480                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            79567681680                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1518869897250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1773225027465                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.703351                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2526645938707                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     88415080000                       # Time in different power states
+system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        22.18                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     165300                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     87019                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.79                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  61.60                       # Row buffer hit rate for writes
+system.physmem.avgGap                      8256288.21                       # Average gap between requests
+system.physmem.pageHitRate                      74.01                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  339738840                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  185373375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 795709200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                460300320                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           186028705200                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            83305465515                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1635827969250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1906943261700                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.532441                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2721218544299                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     95106700000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     32716967293                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     31846334451                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  347578560                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  189651000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 756490800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                451286640                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           172939896480                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            78874475895                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1519477980750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1773037360125                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.632470                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2527659145749                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     88415080000                       # Time in different power states
+system.physmem_1.actEnergy                  329850360                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  179977875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 761599800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                454896000                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           186028705200                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            82993384530                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1636101724500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1906850138265                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.499746                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2721674822130                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     95106700000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     31702650501                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     31390664370                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
 system.realview.nvmem.bytes_read::cpu0.inst          512                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst          832                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total          1344                       # Number of bytes read from this memory
@@ -353,39 +350,39 @@ system.realview.nvmem.bytes_inst_read::total         1344
 system.realview.nvmem.num_reads::cpu0.inst            8                       # Number of read requests responded to by this memory
 system.realview.nvmem.num_reads::cpu1.inst           13                       # Number of read requests responded to by this memory
 system.realview.nvmem.num_reads::total             21                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst          193                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst          314                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total              508                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst          193                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst          314                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total          508                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst          193                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst          314                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total             508                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
+system.realview.nvmem.bw_read::cpu0.inst          180                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst          292                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total              472                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst          180                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst          292                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total          472                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst          180                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst          292                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total             472                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups               34732065                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         16497595                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          1496295                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            19609177                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               10269070                       # Number of BTB hits
+system.cpu0.branchPred.lookups               20844041                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         13655604                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          1017556                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            13118749                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits                8767800                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            52.368695                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               11117365                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect            739154                       # Number of incorrect RAS predictions.
-system.cpu0.branchPred.indirectLookups        4170441                       # Number of indirect predictor lookups.
-system.cpu0.branchPred.indirectHits           3984607                       # Number of indirect target hits.
-system.cpu0.branchPred.indirectMisses          185834                       # Number of indirect misses.
-system.cpu0.branchPredindirectMispredicted        94839                       # Number of mispredicted indirect branches.
+system.cpu0.branchPred.BTBHitPct            66.834117                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                3422259                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect            208349                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.indirectLookups         764708                       # Number of indirect predictor lookups.
+system.cpu0.branchPred.indirectHits            581484                       # Number of indirect target hits.
+system.cpu0.branchPred.indirectMisses          183224                       # Number of indirect misses.
+system.cpu0.branchPredindirectMispredicted       100888                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -415,61 +412,61 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.cpu0.dtb.walker.walks                    65243                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort               65243                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        44492                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        20751                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples        65243                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0          65243    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total        65243                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples         6699                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 12206.821914                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 11332.778692                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev  5808.192470                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-16383         6323     94.39%     94.39% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::16384-32767          330      4.93%     99.31% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-49151           32      0.48%     99.79% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::49152-65535            7      0.10%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::81920-98303            3      0.04%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::98304-114687            3      0.04%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-212991            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total         6699                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.walker.walks                    67283                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort               67283                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        46446                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        20837                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples        67283                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0          67283    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total        67283                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples         6844                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 12453.243717                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 11569.675575                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev  5895.982503                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-16383         6363     92.97%     92.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::16384-32767          412      6.02%     98.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-49151           59      0.86%     99.85% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::49152-65535            3      0.04%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::81920-98303            5      0.07%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::98304-114687            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::180224-196607            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total         6844                       # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walksPending::samples    338010000                       # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::0      338010000    100.00%    100.00% # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::total    338010000                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         5176     77.27%     77.27% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         1523     22.73%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         6699                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        65243                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkPageSizes::4K         5263     76.90%     76.90% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1581     23.10%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         6844                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        67283                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        65243                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6699                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        67283                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6844                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6699                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total        71942                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6844                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        74127                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    23418517                       # DTB read hits
-system.cpu0.dtb.read_misses                     59363                       # DTB read misses
-system.cpu0.dtb.write_hits                   17357852                       # DTB write hits
-system.cpu0.dtb.write_misses                     5880                       # DTB write misses
+system.cpu0.dtb.read_hits                    17352300                       # DTB read hits
+system.cpu0.dtb.read_misses                     60872                       # DTB read misses
+system.cpu0.dtb.write_hits                   14551648                       # DTB write hits
+system.cpu0.dtb.write_misses                     6411                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3435                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                     1178                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  1722                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                    3450                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                     1427                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  1946                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      516                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                23477880                       # DTB read accesses
-system.cpu0.dtb.write_accesses               17363732                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      519                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                17413172                       # DTB read accesses
+system.cpu0.dtb.write_accesses               14558059                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         40776369                       # DTB hits
-system.cpu0.dtb.misses                          65243                       # DTB misses
-system.cpu0.dtb.accesses                     40841612                       # DTB accesses
-system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.hits                         31903948                       # DTB hits
+system.cpu0.dtb.misses                          67283                       # DTB misses
+system.cpu0.dtb.accesses                     31971231                       # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -499,41 +496,42 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.cpu0.itb.walker.walks                     4001                       # Table walker walks requested
-system.cpu0.itb.walker.walksShort                4001                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.cpu0.itb.walker.walks                     3992                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort                3992                       # Table walker walks initiated with short descriptors
 system.cpu0.itb.walker.walksShortTerminationLevel::Level1          306                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3695                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples         4001                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0           4001    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total         4001                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples         2427                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 12648.125258                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 11968.911523                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev  4734.087286                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-8191          373     15.37%     15.37% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::8192-16383         1885     77.67%     93.04% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-24575          118      4.86%     97.90% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::24576-32767           27      1.11%     99.01% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-40959           22      0.91%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::40960-49151            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3686                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples         3992                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0           3992    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total         3992                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples         2438                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 12900.533224                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 12073.120538                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev  5370.959057                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-8191          392     16.08%     16.08% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::8192-16383         1803     73.95%     90.03% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-24575          168      6.89%     96.92% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::24576-32767           38      1.56%     98.48% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-40959           34      1.39%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::40960-49151            1      0.04%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::57344-65535            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::90112-98303            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total         2427                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total         2438                       # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walksPending::samples    337545500                       # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::0      337545500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::total    337545500                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K         2126     87.60%     87.60% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M          301     12.40%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total         2427                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::4K         2137     87.65%     87.65% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          301     12.35%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         2438                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         4001                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total         4001                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3992                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3992                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2427                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2427                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total         6428                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    68314752                       # ITB inst hits
-system.cpu0.itb.inst_misses                      4001                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2438                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2438                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total         6430                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    38811638                       # ITB inst hits
+system.cpu0.itb.inst_misses                      3992                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
@@ -542,795 +540,802 @@ system.cpu0.itb.flush_tlb                          66                       # Nu
 system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2164                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    2175                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     7135                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     7061                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                68318753                       # ITB inst accesses
-system.cpu0.itb.hits                         68314752                       # DTB hits
-system.cpu0.itb.misses                           4001                       # DTB misses
-system.cpu0.itb.accesses                     68318753                       # DTB accesses
-system.cpu0.numPwrStateTransitions               4126                       # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples         2063                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean    1227700157.144935                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev   21500702795.368797                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::underflows         1198     58.07%     58.07% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10          860     41.69%     99.76% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::5e+10-1e+11            1      0.05%     99.81% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11            1      0.05%     99.85% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11            3      0.15%    100.00% # Distribution of time spent in the clock gated state
+system.cpu0.itb.inst_accesses                38815630                       # ITB inst accesses
+system.cpu0.itb.hits                         38811638                       # DTB hits
+system.cpu0.itb.misses                           3992                       # DTB misses
+system.cpu0.itb.accesses                     38815630                       # DTB accesses
+system.cpu0.numPwrStateTransitions               3698                       # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples         1849                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean    1494392801.532720                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev   23960009045.887756                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows         1074     58.09%     58.09% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10          768     41.54%     99.62% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::5e+10-1e+11            1      0.05%     99.68% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11            1      0.05%     99.73% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11            1      0.05%     99.78% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11            4      0.22%    100.00% # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::max_value 499984309000                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total           2063                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON   115032658310                       # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 2532745424190                       # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles                       230068064                       # number of cpu cycles simulated
+system.cpu0.pwrStateClkGateDist::max_value 499963441540                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total           1849                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON    85039993966                       # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 2763132290034                       # Cumulative time (in ticks) in various power states
+system.cpu0.numCycles                       170082548                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                  106706103                       # Number of instructions committed
-system.cpu0.committedOps                    129024022                       # Number of ops (including micro ops) committed
-system.cpu0.discardedOps                      8506641                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends                     2063                       # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles                  5065528558                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi                              2.156091                       # CPI: cycles per instruction
-system.cpu0.ipc                              0.463802                       # IPC: instructions per cycle
-system.cpu0.op_class_0::No_OpClass               2272      0.00%      0.00% # Class of committed instruction
-system.cpu0.op_class_0::IntAlu               87919988     68.14%     68.14% # Class of committed instruction
-system.cpu0.op_class_0::IntMult                105727      0.08%     68.23% # Class of committed instruction
-system.cpu0.op_class_0::IntDiv                      0      0.00%     68.23% # Class of committed instruction
-system.cpu0.op_class_0::FloatAdd                    0      0.00%     68.23% # Class of committed instruction
-system.cpu0.op_class_0::FloatCmp                    0      0.00%     68.23% # Class of committed instruction
-system.cpu0.op_class_0::FloatCvt                    0      0.00%     68.23% # Class of committed instruction
-system.cpu0.op_class_0::FloatMult                   0      0.00%     68.23% # Class of committed instruction
-system.cpu0.op_class_0::FloatDiv                    0      0.00%     68.23% # Class of committed instruction
-system.cpu0.op_class_0::FloatSqrt                   0      0.00%     68.23% # Class of committed instruction
-system.cpu0.op_class_0::SimdAdd                     0      0.00%     68.23% # Class of committed instruction
-system.cpu0.op_class_0::SimdAddAcc                  0      0.00%     68.23% # Class of committed instruction
-system.cpu0.op_class_0::SimdAlu                     0      0.00%     68.23% # Class of committed instruction
-system.cpu0.op_class_0::SimdCmp                     0      0.00%     68.23% # Class of committed instruction
-system.cpu0.op_class_0::SimdCvt                     0      0.00%     68.23% # Class of committed instruction
-system.cpu0.op_class_0::SimdMisc                    0      0.00%     68.23% # Class of committed instruction
-system.cpu0.op_class_0::SimdMult                    0      0.00%     68.23% # Class of committed instruction
-system.cpu0.op_class_0::SimdMultAcc                 0      0.00%     68.23% # Class of committed instruction
-system.cpu0.op_class_0::SimdShift                   0      0.00%     68.23% # Class of committed instruction
-system.cpu0.op_class_0::SimdShiftAcc                0      0.00%     68.23% # Class of committed instruction
-system.cpu0.op_class_0::SimdSqrt                    0      0.00%     68.23% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatAdd                0      0.00%     68.23% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatAlu                0      0.00%     68.23% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatCmp                0      0.00%     68.23% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatCvt                0      0.00%     68.23% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatDiv                0      0.00%     68.23% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatMisc            7151      0.01%     68.23% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatMult               0      0.00%     68.23% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatMultAcc            0      0.00%     68.23% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatSqrt               0      0.00%     68.23% # Class of committed instruction
-system.cpu0.op_class_0::MemRead              22900542     17.75%     85.98% # Class of committed instruction
-system.cpu0.op_class_0::MemWrite             18088342     14.02%    100.00% # Class of committed instruction
+system.cpu0.committedInsts                   79775908                       # Number of instructions committed
+system.cpu0.committedOps                     96002231                       # Number of ops (including micro ops) committed
+system.cpu0.discardedOps                      5290576                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu0.numFetchSuspends                     1849                       # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles                  5526291371                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi                              2.132004                       # CPI: cycles per instruction
+system.cpu0.ipc                              0.469042                       # IPC: instructions per cycle
+system.cpu0.op_class_0::No_OpClass               2273      0.00%      0.00% # Class of committed instruction
+system.cpu0.op_class_0::IntAlu               63778191     66.43%     66.44% # Class of committed instruction
+system.cpu0.op_class_0::IntMult                 92152      0.10%     66.53% # Class of committed instruction
+system.cpu0.op_class_0::IntDiv                      0      0.00%     66.53% # Class of committed instruction
+system.cpu0.op_class_0::FloatAdd                    0      0.00%     66.53% # Class of committed instruction
+system.cpu0.op_class_0::FloatCmp                    0      0.00%     66.53% # Class of committed instruction
+system.cpu0.op_class_0::FloatCvt                    0      0.00%     66.53% # Class of committed instruction
+system.cpu0.op_class_0::FloatMult                   0      0.00%     66.53% # Class of committed instruction
+system.cpu0.op_class_0::FloatDiv                    0      0.00%     66.53% # Class of committed instruction
+system.cpu0.op_class_0::FloatSqrt                   0      0.00%     66.53% # Class of committed instruction
+system.cpu0.op_class_0::SimdAdd                     0      0.00%     66.53% # Class of committed instruction
+system.cpu0.op_class_0::SimdAddAcc                  0      0.00%     66.53% # Class of committed instruction
+system.cpu0.op_class_0::SimdAlu                     0      0.00%     66.53% # Class of committed instruction
+system.cpu0.op_class_0::SimdCmp                     0      0.00%     66.53% # Class of committed instruction
+system.cpu0.op_class_0::SimdCvt                     0      0.00%     66.53% # Class of committed instruction
+system.cpu0.op_class_0::SimdMisc                    0      0.00%     66.53% # Class of committed instruction
+system.cpu0.op_class_0::SimdMult                    0      0.00%     66.53% # Class of committed instruction
+system.cpu0.op_class_0::SimdMultAcc                 0      0.00%     66.53% # Class of committed instruction
+system.cpu0.op_class_0::SimdShift                   0      0.00%     66.53% # Class of committed instruction
+system.cpu0.op_class_0::SimdShiftAcc                0      0.00%     66.53% # Class of committed instruction
+system.cpu0.op_class_0::SimdSqrt                    0      0.00%     66.53% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatAdd                0      0.00%     66.53% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatAlu                0      0.00%     66.53% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatCmp                0      0.00%     66.53% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatCvt                0      0.00%     66.53% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatDiv                0      0.00%     66.53% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatMisc            8115      0.01%     66.54% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatMult               0      0.00%     66.54% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatMultAcc            0      0.00%     66.54% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatSqrt               0      0.00%     66.54% # Class of committed instruction
+system.cpu0.op_class_0::MemRead              16825163     17.53%     84.07% # Class of committed instruction
+system.cpu0.op_class_0::MemWrite             15296337     15.93%    100.00% # Class of committed instruction
 system.cpu0.op_class_0::IprAccess                   0      0.00%    100.00% # Class of committed instruction
 system.cpu0.op_class_0::InstPrefetch                0      0.00%    100.00% # Class of committed instruction
-system.cpu0.op_class_0::total               129024022                       # Class of committed instruction
+system.cpu0.op_class_0::total                96002231                       # Class of committed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    2063                       # number of quiesce instructions executed
-system.cpu0.tickCycles                      178511666                       # Number of cycles that the object actually ticked
-system.cpu0.idleCycles                       51556398                       # Total number of cycles that the object has spent stopped
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements           681177                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          487.337065                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           39381714                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           681689                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            57.770793                       # Average number of references to valid blocks.
+system.cpu0.kern.inst.quiesce                    1849                       # number of quiesce instructions executed
+system.cpu0.tickCycles                      121004168                       # Number of cycles that the object actually ticked
+system.cpu0.idleCycles                       49078380                       # Total number of cycles that the object has spent stopped
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.tags.replacements           716277                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          496.364938                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           30460734                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           716789                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            42.496096                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle        356009000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   487.337065                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.951830                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.951830                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   496.364938                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.969463                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.969463                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          129                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          338                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           45                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          127                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          317                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         81578447                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        81578447                       # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data     21978387                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       21978387                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     16273218                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      16273218                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       306177                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       306177                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       357355                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       357355                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       352292                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       352292                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     38251605                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        38251605                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     38557782                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       38557782                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       418335                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       418335                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       561531                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       561531                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       131453                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       131453                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        20802                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        20802                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data        21460                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total        21460                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       979866                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        979866                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      1111319                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      1111319                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5562272000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   5562272000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  10028849500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  10028849500                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    328076000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    328076000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    523772000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total    523772000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       516000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total       516000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  15591121500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  15591121500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  15591121500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  15591121500                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     22396722                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     22396722                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     16834749                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     16834749                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       437630                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       437630                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       378157                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       378157                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       373752                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       373752                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     39231471                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     39231471                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     39669101                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     39669101                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.018678                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.018678                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.033355                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.033355                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.300375                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.300375                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.055009                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.055009                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.057418                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.057418                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.024977                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.024977                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.028015                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.028015                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13296.214756                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 13296.214756                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17859.832316                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 17859.832316                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15771.368138                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15771.368138                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24406.896552                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24406.896552                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses         63863131                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        63863131                       # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.ReadReq_hits::cpu0.data     15863909                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       15863909                       # number of ReadReq hits
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+system.cpu0.dcache.WriteReq_hits::total      13436402                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       320993                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       320993                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       365530                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       365530                       # number of LoadLockedReq hits
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+system.cpu0.dcache.StoreCondReq_hits::total       361278                       # number of StoreCondReq hits
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+system.cpu0.dcache.demand_hits::total        29300311                       # number of demand (read+write) hits
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+system.cpu0.dcache.ReadReq_misses::cpu0.data       439369                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       439369                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       580672                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       580672                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       135956                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       135956                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21086                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        21086                       # number of LoadLockedReq misses
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+system.cpu0.dcache.StoreCondReq_misses::total        20448                       # number of StoreCondReq misses
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+system.cpu0.dcache.overall_misses::total      1155997                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   6148409000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   6148409000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  10121621500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  10121621500                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    324178500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    324178500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    483049500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total    483049500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       688000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total       688000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  16270030500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  16270030500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  16270030500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  16270030500                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     16303278                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     16303278                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     14017074                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     14017074                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       456949                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       456949                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       386616                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       386616                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       381726                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       381726                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     30320352                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     30320352                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     30777301                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     30777301                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.026950                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.026950                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.041426                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.041426                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.297530                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.297530                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.054540                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.054540                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.053567                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.053567                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.033642                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.033642                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.037560                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.037560                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13993.725092                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 13993.725092                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17430.875778                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 17430.875778                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15374.110784                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15374.110784                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23623.312793                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23623.312793                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15911.483305                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 15911.483305                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14029.384452                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 14029.384452                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15950.369152                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 15950.369152                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14074.457373                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 14074.457373                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks       681177                       # number of writebacks
-system.cpu0.dcache.writebacks::total           681177                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        44450                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total        44450                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       246335                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total       246335                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        14695                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14695                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data       290785                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       290785                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data       290785                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       290785                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       373885                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       373885                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       315196                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       315196                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        98829                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total        98829                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6107                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6107                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        21460                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total        21460                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       689081                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       689081                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       787910                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       787910                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        29629                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        29629                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        26357                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        26357                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        55986                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        55986                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4452451000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4452451000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5571993500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5571993500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1619437000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1619437000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     94023500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     94023500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    502325000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    502325000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       503000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       503000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  10024444500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  10024444500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  11643881500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  11643881500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6101487500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6101487500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6101487500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6101487500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016694                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016694                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018723                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018723                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.225828                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.225828                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016149                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016149                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.057418                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.057418                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.017564                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.017564                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.019862                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.019862                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11908.610937                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11908.610937                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17677.868691                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17677.868691                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16386.253023                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16386.253023                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15396.020960                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15396.020960                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23407.502330                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23407.502330                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       716277                       # number of writebacks
+system.cpu0.dcache.writebacks::total           716277                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        44943                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total        44943                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       255413                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total       255413                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        14625                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14625                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data       300356                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       300356                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data       300356                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       300356                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       394426                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       394426                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       325259                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       325259                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       102388                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       102388                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6461                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6461                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20448                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total        20448                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       719685                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       719685                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       822073                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       822073                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        20384                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        20384                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        19085                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        19085                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        39469                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        39469                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   5005155000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5005155000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5561809000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5561809000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1663563000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1663563000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     98784500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     98784500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    462621500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    462621500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       668000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       668000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  10566964000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  10566964000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  12230527000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  12230527000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   4556252000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   4556252000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   4556252000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   4556252000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.024193                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.024193                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.023204                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.023204                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.224069                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.224069                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016712                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016712                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.053567                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.053567                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023736                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.023736                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.026710                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.026710                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12689.718731                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12689.718731                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17099.631371                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17099.631371                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16247.636442                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16247.636442                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15289.351494                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15289.351494                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22624.290884                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22624.290884                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14547.556093                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14547.556093                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14778.187230                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14778.187230                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 205929.579129                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 205929.579129                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 108982.379523                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 108982.379523                       # average overall mshr uncacheable latency
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements          1887196                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.757846                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           66419655                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1887708                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            35.185344                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       6638125000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.757846                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999527                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999527                       # Average percentage of cache occupancy
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14682.762598                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14682.762598                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14877.665365                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14877.665365                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223520.996860                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223520.996860                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115438.749398                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115438.749398                       # average overall mshr uncacheable latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.tags.replacements          1970602                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.774874                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           36833218                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1971114                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            18.686498                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle       6638665000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.774874                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999560                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999560                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          181                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          241                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           90                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          168                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          244                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          100                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        138502472                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       138502472                       # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst     66419655                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       66419655                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     66419655                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        66419655                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     66419655                       # number of overall hits
-system.cpu0.icache.overall_hits::total       66419655                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      1887721                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1887721                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      1887721                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1887721                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      1887721                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1887721                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  17836461000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  17836461000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  17836461000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  17836461000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  17836461000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  17836461000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     68307376                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     68307376                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     68307376                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     68307376                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     68307376                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     68307376                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.027636                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.027636                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.027636                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.027636                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.027636                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.027636                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9448.674354                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  9448.674354                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9448.674354                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  9448.674354                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9448.674354                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  9448.674354                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses         79579816                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        79579816                       # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.ReadReq_hits::cpu0.inst     36833218                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       36833218                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     36833218                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        36833218                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     36833218                       # number of overall hits
+system.cpu0.icache.overall_hits::total       36833218                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      1971127                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1971127                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      1971127                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1971127                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      1971127                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1971127                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  19380486500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  19380486500                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  19380486500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  19380486500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  19380486500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  19380486500                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     38804345                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     38804345                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     38804345                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     38804345                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     38804345                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     38804345                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.050797                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.050797                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.050797                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.050797                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.050797                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.050797                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9832.185597                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  9832.185597                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9832.185597                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  9832.185597                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9832.185597                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  9832.185597                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks      1887196                       # number of writebacks
-system.cpu0.icache.writebacks::total          1887196                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1887721                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1887721                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      1887721                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1887721                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      1887721                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1887721                       # number of overall MSHR misses
+system.cpu0.icache.writebacks::writebacks      1970602                       # number of writebacks
+system.cpu0.icache.writebacks::total          1970602                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1971127                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1971127                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      1971127                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1971127                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      1971127                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1971127                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         3448                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total         3448                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         3448                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total         3448                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  16892601000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  16892601000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  16892601000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  16892601000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  16892601000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  16892601000                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  18394923500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  18394923500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  18394923500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  18394923500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  18394923500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  18394923500                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    319413000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    319413000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    319413000                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total    319413000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.027636                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.027636                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.027636                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.027636                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.027636                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.027636                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  8948.674619                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  8948.674619                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  8948.674619                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total  8948.674619                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  8948.674619                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total  8948.674619                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.050797                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.050797                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.050797                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.050797                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.050797                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.050797                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9332.185851                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9332.185851                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9332.185851                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total  9332.185851                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9332.185851                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total  9332.185851                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92637.180974                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92637.180974                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92637.180974                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92637.180974                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      1767222                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      1767306                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit           74                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      1842994                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      1843099                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit           91                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage       225214                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.tags.replacements          281957                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16020.304669                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs           4495555                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs          298080                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs           15.081706                       # Average number of references to valid blocks.
+system.cpu0.l2cache.prefetcher.pfSpanPage       234669                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.cpu0.l2cache.tags.replacements          289615                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       15618.929391                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs           2598682                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs          305234                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            8.513737                       # Average number of references to valid blocks.
 system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 15153.098614                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    61.898882                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.073768                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   805.233405                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.924872                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003778                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000005                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.049148                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.977802                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1000                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023           13                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15110                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           18                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          315                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          390                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          277                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            4                       # Occupied blocks per task id
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 system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
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+system.cpu0.l2cache.overall_miss_latency::total   9865129496                       # number of overall miss cycles
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        80727                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         5529                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total        86256                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::writebacks       482674                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::total       482674                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::writebacks      2161538                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::total      2161538                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        56710                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total        56710                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        20447                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total        20447                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       268557                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total       268557                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1971127                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::total      1971127                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       503268                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::total       503268                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        80727                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         5529                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.inst      1971127                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.data       771825                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::total      2829208                       # number of demand (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        80727                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         5529                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst      1971127                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data       771825                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total      2829208                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.011434                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.032917                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.012811                       # miss rate for ReadReq accesses
 system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data            1                       # miss rate for UpgradeReq accesses
 system.cpu0.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.999951                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.999951                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.171843                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.171843                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.031987                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.031987                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.210344                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.210344                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.009669                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.021626                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.031987                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.196876                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.076152                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.009669                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.021626                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.031987                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.196876                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.076152                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 36470.394737                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23136.363636                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 34639.046538                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  2023.339988                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  2023.339988                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  1399.655108                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  1399.655108                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 120624.500000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 120624.500000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50568.110966                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50568.110966                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 49179.002020                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 49179.002020                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29297.604085                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29297.604085                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 36470.394737                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23136.363636                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 49179.002020                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35791.929295                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 39706.315271                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 36470.394737                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23136.363636                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 49179.002020                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35791.929295                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 39706.315271                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.174496                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.174496                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.046629                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.046629                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.226931                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.226931                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.011434                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.032917                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.046629                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.208686                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.089808                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.011434                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.032917                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.046629                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.208686                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.089808                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 35462.621885                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23296.703297                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 33458.823529                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data   752.301181                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total   752.301181                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data   463.807102                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total   463.807102                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       635999                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       635999                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49194.592634                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49194.592634                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 44310.868004                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 44310.868004                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 30209.181539                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 30209.181539                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 35462.621885                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23296.703297                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 44310.868004                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35732.866014                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 38825.946711                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 35462.621885                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23296.703297                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 44310.868004                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35732.866014                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 38825.946711                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs           38                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs               2                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs           19                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.l2cache.unused_prefetches            9085                       # number of HardPF blocks evicted w/o reference
-system.cpu0.l2cache.writebacks::writebacks       227660                       # number of writebacks
-system.cpu0.l2cache.writebacks::total          227660                       # number of writebacks
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         2626                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total         2626                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           53                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           53                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          363                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          363                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           53                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data         2989                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total         3042                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           53                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data         2989                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total         3042                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          760                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          121                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total          881                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       247545                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       247545                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        57605                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total        57605                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        21456                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        21456                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            4                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            4                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        41640                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total        41640                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        60329                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        60329                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       100353                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       100353                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          760                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          121                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        60329                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data       141993                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total       203203                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          760                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          121                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        60329                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data       141993                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       247545                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total       450748                       # number of overall MSHR misses
+system.cpu0.l2cache.unused_prefetches           11131                       # number of HardPF blocks evicted w/o reference
+system.cpu0.l2cache.writebacks::writebacks       233184                       # number of writebacks
+system.cpu0.l2cache.writebacks::total          233184                       # number of writebacks
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker            1                       # number of ReadReq MSHR hits
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+system.cpu0.l2cache.ReadExReq_mshr_hits::total         2845                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           59                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           59                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          394                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          394                       # number of ReadSharedReq MSHR hits
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+system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           59                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.data         3239                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::total         3299                       # number of demand (read+write) MSHR hits
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+system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           59                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.data         3239                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::total         3299                       # number of overall MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          923                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          181                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::total         1104                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       263706                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::total       263706                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        56710                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total        56710                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        20446                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        20446                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            1                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        44017                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::total        44017                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        91853                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        91853                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       113813                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       113813                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          923                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          181                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        91853                       # number of demand (read+write) MSHR misses
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 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         3448                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        29629                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        33077                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        26357                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        26357                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        20384                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        23832                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        19085                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        19085                       # number of WriteReq MSHR uncacheable
 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         3448                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        55986                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        59434                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     23157500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      2073500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     25231000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  14000669196                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  14000669196                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   1121106500                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   1121106500                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    340294500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    340294500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       404498                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       404498                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   1697761000                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1697761000                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   2606173000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   2606173000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2329095993                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2329095993                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     23157500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      2073500                       # number of demand (read+write) MSHR miss cycles
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-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   4026856993                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total   6658260993                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     23157500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      2073500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   2606173000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   4026856993                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  14000669196                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total  20658930189                       # number of overall MSHR miss cycles
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+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  14352533313                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  14352533313                       # number of HardPFReq MSHR miss cycles
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+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    980881500                       # number of UpgradeReq MSHR miss cycles
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 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    291829000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5864363500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6156192500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   4393084500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   4684913500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    291829000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   5864363500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   6156192500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.009669                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.021626                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.010463                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   4393084500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   4684913500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.011434                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.032736                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.012799                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.999951                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.999951                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.161648                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.161648                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.031959                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.031959                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.209586                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.209586                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.009669                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.021626                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.031959                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.192817                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.075029                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.009669                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.021626                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.031959                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.192817                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.163902                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.163902                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.046599                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.046599                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.226148                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.226148                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.011434                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.032736                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.046599                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.204489                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.088642                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.011434                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.032736                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.046599                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.204489                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.166430                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30470.394737                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17136.363636                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28639.046538                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56558.077101                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56558.077101                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19461.965107                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19461.965107                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15860.109060                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15860.109060                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 101124.500000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 101124.500000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40772.358309                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40772.358309                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 43199.340284                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 43199.340284                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23209.032047                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23209.032047                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30470.394737                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17136.363636                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43199.340284                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28359.545844                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32766.548688                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30470.394737                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17136.363636                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43199.340284                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28359.545844                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56558.077101                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45832.549870                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.181851                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29462.621885                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17290.055249                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27466.938406                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 54426.267559                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 54426.267559                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17296.446835                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17296.446835                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15079.795510                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15079.795510                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       515999                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       515999                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39199.922757                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39199.922757                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 38321.366749                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 38321.366749                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24124.678165                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24124.678165                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29462.621885                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17290.055249                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38321.366749                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28328.993195                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31984.995219                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29462.621885                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17290.055249                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38321.366749                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28328.993195                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 54426.267559                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 43487.383325                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84637.180974                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197926.474063                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 186117.014844                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 215516.311813                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196580.794730                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84637.180974                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 104746.963527                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 103580.315981                       # average overall mshr uncacheable latency
-system.cpu0.toL2Bus.snoop_filter.tot_requests      5292246                       # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests      2668157                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        40914                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops       334901                       # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       330475                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         4426                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.cpu0.toL2Bus.trans_dist::ReadReq        126809                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp      2542571                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        26357                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        26357                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty       693110                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean      2103191                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict       223137                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq       294264                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq        92982                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        43850                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       116200                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           14                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq       275510                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp       272175                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1887721                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq       569608                       # Transaction distribution
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111304.682156                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109162.185148                       # average overall mshr uncacheable latency
+system.cpu0.toL2Bus.snoop_filter.tot_requests      5528539                       # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests      2785631                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        42665                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops       220679                       # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       216467                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         4212                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.cpu0.toL2Bus.trans_dist::ReadReq        119671                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp      2643248                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        19085                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        19085                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty       716138                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean      2204203                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict       105351                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       312801                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq        88645                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        43001                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       114336                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           10                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           29                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq       287716                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp       284337                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1971127                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq       603215                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::InvalidateReq         3113                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      5669533                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2525108                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        13291                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       164598                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total          8372530                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    241815296                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     94996751                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        22380                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       314416                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total         337148843                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    1025467                       # Total snoops (count)
-system.cpu0.toL2Bus.snoopTraffic             18711896                       # Total snoop traffic (bytes)
-system.cpu0.toL2Bus.snoop_fanout::samples      3771293                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       0.106316                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.312026                       # Request fanout histogram
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      5919751                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2595390                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        13207                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       168847                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total          8697195                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    252491264                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     99508828                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        22116                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       322908                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total         352345116                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                     940127                       # Total snoops (count)
+system.cpu0.toL2Bus.snoopTraffic             19140516                       # Total snoop traffic (bytes)
+system.cpu0.toL2Bus.snoop_fanout::samples      3787201                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       0.076346                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.269706                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0           3374771     89.49%     89.49% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1            392096     10.40%     99.88% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2              4426      0.12%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0           3502276     92.48%     92.48% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1            280713      7.41%     99.89% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2              4212      0.11%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total       3771293                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy    5293903990                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total       3787201                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy    5519275492                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    114422325                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    116183079                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   2837181638                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   2962129461                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   1188012916                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   1227256511                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy      7701489                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy      7683988                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy     86027432                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy     88134970                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups                5469499                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted          3374978                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           316517                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups             3346860                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                2136825                       # Number of BTB hits
+system.cpu1.branchPred.lookups               19426531                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted          6224342                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           651829                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            10038478                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                3634441                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            63.845664                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                 972408                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect             68961                       # Number of incorrect RAS predictions.
-system.cpu1.branchPred.indirectLookups         195238                       # Number of indirect predictor lookups.
-system.cpu1.branchPred.indirectHits            132437                       # Number of indirect target hits.
-system.cpu1.branchPred.indirectMisses           62801                       # Number of indirect misses.
-system.cpu1.branchPredindirectMispredicted        28788                       # Number of mispredicted indirect branches.
-system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
+system.cpu1.branchPred.BTBHitPct            36.205100                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                8674574                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect            447731                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.indirectLookups        3678807                       # Number of indirect predictor lookups.
+system.cpu1.branchPred.indirectHits           3614078                       # Number of indirect target hits.
+system.cpu1.branchPred.indirectMisses           64729                       # Number of indirect misses.
+system.cpu1.branchPredindirectMispredicted        23620                       # Number of mispredicted indirect branches.
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1360,59 +1365,66 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.cpu1.dtb.walker.walks                    30404                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort               30404                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        23807                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         6597                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples        30404                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0          30404    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total        30404                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples         2736                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 12207.419591                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 11247.456123                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev  8821.385005                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-32767         2714     99.20%     99.20% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-65535           14      0.51%     99.71% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-98303            4      0.15%     99.85% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::98304-131071            3      0.11%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::294912-327679            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total         2736                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples  -1954228032                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0    -1954228032    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total  -1954228032                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K         2033     74.31%     74.31% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M          703     25.69%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         2736                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        30404                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.walker.walks                    27735                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort               27735                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        21301                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         6434                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples        27735                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0          27735    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total        27735                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples         2744                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 12429.118076                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 11482.413236                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  6276.586572                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-8191          644     23.47%     23.47% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::8192-16383         1820     66.33%     89.80% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-24575          198      7.22%     97.01% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::24576-32767           63      2.30%     99.31% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-40959            9      0.33%     99.64% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::40960-49151            4      0.15%     99.78% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::49152-57343            1      0.04%     99.82% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::57344-65535            1      0.04%     99.85% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::90112-98303            1      0.04%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::98304-106495            1      0.04%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::106496-114687            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::114688-122879            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total         2744                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples  -1939283032                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0    -1939283032    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total  -1939283032                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K         2036     74.20%     74.20% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M          708     25.80%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         2744                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        27735                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        30404                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2736                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        27735                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2744                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2736                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total        33140                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2744                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        30479                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     5173966                       # DTB read hits
-system.cpu1.dtb.read_misses                     27871                       # DTB read misses
-system.cpu1.dtb.write_hits                    4222414                       # DTB write hits
-system.cpu1.dtb.write_misses                     2533                       # DTB write misses
+system.cpu1.dtb.read_hits                    11374009                       # DTB read hits
+system.cpu1.dtb.read_misses                     25676                       # DTB read misses
+system.cpu1.dtb.write_hits                    7084428                       # DTB write hits
+system.cpu1.dtb.write_misses                     2059                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    2009                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      306                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   555                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries                    1996                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      172                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                   434                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      267                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 5201837                       # DTB read accesses
-system.cpu1.dtb.write_accesses                4224947                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      262                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                11399685                       # DTB read accesses
+system.cpu1.dtb.write_accesses                7086487                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                          9396380                       # DTB hits
-system.cpu1.dtb.misses                          30404                       # DTB misses
-system.cpu1.dtb.accesses                      9426784                       # DTB accesses
-system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.hits                         18458437                       # DTB hits
+system.cpu1.dtb.misses                          27735                       # DTB misses
+system.cpu1.dtb.accesses                     18486172                       # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1442,44 +1454,46 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.cpu1.itb.walker.walks                     2488                       # Table walker walks requested
-system.cpu1.itb.walker.walksShort                2488                       # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1          182                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2306                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples         2488                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0           2488    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total         2488                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples         1135                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 12427.312775                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 11760.899210                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev  5007.072010                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-4095            4      0.35%      0.35% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::4096-8191          156     13.74%     14.10% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-12287          686     60.44%     74.54% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::12288-16383          210     18.50%     93.04% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-20479           30      2.64%     95.68% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::20480-24575            2      0.18%     95.86% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-28671           21      1.85%     97.71% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::28672-32767            8      0.70%     98.41% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::36864-40959           15      1.32%     99.74% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::40960-45055            3      0.26%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total         1135                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples  -1954817532                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0    -1954817532    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total  -1954817532                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K          965     85.02%     85.02% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M          170     14.98%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total         1135                       # Table walker page sizes translated
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.cpu1.itb.walker.walks                     2480                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                2480                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1          180                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2300                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples         2480                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0           2480    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total         2480                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples         1130                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 12659.734513                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 11853.270475                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  5315.711785                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-8191          183     16.19%     16.19% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-12287          614     54.34%     70.53% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-16383          213     18.85%     89.38% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-20479           45      3.98%     93.36% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::20480-24575           23      2.04%     95.40% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-28671           28      2.48%     97.88% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::28672-32767           15      1.33%     99.20% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-36863            2      0.18%     99.38% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::36864-40959            4      0.35%     99.73% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-45055            1      0.09%     99.82% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::49152-53247            1      0.09%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::53248-57343            1      0.09%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total         1130                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples  -1939872532                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0    -1939872532    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total  -1939872532                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K          965     85.40%     85.40% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          165     14.60%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total         1130                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         2488                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total         2488                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         2480                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total         2480                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1135                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1135                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total         3623                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    10174079                       # ITB inst hits
-system.cpu1.itb.inst_misses                      2488                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1130                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1130                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total         3610                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                    39704875                       # ITB inst hits
+system.cpu1.itb.inst_misses                      2480                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
@@ -1488,778 +1502,777 @@ system.cpu1.itb.flush_tlb                          66                       # Nu
 system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    1107                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    1100                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                     1891                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                     1840                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                10176567                       # ITB inst accesses
-system.cpu1.itb.hits                         10174079                       # DTB hits
-system.cpu1.itb.misses                           2488                       # DTB misses
-system.cpu1.itb.accesses                     10176567                       # DTB accesses
-system.cpu1.numPwrStateTransitions               5445                       # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples         2723                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean    962192053.212266                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev   19383110303.670654                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::underflows         1861     68.34%     68.34% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1000-5e+10          855     31.40%     99.74% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::5e+10-1e+11            3      0.11%     99.85% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11            4      0.15%    100.00% # Distribution of time spent in the clock gated state
+system.cpu1.itb.inst_accesses                39707355                       # ITB inst accesses
+system.cpu1.itb.hits                         39704875                       # DTB hits
+system.cpu1.itb.misses                           2480                       # DTB misses
+system.cpu1.itb.accesses                     39707355                       # DTB accesses
+system.cpu1.numPwrStateTransitions               5533                       # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples         2767                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean    1008221990.514637                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev   25700822378.312321                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows         1966     71.05%     71.05% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10          797     28.80%     99.86% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5e+10-1e+11            1      0.04%     99.89% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11            1      0.04%     99.93% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11            1      0.04%     99.96% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11            1      0.04%    100.00% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::max_value 499966911836                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total           2723                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON    27729121603                       # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 2620048960897                       # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles                        55461727                       # number of cpu cycles simulated
+system.cpu1.pwrStateClkGateDist::max_value 949980874116                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total           2767                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON    58422036246                       # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 2789750247754                       # Cumulative time (in ticks) in various power states
+system.cpu1.numCycles                       116847616                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   20907814                       # Number of instructions committed
-system.cpu1.committedOps                     25520055                       # Number of ops (including micro ops) committed
-system.cpu1.discardedOps                      1855956                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends                     2723                       # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles                  5239453402                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi                              2.652679                       # CPI: cycles per instruction
-system.cpu1.ipc                              0.376977                       # IPC: instructions per cycle
-system.cpu1.op_class_0::No_OpClass                 67      0.00%      0.00% # Class of committed instruction
-system.cpu1.op_class_0::IntAlu               16137166     63.23%     63.23% # Class of committed instruction
-system.cpu1.op_class_0::IntMult                 34169      0.13%     63.37% # Class of committed instruction
-system.cpu1.op_class_0::IntDiv                      0      0.00%     63.37% # Class of committed instruction
-system.cpu1.op_class_0::FloatAdd                    0      0.00%     63.37% # Class of committed instruction
-system.cpu1.op_class_0::FloatCmp                    0      0.00%     63.37% # Class of committed instruction
-system.cpu1.op_class_0::FloatCvt                    0      0.00%     63.37% # Class of committed instruction
-system.cpu1.op_class_0::FloatMult                   0      0.00%     63.37% # Class of committed instruction
-system.cpu1.op_class_0::FloatDiv                    0      0.00%     63.37% # Class of committed instruction
-system.cpu1.op_class_0::FloatSqrt                   0      0.00%     63.37% # Class of committed instruction
-system.cpu1.op_class_0::SimdAdd                     0      0.00%     63.37% # Class of committed instruction
-system.cpu1.op_class_0::SimdAddAcc                  0      0.00%     63.37% # Class of committed instruction
-system.cpu1.op_class_0::SimdAlu                     0      0.00%     63.37% # Class of committed instruction
-system.cpu1.op_class_0::SimdCmp                     0      0.00%     63.37% # Class of committed instruction
-system.cpu1.op_class_0::SimdCvt                     0      0.00%     63.37% # Class of committed instruction
-system.cpu1.op_class_0::SimdMisc                    0      0.00%     63.37% # Class of committed instruction
-system.cpu1.op_class_0::SimdMult                    0      0.00%     63.37% # Class of committed instruction
-system.cpu1.op_class_0::SimdMultAcc                 0      0.00%     63.37% # Class of committed instruction
-system.cpu1.op_class_0::SimdShift                   0      0.00%     63.37% # Class of committed instruction
-system.cpu1.op_class_0::SimdShiftAcc                0      0.00%     63.37% # Class of committed instruction
-system.cpu1.op_class_0::SimdSqrt                    0      0.00%     63.37% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatAdd                0      0.00%     63.37% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatAlu                0      0.00%     63.37% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatCmp                0      0.00%     63.37% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatCvt                0      0.00%     63.37% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatDiv                0      0.00%     63.37% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatMisc            4083      0.02%     63.38% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatMult               0      0.00%     63.38% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatMultAcc            0      0.00%     63.38% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatSqrt               0      0.00%     63.38% # Class of committed instruction
-system.cpu1.op_class_0::MemRead               4989153     19.55%     82.93% # Class of committed instruction
-system.cpu1.op_class_0::MemWrite              4355417     17.07%    100.00% # Class of committed instruction
+system.cpu1.committedInsts                   48452289                       # Number of instructions committed
+system.cpu1.committedOps                     59283596                       # Number of ops (including micro ops) committed
+system.cpu1.discardedOps                      5163197                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu1.numFetchSuspends                     2767                       # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles                  5578862239                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi                              2.411602                       # CPI: cycles per instruction
+system.cpu1.ipc                              0.414662                       # IPC: instructions per cycle
+system.cpu1.op_class_0::No_OpClass                 66      0.00%      0.00% # Class of committed instruction
+system.cpu1.op_class_0::IntAlu               40834570     68.88%     68.88% # Class of committed instruction
+system.cpu1.op_class_0::IntMult                 45625      0.08%     68.96% # Class of committed instruction
+system.cpu1.op_class_0::IntDiv                      0      0.00%     68.96% # Class of committed instruction
+system.cpu1.op_class_0::FloatAdd                    0      0.00%     68.96% # Class of committed instruction
+system.cpu1.op_class_0::FloatCmp                    0      0.00%     68.96% # Class of committed instruction
+system.cpu1.op_class_0::FloatCvt                    0      0.00%     68.96% # Class of committed instruction
+system.cpu1.op_class_0::FloatMult                   0      0.00%     68.96% # Class of committed instruction
+system.cpu1.op_class_0::FloatDiv                    0      0.00%     68.96% # Class of committed instruction
+system.cpu1.op_class_0::FloatSqrt                   0      0.00%     68.96% # Class of committed instruction
+system.cpu1.op_class_0::SimdAdd                     0      0.00%     68.96% # Class of committed instruction
+system.cpu1.op_class_0::SimdAddAcc                  0      0.00%     68.96% # Class of committed instruction
+system.cpu1.op_class_0::SimdAlu                     0      0.00%     68.96% # Class of committed instruction
+system.cpu1.op_class_0::SimdCmp                     0      0.00%     68.96% # Class of committed instruction
+system.cpu1.op_class_0::SimdCvt                     0      0.00%     68.96% # Class of committed instruction
+system.cpu1.op_class_0::SimdMisc                    0      0.00%     68.96% # Class of committed instruction
+system.cpu1.op_class_0::SimdMult                    0      0.00%     68.96% # Class of committed instruction
+system.cpu1.op_class_0::SimdMultAcc                 0      0.00%     68.96% # Class of committed instruction
+system.cpu1.op_class_0::SimdShift                   0      0.00%     68.96% # Class of committed instruction
+system.cpu1.op_class_0::SimdShiftAcc                0      0.00%     68.96% # Class of committed instruction
+system.cpu1.op_class_0::SimdSqrt                    0      0.00%     68.96% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatAdd                0      0.00%     68.96% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatAlu                0      0.00%     68.96% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatCmp                0      0.00%     68.96% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatCvt                0      0.00%     68.96% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatDiv                0      0.00%     68.96% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatMisc            3333      0.01%     68.96% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatMult               0      0.00%     68.96% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatMultAcc            0      0.00%     68.96% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatSqrt               0      0.00%     68.96% # Class of committed instruction
+system.cpu1.op_class_0::MemRead              11200779     18.89%     87.86% # Class of committed instruction
+system.cpu1.op_class_0::MemWrite              7199223     12.14%    100.00% # Class of committed instruction
 system.cpu1.op_class_0::IprAccess                   0      0.00%    100.00% # Class of committed instruction
 system.cpu1.op_class_0::InstPrefetch                0      0.00%    100.00% # Class of committed instruction
-system.cpu1.op_class_0::total                25520055                       # Class of committed instruction
+system.cpu1.op_class_0::total                59283596                       # Class of committed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2723                       # number of quiesce instructions executed
-system.cpu1.tickCycles                       37036327                       # Number of cycles that the object actually ticked
-system.cpu1.idleCycles                       18425400                       # Total number of cycles that the object has spent stopped
-system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.tags.replacements           231690                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          479.724430                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            8932333                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           232024                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            38.497453                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     109862994000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   479.724430                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.936962                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.936962                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          334                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          264                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3           70                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.652344                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         18884551                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        18884551                       # Number of data accesses
-system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.ReadReq_hits::cpu1.data      4750067                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        4750067                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      3901959                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       3901959                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data        65733                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total        65733                       # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        87399                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        87399                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        79392                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        79392                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      8652026                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         8652026                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      8717759                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        8717759                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       172325                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       172325                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       169730                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       169730                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data        34831                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total        34831                       # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        17668                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        17668                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23402                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        23402                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       342055                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        342055                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       376886                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       376886                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2622225500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   2622225500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   4369952500                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   4369952500                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    333352000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    333352000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    570866500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total    570866500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       547000                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total       547000                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data   6992178000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   6992178000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data   6992178000                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   6992178000                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      4922392                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      4922392                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      4071689                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      4071689                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       100564                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total       100564                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       105067                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total       105067                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       102794                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total       102794                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      8994081                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      8994081                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      9094645                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      9094645                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.035008                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.035008                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.041685                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.041685                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.346357                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.346357                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.168159                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.168159                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.227659                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.227659                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.038031                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.038031                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.041440                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.041440                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15216.744523                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15216.744523                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25746.494432                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 25746.494432                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18867.557165                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18867.557165                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24393.919323                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24393.919323                       # average StoreCondReq miss latency
+system.cpu1.kern.inst.quiesce                    2767                       # number of quiesce instructions executed
+system.cpu1.tickCycles                       94150450                       # Number of cycles that the object actually ticked
+system.cpu1.idleCycles                       22697166                       # Total number of cycles that the object has spent stopped
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.tags.replacements           195596                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          473.279573                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs           18031187                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           195963                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            92.013222                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle      91237126000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   473.279573                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.924374                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.924374                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          367                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          310                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3           57                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.716797                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         36965565                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        36965565                       # Number of data accesses
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.ReadReq_hits::cpu1.data     10998874                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       10998874                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      6796614                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       6796614                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data        50142                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total        50142                       # number of SoftPFReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        80008                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        80008                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        71567                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        71567                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data     17795488                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total        17795488                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data     17845630                       # number of overall hits
+system.cpu1.dcache.overall_hits::total       17845630                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       148727                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       148727                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       145387                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       145387                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data        30687                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total        30687                       # number of SoftPFReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        16966                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        16966                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23611                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        23611                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       294114                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        294114                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       324801                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       324801                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2356620500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   2356620500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   3915884500                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   3915884500                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    322199000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    322199000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    556849500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total    556849500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       389000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total       389000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   6272505000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   6272505000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   6272505000                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   6272505000                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data     11147601                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total     11147601                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      6942001                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      6942001                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        80829                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total        80829                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        96974                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        96974                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        95178                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        95178                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data     18089602                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total     18089602                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data     18170431                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total     18170431                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.013342                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.013342                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.020943                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.020943                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.379653                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.379653                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.174954                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.174954                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.248072                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.248072                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.016259                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.016259                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.017875                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.017875                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15845.276917                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15845.276917                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26934.213513                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 26934.213513                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18990.864081                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18990.864081                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23584.325103                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23584.325103                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20441.677508                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 20441.677508                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18552.501287                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 18552.501287                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21326.781452                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 21326.781452                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19311.840173                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 19311.840173                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.writebacks::writebacks       231690                       # number of writebacks
-system.cpu1.dcache.writebacks::total           231690                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data         6182                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total         6182                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data        63208                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total        63208                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12205                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12205                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data        69390                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total        69390                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data        69390                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total        69390                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       166143                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       166143                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       106522                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total       106522                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        33373                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total        33373                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5463                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5463                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23402                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        23402                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       272665                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       272665                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       306038                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       306038                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         5399                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total         5399                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         4698                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total         4698                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        10097                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total        10097                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2348457500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2348457500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2649909000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2649909000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    556338500                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    556338500                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     95279500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     95279500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    547474500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    547474500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       537000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       537000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4998366500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   4998366500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   5554705000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   5554705000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    994956000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    994956000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    994956000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total    994956000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033752                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.033752                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.026162                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.026162                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.331858                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.331858                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.051995                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.051995                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.227659                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.227659                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.030316                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.030316                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.033650                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.033650                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14135.157665                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14135.157665                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24876.635812                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24876.635812                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16670.317322                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16670.317322                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17440.874977                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17440.874977                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23394.346637                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23394.346637                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       195596                       # number of writebacks
+system.cpu1.dcache.writebacks::total           195596                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data         5710                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total         5710                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data        52879                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total        52879                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12082                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12082                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data        58589                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total        58589                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data        58589                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total        58589                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       143017                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       143017                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        92508                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        92508                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        29859                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total        29859                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4884                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4884                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23611                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        23611                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       235525                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       235525                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       265384                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       265384                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        14595                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total        14595                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        11928                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total        11928                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        26523                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total        26523                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2115141000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2115141000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2362860000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2362860000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    507235000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    507235000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     82984000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     82984000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    533247500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    533247500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       380000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       380000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4478001000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   4478001000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4985236000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   4985236000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2537758000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2537758000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   2537758000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   2537758000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.012829                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.012829                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.013326                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.013326                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.369409                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.369409                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.050364                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.050364                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.248072                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.248072                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.013020                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.013020                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.014605                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.014605                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14789.437619                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14789.437619                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25542.223375                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25542.223375                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16987.675408                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16987.675408                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16990.990991                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16990.990991                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22584.706281                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22584.706281                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18331.529533                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18331.529533                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18150.376751                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18150.376751                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184285.238007                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184285.238007                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 98539.764286                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 98539.764286                       # average overall mshr uncacheable latency
-system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.cpu1.icache.tags.replacements          1038587                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          498.233977                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs            9132995                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs          1039099                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs             8.789341                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle      72888333000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.233977                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.973113                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.973113                       # Average percentage of cache occupancy
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19012.847893                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19012.847893                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18784.990806                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18784.990806                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173878.588558                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173878.588558                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95681.408589                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95681.408589                       # average overall mshr uncacheable latency
+system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.cpu1.icache.tags.replacements           948026                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          499.199607                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs           38754409                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           948538                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            40.856991                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle      72914784000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.199607                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.974999                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.974999                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          463                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3           49                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          461                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3           51                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         21383287                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        21383287                       # Number of data accesses
-system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.cpu1.icache.ReadReq_hits::cpu1.inst      9132995                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        9132995                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst      9132995                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         9132995                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst      9132995                       # number of overall hits
-system.cpu1.icache.overall_hits::total        9132995                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst      1039099                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total      1039099                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst      1039099                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total       1039099                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst      1039099                       # number of overall misses
-system.cpu1.icache.overall_misses::total      1039099                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   9377315500                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   9377315500                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   9377315500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   9377315500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   9377315500                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   9377315500                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     10172094                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     10172094                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     10172094                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     10172094                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     10172094                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     10172094                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.102152                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.102152                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.102152                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.102152                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.102152                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.102152                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9024.467832                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total  9024.467832                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9024.467832                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total  9024.467832                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9024.467832                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total  9024.467832                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses         80354432                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        80354432                       # Number of data accesses
+system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.cpu1.icache.ReadReq_hits::cpu1.inst     38754409                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       38754409                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     38754409                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        38754409                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     38754409                       # number of overall hits
+system.cpu1.icache.overall_hits::total       38754409                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       948538                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       948538                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       948538                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        948538                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       948538                       # number of overall misses
+system.cpu1.icache.overall_misses::total       948538                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   8680888000                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   8680888000                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   8680888000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   8680888000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   8680888000                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   8680888000                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     39702947                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     39702947                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     39702947                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     39702947                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     39702947                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     39702947                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.023891                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.023891                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.023891                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.023891                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.023891                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.023891                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9151.861075                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total  9151.861075                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9151.861075                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total  9151.861075                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9151.861075                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total  9151.861075                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.writebacks::writebacks      1038587                       # number of writebacks
-system.cpu1.icache.writebacks::total          1038587                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      1039099                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total      1039099                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst      1039099                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total      1039099                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst      1039099                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total      1039099                       # number of overall MSHR misses
+system.cpu1.icache.writebacks::writebacks       948026                       # number of writebacks
+system.cpu1.icache.writebacks::total           948026                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       948538                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       948538                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       948538                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       948538                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       948538                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       948538                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total          112                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total          112                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   8857766000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   8857766000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   8857766000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   8857766000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   8857766000                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   8857766000                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     10704000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     10704000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     10704000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total     10704000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.102152                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.102152                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.102152                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.102152                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.102152                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.102152                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8524.467832                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8524.467832                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8524.467832                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  8524.467832                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8524.467832                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  8524.467832                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95571.428571                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95571.428571                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95571.428571                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95571.428571                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.prefetcher.num_hwpf_issued       276399                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified       276459                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit           53                       # number of redundant prefetches already in prefetch queue
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   8206619000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   8206619000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   8206619000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   8206619000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   8206619000                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   8206619000                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     10719000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     10719000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     10719000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total     10719000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.023891                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.023891                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.023891                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.023891                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.023891                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.023891                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8651.861075                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8651.861075                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8651.861075                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  8651.861075                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8651.861075                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  8651.861075                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95705.357143                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95705.357143                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95705.357143                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95705.357143                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.cpu1.l2cache.prefetcher.num_hwpf_issued       199515                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified       199547                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit           28                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage        69493                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.tags.replacements           70219                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       15563.656432                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs           2283330                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs           85023                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs           26.855439                       # Average number of references to valid blocks.
+system.cpu1.l2cache.prefetcher.pfSpanPage        59237                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.cpu1.l2cache.tags.replacements           51581                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       14798.019682                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs           1058904                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs           65844                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs           16.082012                       # Average number of references to valid blocks.
 system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 14385.822816                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    54.124799                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.170471                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  1123.538345                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.878041                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.003304                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000010                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.068575                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.949930                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1056                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_blocks::writebacks 14409.418299                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    42.207150                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.101777                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   346.292455                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.879481                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.002576                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000006                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.021136                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.903199                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022          289                       # Occupied blocks per task id
 system.cpu1.l2cache.tags.occ_task_id_blocks::1023           42                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13706                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            4                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          291                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          761                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            9                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           14                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13932                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            3                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          101                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          185                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           11                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           12                       # Occupied blocks per task id
 system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           19                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          309                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         5206                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         8191                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.064453                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         1267                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         7924                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         4741                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.017639                       # Percentage of cache occupancy per task id
 system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.002563                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.836548                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses        42757972                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses       42757972                       # Number of data accesses
-system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        32984                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         3253                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total         36237                       # number of ReadReq hits
-system.cpu1.l2cache.WritebackDirty_hits::writebacks       134317                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackDirty_hits::total       134317                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackClean_hits::writebacks      1113970                       # number of WritebackClean hits
-system.cpu1.l2cache.WritebackClean_hits::total      1113970                       # number of WritebackClean hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data        37754                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total        37754                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      1012452                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total      1012452                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data       130088                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total       130088                       # number of ReadSharedReq hits
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-system.cpu1.l2cache.UpgradeReq_misses::total        31976                       # number of UpgradeReq misses
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-system.cpu1.l2cache.ReadCleanReq_misses::total        26647                       # number of ReadCleanReq misses
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-system.cpu1.l2cache.UpgradeReq_miss_latency::total     79820500                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data     32048000                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total     32048000                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data       521000                       # number of SCUpgradeFailReq miss cycles
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-system.cpu1.l2cache.ReadCleanReq_miss_latency::total   1147386500                       # number of ReadCleanReq miss cycles
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-system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1827426992                       # number of ReadSharedReq miss cycles
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-system.cpu1.l2cache.demand_miss_latency::cpu1.data   3305909992                       # number of demand (read+write) miss cycles
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-system.cpu1.l2cache.WritebackDirty_accesses::total       134317                       # number of WritebackDirty accesses(hits+misses)
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-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23401                       # number of SCUpgradeReq accesses(hits+misses)
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-system.cpu1.l2cache.ReadReq_miss_rate::total     0.025284                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.850342                       # Percentage of cache occupancy per task id
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+system.cpu1.l2cache.tags.data_accesses       39538104                       # Number of data accesses
+system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
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+system.cpu1.l2cache.WritebackDirty_accesses::writebacks       117770                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::total       117770                       # number of WritebackDirty accesses(hits+misses)
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+system.cpu1.l2cache.ReadReq_miss_rate::total     0.029634                       # miss rate for ReadReq accesses
 system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.493561                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.493561                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.025644                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.025644                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.365353                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.365353                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.020869                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.067908                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.025644                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.399546                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.102722                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.020869                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.067908                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.025644                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.399546                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.102722                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 25490.753912                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20508.438819                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24234.574468                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  2496.262822                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  2496.262822                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  1369.514123                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  1369.514123                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data       521000                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total       521000                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 40182.720009                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 40182.720009                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 43058.749578                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 43058.749578                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 24401.807902                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 24401.807902                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 25490.753912                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20508.438819                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 43058.749578                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29600.834433                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 32139.563380                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 25490.753912                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20508.438819                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 43058.749578                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29600.834433                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 32139.563380                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs           26                       # number of cycles access was blocked
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.554809                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.554809                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.037434                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.037434                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.421703                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.421703                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.023366                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.084862                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.037434                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.456381                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.119553                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.023366                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.084862                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.037434                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.456381                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.119553                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 23450.557103                       # average ReadReq miss latency
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+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22523.668639                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data   448.549342                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total   448.549342                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data   840.053365                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total   840.053365                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 40188.956916                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 40188.956916                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35362.256393                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35362.256393                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23421.933606                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23421.933606                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 23450.557103                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20275.337838                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35362.256393                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28732.275531                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 30299.134815                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 23450.557103                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20275.337838                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35362.256393                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28732.275531                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 30299.134815                       # average overall miss latency
+system.cpu1.l2cache.blocked_cycles::no_mshrs          120                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs               2                       # number of cycles access was blocked
+system.cpu1.l2cache.blocked::no_mshrs               3                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs           13                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs           40                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.l2cache.unused_prefetches            2265                       # number of HardPF blocks evicted w/o reference
-system.cpu1.l2cache.writebacks::writebacks        42373                       # number of writebacks
-system.cpu1.l2cache.writebacks::total           42373                       # number of writebacks
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          331                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total          331                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst           22                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::total           22                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          129                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          129                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst           22                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data          460                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total          482                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst           22                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data          460                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total          482                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          703                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          237                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total          940                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        38782                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total        38782                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        31976                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total        31976                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23401                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23401                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        36463                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total        36463                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        26625                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        26625                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        74760                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        74760                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          703                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          237                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        26625                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data       111223                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total       138788                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          703                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          237                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        26625                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data       111223                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        38782                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total       177570                       # number of overall MSHR misses
+system.cpu1.l2cache.unused_prefetches             854                       # number of HardPF blocks evicted w/o reference
+system.cpu1.l2cache.writebacks::writebacks        34916                       # number of writebacks
+system.cpu1.l2cache.writebacks::total           34916                       # number of writebacks
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker            2                       # number of ReadReq MSHR hits
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+system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst           16                       # number of ReadCleanReq MSHR hits
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::total           16                       # number of ReadCleanReq MSHR hits
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+system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29883                       # number of UpgradeReq MSHR misses
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 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         5399                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         5511                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         4698                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         4698                       # number of WriteReq MSHR uncacheable
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 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        10097                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        10209                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker     13702000                       # number of ReadReq MSHR miss cycles
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-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     17140500                       # number of ReadReq MSHR miss cycles
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-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   1312457547                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    566974500                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    566974500                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    370291999                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    370291999                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       461000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       461000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1222094000                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1222094000                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    987020000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    987020000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1373517992                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1373517992                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker     13702000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3438500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    987020000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2595611992                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total   3599772492                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker     13702000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3438500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    987020000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2595611992                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1312457547                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total   4912230039                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9808000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    951737000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    961545000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      9808000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    951737000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    961545000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.020869                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.067908                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.025284                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        26523                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        26635                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker     12503500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      4198500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     16702000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher    979860887                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total    979860887                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    459895000                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    459895000                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    354696000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    354696000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       312500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       312500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1165426499                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1165426499                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst   1042424000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total   1042424000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1304028987                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1304028987                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker     12503500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      4198500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst   1042424000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2469455486                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total   3528581486                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker     12503500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      4198500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst   1042424000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2469455486                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    979860887                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total   4508442373                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9823000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2420981000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2430804000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      9823000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   2420981000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   2430804000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.023300                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.084289                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.029517                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.489121                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.489121                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.025623                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.025623                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.364724                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.364724                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.020869                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.067908                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.025623                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.397900                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.102366                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.020869                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.067908                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.025623                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.397900                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.551439                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.551439                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.037418                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.037418                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.421225                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.421225                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.023300                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.084289                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.037418                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.455149                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.119294                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.023300                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.084289                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.037418                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.455149                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.130971                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 19490.753912                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14508.438819                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18234.574468                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33841.925300                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33841.925300                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17731.251564                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17731.251564                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15823.768172                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15823.768172                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       461000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       461000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33516.002523                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33516.002523                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 37071.173709                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 37071.173709                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 18372.364794                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 18372.364794                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 19490.753912                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14508.438819                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 37071.173709                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23337.007561                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25937.202726                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 19490.753912                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14508.438819                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 37071.173709                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23337.007561                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33841.925300                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27663.625832                       # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87571.428571                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176280.237081                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174477.408819                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87571.428571                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 94259.383975                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 94186.012342                       # average overall mshr uncacheable latency
-system.cpu1.toL2Bus.snoop_filter.tot_requests      2654318                       # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests      1335711                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        21986                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops       212975                       # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       211032                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         1943                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.cpu1.toL2Bus.trans_dist::ReadReq         47306                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp      1331970                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq         4698                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp         4698                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty       177822                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean      1135956                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict       137781                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq        47279                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq        75014                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        42924                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp        89713                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           14                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq        82844                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp        80563                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq      1039099                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq       293637                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq          236                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      3117009                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side      1002647                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         8284                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        70688                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total          4198628                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    132979072                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     35729427                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        13960                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       134748                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total         168857207                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                     473910                       # Total snoops (count)
-system.cpu1.toL2Bus.snoopTraffic              5785960                       # Total snoop traffic (bytes)
-system.cpu1.toL2Bus.snoop_fanout::samples      1814338                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       0.136111                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.346015                       # Request fanout histogram
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.140483                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 17462.988827                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14280.612245                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16536.633663                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37807.650847                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 37807.650847                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15389.853763                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15389.853763                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15022.489518                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15022.489518                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33746.242913                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33746.242913                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29370.675082                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29370.675082                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17415.614768                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17415.614768                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 17462.988827                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14280.612245                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29370.675082                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22570.243538                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24182.610894                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 17462.988827                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14280.612245                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29370.675082                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22570.243538                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37807.650847                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26237.654282                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87705.357143                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165877.423775                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165282.110560                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87705.357143                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 91278.550692                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 91263.525436                       # average overall mshr uncacheable latency
+system.cpu1.toL2Bus.snoop_filter.tot_requests      2396557                       # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests      1207646                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        20286                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops       118595                       # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       110586                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         8009                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.cpu1.toL2Bus.trans_dist::ReadReq         53656                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp      1217922                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq        11928                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp        11928                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty       153983                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean      1025852                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict        34704                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq        31184                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq        74094                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41981                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp        86038                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           20                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           29                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq        69927                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp        67092                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq       948538                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq       295426                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq           64                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      2845326                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       911410                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         8268                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        64898                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total          3829902                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    121387264                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     30723028                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        13952                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       122916                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total         152247160                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                     369470                       # Total snoops (count)
+system.cpu1.toL2Bus.snoopTraffic              5053360                       # Total snoop traffic (bytes)
+system.cpu1.toL2Bus.snoop_fanout::samples      1597738                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       0.098519                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.314386                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0           1569330     86.50%     86.50% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1            243065     13.40%     99.89% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2              1943      0.11%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0           1448339     90.65%     90.65% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1            141390      8.85%     99.50% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2              8009      0.50%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total       1814338                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy    2620766990                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total       1597738                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy    2375408982                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy     87124018                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy     79990687                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy   1558968196                       # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy    456771923                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy   1423068313                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer1.occupancy    409788212                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy      4794998                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy      4783493                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy     37016968                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy     34178481                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq                31014                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               31014                       # Transaction distribution
+system.iobus.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.iobus.trans_dist::ReadReq                31003                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               31003                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59422                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              59422                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56602                       # Packet count per connected master and slave (bytes)
@@ -2268,7 +2281,7 @@ system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          846                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
@@ -2281,17 +2294,17 @@ system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       107912                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72960                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total        72960                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  180872                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       107916                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72934                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total        72934                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  180850                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71546                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          447                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -2304,94 +2317,94 @@ system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       162794                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321280                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      2321280                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2484074                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             48375000                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::total       162796                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321176                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      2321176                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2483972                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             48331500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               113500                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               110000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               329000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               333000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                27500                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                28500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy                13000                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy                13500                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy                92000                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy                88500                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer8.occupancy               619500                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy               620000                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy               19500                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy               21000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer13.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy               10500                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy                8500                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               45500                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               47000                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy                8500                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy                8500                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer19.occupancy                2500                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer21.occupancy                9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer21.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6358000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6355500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            38893000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            39060500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           187720844                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           187669353                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            84714000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            84718000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36784000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36758000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements                36462                       # number of replacements
-system.iocache.tags.tagsinuse               14.359878                       # Cycle average of tags in use
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.replacements                36449                       # number of replacements
+system.iocache.tags.tagsinuse               14.473969                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                36478                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                36465                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         271405535000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide    14.359878                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.897492                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.897492                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         271637878000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide    14.473969                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.904623                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.904623                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               328320                       # Number of tag accesses
-system.iocache.tags.data_accesses              328320                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.iocache.ReadReq_misses::realview.ide          256                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              256                       # number of ReadReq misses
+system.iocache.tags.tag_accesses               328203                       # Number of tag accesses
+system.iocache.tags.data_accesses              328203                       # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.iocache.ReadReq_misses::realview.ide          243                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              243                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide        36480                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             36480                       # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide        36480                       # number of overall misses
-system.iocache.overall_misses::total            36480                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     33042377                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     33042377                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4307289467                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4307289467                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide   4340331844                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   4340331844                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide   4340331844                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   4340331844                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ide          256                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            256                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::realview.ide        36467                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             36467                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide        36467                       # number of overall misses
+system.iocache.overall_misses::total            36467                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide     31680877                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     31680877                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4302277476                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4302277476                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide   4333958353                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   4333958353                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide   4333958353                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   4333958353                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ide          243                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            243                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide        36480                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           36480                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide        36480                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          36480                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::realview.ide        36467                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           36467                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide        36467                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          36467                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
@@ -2400,38 +2413,38 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 129071.785156                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 129071.785156                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118907.063466                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 118907.063466                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 118978.394846                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 118978.394846                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 118978.394846                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 118978.394846                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs            32                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 130373.979424                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 130373.979424                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118768.702407                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118768.702407                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 118846.034853                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 118846.034853                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 118846.034853                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 118846.034853                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs            25                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    3                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    6                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    10.666667                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     4.166667                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.writebacks::writebacks           36206                       # number of writebacks
 system.iocache.writebacks::total                36206                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ide          256                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          256                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide          243                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          243                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide        36480                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        36480                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide        36480                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        36480                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     20242377                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     20242377                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2493740476                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2493740476                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   2513982853                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   2513982853                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   2513982853                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   2513982853                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::realview.ide        36467                       # number of demand (read+write) MSHR misses
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+system.iocache.overall_mshr_misses::total        36467                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     19530877                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     19530877                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2488777487                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2488777487                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   2508308364                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   2508308364                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   2508308364                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   2508308364                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -2440,590 +2453,592 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79071.785156                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 79071.785156                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68842.217204                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68842.217204                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 68914.003646                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 68914.003646                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 68914.003646                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 68914.003646                       # average overall mshr miss latency
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements                   135113                       # number of replacements
-system.l2c.tags.tagsinuse                63251.941629                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     475115                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   198978                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     2.387777                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   14216.048080                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    74.910809                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.033810                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     7426.792759                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2102.106662                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 29896.915616                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker    20.238831                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     3811.016358                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     1509.520853                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  4194.357849                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.216920                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001143                       # Average percentage of cache occupancy
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+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68705.208895                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68705.208895                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 68782.964434                       # average overall mshr miss latency
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+system.iocache.overall_avg_mshr_miss_latency::realview.ide 68782.964434                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 68782.964434                       # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.l2c.tags.replacements                   143192                       # number of replacements
+system.l2c.tags.tagsinuse                65154.235518                       # Cycle average of tags in use
+system.l2c.tags.total_refs                     608270                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   208652                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     2.915237                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle              94157771000                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks    6329.103935                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker    78.467327                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.034862                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     8953.646572                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     6857.938638                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35058.708510                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker    16.060603                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     2144.069552                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     3463.562714                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  2252.642806                       # Average occupied blocks per requestor
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 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000001                       # Average percentage of cache occupancy
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-system.l2c.tags.occ_task_id_blocks::1024        36452                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::1            3                       # Occupied blocks per task id
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-system.l2c.tags.age_task_id_blocks_1022::3         4822                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4        22394                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4           88                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0            6                       # Occupied blocks per task id
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-system.l2c.tags.age_task_id_blocks_1024::2          417                       # Occupied blocks per task id
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-system.l2c.tags.occ_task_id_percent::1023     0.001358                       # Percentage of cache occupancy per task id
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-system.l2c.tags.tag_accesses                  6444953                       # Number of tag accesses
-system.l2c.tags.data_accesses                 6444953                       # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.l2c.WritebackDirty_hits::writebacks       270033                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total          270033                       # number of WritebackDirty hits
-system.l2c.UpgradeReq_hits::cpu0.data           32996                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data            3857                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               36853                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data          2004                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data          1040                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total              3044                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data             3941                       # number of ReadExReq hits
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-system.l2c.ReadExReq_hits::total                 5877                       # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker          357                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker           67                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst        40247                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data        47388                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        44871                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker          179                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker           29                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst        20863                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data        12359                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         8223                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total           174583                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker           357                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker            67                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst               40247                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data               51329                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher        44871                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker           179                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker            29                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst               20863                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data               14295                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher         8223                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                  180460                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker          357                       # number of overall hits
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-system.l2c.overall_hits::cpu0.data              51329                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher        44871                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker          179                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker           29                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst              20863                       # number of overall hits
-system.l2c.overall_hits::cpu1.data              14295                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher         8223                       # number of overall hits
-system.l2c.overall_hits::total                 180460                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data          9513                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          4300                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             13813                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          964                       # number of SCUpgradeReq misses
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-system.l2c.SCUpgradeReq_misses::total            2167                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          11039                       # number of ReadExReq misses
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-system.l2c.ReadExReq_misses::total              19999                       # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0.dtb.walker          128                       # number of ReadSharedReq misses
+system.l2c.tags.occ_percent::cpu0.inst       0.136622                       # Average percentage of cache occupancy
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+system.l2c.tags.occ_task_id_blocks::1024        33709                       # Occupied blocks per task id
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+system.l2c.tags.age_task_id_blocks_1022::4        26979                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
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+system.l2c.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
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+system.l2c.tags.age_task_id_blocks_1024::4        31665                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.483429                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.001053                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.514359                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                  6826219                       # Number of tag accesses
+system.l2c.tags.data_accesses                 6826219                       # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.l2c.WritebackDirty_hits::writebacks       268100                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total          268100                       # number of WritebackDirty hits
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+system.l2c.UpgradeReq_hits::cpu1.data            5296                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total               48579                       # number of UpgradeReq hits
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+system.l2c.SCUpgradeReq_hits::total              5058                       # number of SCUpgradeReq hits
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+system.l2c.ReadSharedReq_hits::total           232219                       # number of ReadSharedReq hits
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+system.l2c.UpgradeReq_misses::total               779                       # number of UpgradeReq misses
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+system.l2c.SCUpgradeReq_misses::total             225                       # number of SCUpgradeReq misses
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-system.l2c.ReadSharedReq_misses::cpu0.inst        20082                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data         8636                       # number of ReadSharedReq misses
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-system.l2c.demand_misses::cpu0.dtb.walker          128                       # number of demand (read+write) misses
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 system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             20082                       # number of demand (read+write) misses
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-system.l2c.demand_misses::cpu1.data             11751                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher         9488                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                197062                       # number of demand (read+write) misses
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 system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
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-system.l2c.overall_misses::cpu0.data            19675                       # number of overall misses
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-system.l2c.overall_misses::cpu1.data            11751                       # number of overall misses
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-system.l2c.overall_misses::total               197062                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data     11061000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data      7336000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     18397000                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1913000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data      1241000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total      3154000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   1093563000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data    738422000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   1831985000                       # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker     11632000                       # number of ReadSharedReq miss cycles
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+system.l2c.UpgradeReq_miss_latency::total      9918000                       # number of UpgradeReq miss cycles
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+system.l2c.SCUpgradeReq_miss_latency::total      1192500                       # number of SCUpgradeReq miss cycles
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 system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker        84000                       # number of ReadSharedReq miss cycles
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-system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker      3061500                       # number of ReadSharedReq miss cycles
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-system.l2c.ReadSharedReq_miss_latency::cpu1.data    249182500                       # number of ReadSharedReq miss cycles
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-system.l2c.ReadSharedReq_miss_latency::total  17492536067                       # number of ReadSharedReq miss cycles
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 system.l2c.demand_miss_latency::cpu0.itb.walker        84000                       # number of demand (read+write) miss cycles
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-system.l2c.demand_miss_latency::cpu1.dtb.walker      3061500                       # number of demand (read+write) miss cycles
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-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher   1135921938                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     19324521067                       # number of demand (read+write) miss cycles
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+system.l2c.demand_miss_latency::total     19395454169                       # number of demand (read+write) miss cycles
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 system.l2c.overall_miss_latency::cpu0.itb.walker        84000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   1625007000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data   1861714000                       # number of overall miss cycles
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-system.l2c.overall_miss_latency::total    19324521067                       # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks       270033                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total       270033                       # number of WritebackDirty accesses(hits+misses)
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-system.l2c.UpgradeReq_accesses::total           50666                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data         2968                       # number of SCUpgradeReq accesses(hits+misses)
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-system.l2c.SCUpgradeReq_accesses::total          5211                       # number of SCUpgradeReq accesses(hits+misses)
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-system.l2c.ReadExReq_accesses::total            25876                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          485                       # number of ReadSharedReq accesses(hits+misses)
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-system.l2c.ReadSharedReq_accesses::cpu0.data        56024                       # number of ReadSharedReq accesses(hits+misses)
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-system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher        17711                       # number of ReadSharedReq accesses(hits+misses)
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-system.l2c.overall_accesses::total             377522                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.223788                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.527155                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.272629                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.324798                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.536335                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.415851                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.736916                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.822320                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.772878                       # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.263918                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.014706                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.332875                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.154148                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.743618                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.143541                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.216413                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.184224                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.535712                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.503526                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.263918                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.014706                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.332875                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.277097                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.743618                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.143541                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.216413                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.451163                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.535712                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.521988                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.263918                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.014706                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.332875                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.277097                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.743618                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.143541                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.216413                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.451163                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.535712                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.521988                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1162.724693                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1706.046512                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  1331.861290                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  1984.439834                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1031.587697                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  1455.468389                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 99063.592717                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82413.169643                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 91603.830192                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker        90875                       # average ReadSharedReq miss latency
+system.l2c.overall_miss_latency::cpu0.inst   1853877000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data   2006922000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  13504616525                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker      2056500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    279082000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data    872551000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher    863540144                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    19395454169                       # number of overall miss cycles
+system.l2c.WritebackDirty_accesses::writebacks       268100                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total       268100                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data        43769                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         5589                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           49358                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data         2910                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data         2373                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          5283                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data        15589                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        10161                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total            25750                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          611                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.itb.walker          105                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.inst        91852                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data        73599                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       179129                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker          144                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           31                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.inst        35492                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data        14986                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher        12368                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total       408317                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker          611                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker          105                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst           91852                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data           89188                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.l2cache.prefetcher       179129                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker          144                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker           31                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst           35492                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data           25147                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher        12368                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total              434067                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker          611                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker          105                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst          91852                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data          89188                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       179129                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker          144                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker           31                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst          35492                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data          25147                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher        12368                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total             434067                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.011104                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.052424                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.015783                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.032990                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.054362                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.042589                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.723780                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.852475                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.774563                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.229133                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.009524                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.247997                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.134010                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.733684                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.152778                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.094641                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.110904                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.553687                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.431278                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.229133                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.009524                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.247997                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.237095                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.733684                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.152778                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.094641                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.410546                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.553687                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.451642                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.229133                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.009524                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.247997                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.237095                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.733684                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.152778                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.094641                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.410546                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.553687                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.451642                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 19171.810700                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2049.488055                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 12731.707317                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  5942.708333                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  4821.705426                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total         5300                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 99296.286449                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83405.045024                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 92394.810730                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 90892.857143                       # average ReadSharedReq miss latency
 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker        84000                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 80918.583806                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88947.545160                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 101570.084360                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker       102050                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 83418.517876                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 89280.723755                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 119721.958052                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 98792.723872                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker        90875                       # average overall miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 81385.354932                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 89887.660955                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 102756.091163                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 93477.272727                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 83084.846681                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90310.770156                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 126101.072430                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 99675.406132                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 90892.857143                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu0.itb.walker        84000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 80918.583806                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 94623.329098                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 101570.084360                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker       102050                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 83418.517876                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 84044.294103                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 119721.958052                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 98063.153053                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker        90875                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 81385.354932                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 94907.878559                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 102756.091163                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 93477.272727                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 83084.846681                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 84516.757071                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 126101.072430                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 98934.693761                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 90892.857143                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.itb.walker        84000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 80918.583806                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 94623.329098                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 101570.084360                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker       102050                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 83418.517876                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 84044.294103                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 119721.958052                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 98063.153053                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs                49                       # number of cycles access was blocked
+system.l2c.overall_avg_miss_latency::cpu0.inst 81385.354932                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 94907.878559                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 102756.091163                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 93477.272727                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 83084.846681                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 84516.757071                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 126101.072430                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 98934.693761                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs                94                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        2                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        4                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs     24.500000                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs     23.500000                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.writebacks::writebacks              105051                       # number of writebacks
-system.l2c.writebacks::total                   105051                       # number of writebacks
+system.l2c.writebacks::writebacks              104558                       # number of writebacks
+system.l2c.writebacks::total                   104558                       # number of writebacks
+system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            1                       # number of ReadSharedReq MSHR hits
 system.l2c.ReadSharedReq_mshr_hits::cpu1.inst            2                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total            2                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total            3                       # number of ReadSharedReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu1.inst              2                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                  2                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                  3                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu1.inst             2                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                 2                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks         4156                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total         4156                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         9513                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         4300                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        13813                       # number of UpgradeReq MSHR misses
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 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
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-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.527155                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.272629                       # mshr miss rate for UpgradeReq accesses
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-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.263918                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.014706                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.332875                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.154148                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.743618                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.143541                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.216338                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.184224                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.535712                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.503521                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.263918                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.014706                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.332875                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.277097                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.743618                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.143541                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.216338                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.451163                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.535712                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.521983                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.263918                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.014706                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.332875                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.277097                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.743618                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.143541                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.216338                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.451163                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.535712                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.521983                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23846.000210                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 23640.581395                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23782.053138                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 25393.672199                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 25105.152951                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25233.502077                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 89063.592717                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72413.002567                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 81603.755338                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker        80875                       # average ReadSharedReq mshr miss latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.011104                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.052424                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.015783                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.032990                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.054362                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.042589                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.723780                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.852475                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.774563                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.229133                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.009524                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.247986                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.134010                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.733684                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.152778                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.094585                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.110904                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.553687                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.431270                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.229133                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.009524                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.247986                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.237095                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.733684                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.152778                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.094585                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.410546                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.553687                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.451635                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.229133                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.009524                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.247986                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.237095                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.733684                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.152778                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.094585                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.410546                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.553687                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.451635                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21985.596708                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22336.177474                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22117.458280                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26411.458333                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23174.418605                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24555.555556                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 89296.286449                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73405.045024                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 82394.810730                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 80892.857143                       # average ReadSharedReq mshr miss latency
 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker        74000                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 70918.459566                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78947.545160                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91570.072857                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker        92050                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73433.246875                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 79279.651021                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109721.537416                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 88793.314688                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        80875                       # average overall mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 71387.918298                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 79887.660955                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92756.068382                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 83477.272727                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73091.748585                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80309.869434                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116100.999562                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 89676.133235                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80892.857143                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        74000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 70918.459566                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 84623.329098                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91570.072857                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        92050                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73433.246875                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74043.911922                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109721.537416                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 88063.668908                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        80875                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71387.918298                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 84907.878559                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92756.068382                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 83477.272727                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73091.748585                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74516.612069                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116100.999562                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 88935.335554                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80892.857143                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        74000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70918.459566                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 84623.329098                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91570.072857                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        92050                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73433.246875                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74043.911922                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109721.537416                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 88063.668908                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71387.918298                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 84907.878559                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92756.068382                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 83477.272727                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73091.748585                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74516.612069                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116100.999562                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 88935.335554                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63637.035963                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 179924.347835                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 66571.428571                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158365.363232                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 166188.791033                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197515.134419                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 66705.357143                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 147906.284265                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 166371.405958                       # average ReadReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63637.035963                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 95219.849641                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 66571.428571                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 84658.163265                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 92079.185841                       # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests        535318                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       308111                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests          583                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 102007.866934                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 66705.357143                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81381.919306                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 92183.762527                       # average overall mshr uncacheable latency
+system.membus.snoop_filter.tot_requests        516977                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests       290556                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests          569                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq               38585                       # Transaction distribution
-system.membus.trans_dist::ReadResp             215902                       # Transaction distribution
-system.membus.trans_dist::WriteReq              31055                       # Transaction distribution
-system.membus.trans_dist::WriteResp             31055                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       141257                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            18818                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            79128                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          41795                       # Transaction distribution
+system.membus.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadReq               38536                       # Transaction distribution
+system.membus.trans_dist::ReadResp             214874                       # Transaction distribution
+system.membus.trans_dist::WriteReq              31013                       # Transaction distribution
+system.membus.trans_dist::WriteResp             31013                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       140764                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            19586                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            64644                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          38971                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq            2                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             40708                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            19870                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        177317                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             40377                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            19925                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        176338                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107912                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107916                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           42                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14304                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       675920                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       798178                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72957                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        72957                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 871135                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162794                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14120                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       656690                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       778768                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72931                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        72931                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 851699                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162796                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1344                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        28608                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     19551584                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     19744330                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        28240                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     19461788                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     19654168                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2318144                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2318144                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                22062474                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           126237                       # Total snoops (count)
-system.membus.snoopTraffic                      37184                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            444815                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.011558                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.106883                       # Request fanout histogram
+system.membus.pkt_size::total                21972312                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           123613                       # Total snoops (count)
+system.membus.snoopTraffic                      36288                       # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples            426105                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.011500                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.106618                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  439674     98.84%     98.84% # Request fanout histogram
-system.membus.snoop_fanout::1                    5141      1.16%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  421205     98.85%     98.85% # Request fanout histogram
+system.membus.snoop_fanout::1                    4900      1.15%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              444815                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            94951000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              426105                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            95080500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               22828                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            12539499                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            12459499                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          1031011447                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          1008366249                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1149570495                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1144784655                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy            1412877                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy            1337127                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
 system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
 system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
 system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
 system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -3055,77 +3070,77 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
 system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests      1073312                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests       580718                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests       172518                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops          20634                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops        19568                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops         1066                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2647778082500                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadReq              38588                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            515387                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             31055                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            31055                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty       375084                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict          144219                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          115852                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         44839                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         160691                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq           23                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq            51833                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp           51833                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq       476801                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq         4556                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1253209                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       392983                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               1646192                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     34630659                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7267527                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               41898186                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          395888                       # Total snoops (count)
-system.toL2Bus.snoopTraffic                  16395788                       # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples           898686                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.386698                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.489423                       # Request fanout histogram
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.snoop_filter.tot_requests      1122676                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests       592030                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests       210689                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops          28909                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops        27742                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops         1167                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848172284000                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.trans_dist::ReadReq              38539                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            569123                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             31013                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            31013                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty       372658                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          153621                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          113203                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         44029                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         157232                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq           29                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp           29                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq            51954                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp           51954                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       530586                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq         4329                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1344687                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       405982                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               1750669                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     38363344                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7028808                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               45392152                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          398871                       # Total snoops (count)
+system.toL2Bus.snoopTraffic                  16195724                       # Total snoop traffic (bytes)
+system.toL2Bus.snoop_fanout::samples           956902                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.408687                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.494066                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                 552232     61.45%     61.45% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 345388     38.43%     99.88% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                   1066      0.12%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                 566996     59.25%     59.25% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 388739     40.62%     99.88% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                   1167      0.12%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total             898686                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy          930017339                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total             956902                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy          952868265                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           361623                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           342123                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         658710189                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy         724877328                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         272587474                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         285789223                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
index 60905542e..4972770ec 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
@@ -1,121 +1,121 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.858997                       # Number of seconds simulated
-sim_ticks                                2858997339500                       # Number of ticks simulated
-final_tick                               2858997339500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.853344                       # Number of seconds simulated
+sim_ticks                                2853343899500                       # Number of ticks simulated
+final_tick                               2853343899500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 120078                       # Simulator instruction rate (inst/s)
-host_op_rate                                   145187                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3059253370                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 579060                       # Number of bytes of host memory used
-host_seconds                                   934.54                       # Real time elapsed on the host
-sim_insts                                   112217626                       # Number of instructions simulated
-sim_ops                                     135683579                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 139312                       # Simulator instruction rate (inst/s)
+host_op_rate                                   168444                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3544495637                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 589148                       # Number of bytes of host memory used
+host_seconds                                   805.01                       # Real time elapsed on the host
+sim_insts                                   112146750                       # Number of instructions simulated
+sim_ops                                     135598813                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.dtb.walker         8000                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1706880                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9150764                       # Number of bytes read from this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.dtb.walker         7680                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker           64                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1675712                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9177004                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10866732                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1706880                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1706880                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7954240                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             10861420                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1675712                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1675712                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7976832                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7971764                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker          125                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              26670                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             143502                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           7994356                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker          120                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker            1                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              26183                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             143912                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                170314                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          124285                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                170231                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          124638                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               128666                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker           2798                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker             45                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               597020                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3200690                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               129019                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           2692                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker             22                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               587280                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3216228                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              336                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3800889                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          597020                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             597020                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2782178                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data                6129                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2788308                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2782178                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          2798                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker            45                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              597020                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3206819                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                 3806558                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          587280                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             587280                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2795608                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data                6142                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2801750                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2795608                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          2692                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker            22                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              587280                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3222369                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             336                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6589197                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        170314                       # Number of read requests accepted
-system.physmem.writeReqs                       128666                       # Number of write requests accepted
-system.physmem.readBursts                      170314                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     128666                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10892160                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      7936                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7984576                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10866732                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7971764                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      124                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    3887                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bw_total::total                6608308                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        170231                       # Number of read requests accepted
+system.physmem.writeReqs                       129019                       # Number of write requests accepted
+system.physmem.readBursts                      170231                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     129019                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10886144                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      8640                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8006976                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10861420                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7994356                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      135                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    3888                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               10846                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10861                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               10970                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               10944                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               13948                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10354                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               10606                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10917                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10091                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10226                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               9938                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9330                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10171                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10932                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10237                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               9819                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8179                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8215                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8623                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8456                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7543                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7549                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7648                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8016                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7706                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7733                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7506                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7211                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7604                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8124                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7522                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7124                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               10508                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10518                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10699                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               10590                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               13367                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10649                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               10947                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               11320                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10289                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10353                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10214                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9210                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10497                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              11112                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10041                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9782                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7781                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7920                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8383                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8149                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7457                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7755                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7974                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8419                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7882                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7909                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7627                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7117                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7926                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8274                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7391                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7145                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          12                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2858996896000                       # Total gap between requests
+system.physmem.numWrRetry                           4                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2853343449000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     543                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  169757                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  169674                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 124285                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    162889                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      7005                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       284                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 124638                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    162184                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      7619                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       281                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
@@ -160,160 +160,164 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1874                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2917                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     7032                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6365                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     7124                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6452                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6411                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6488                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7149                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6917                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7499                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8410                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7380                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7541                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     8938                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7440                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7263                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7210                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1257                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      273                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      223                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      114                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      134                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      110                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      158                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      121                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      156                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      136                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      172                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      100                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       79                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       59                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       91                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       79                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       84                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       75                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       79                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       48                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       45                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       39                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       30                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        61663                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      306.126397                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     182.384465                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     323.388642                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          22560     36.59%     36.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        14992     24.31%     60.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6700     10.87%     71.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3651      5.92%     77.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2898      4.70%     82.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1667      2.70%     85.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1045      1.69%     86.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1093      1.77%     88.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7057     11.44%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          61663                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6083                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        27.977314                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      575.322656                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6082     99.98%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6083                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6083                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.509453                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.487861                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       14.653648                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5420     89.10%     89.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              90      1.48%     90.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              39      0.64%     91.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              27      0.44%     91.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              35      0.58%     92.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              16      0.26%     92.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              41      0.67%     93.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               7      0.12%     93.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             151      2.48%     95.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               6      0.10%     95.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               8      0.13%     96.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              13      0.21%     96.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67              69      1.13%     97.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               4      0.07%     97.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               3      0.05%     97.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              36      0.59%     98.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              90      1.48%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               2      0.03%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.02%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.02%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            10      0.16%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.02%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.03%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             3      0.05%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.02%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.02%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             2      0.03%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             3      0.05%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-211             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6083                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1877618250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5068680750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    850950000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       11032.48                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::15                     1927                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2883                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6085                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6461                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6753                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6440                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6861                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7240                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7833                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     7817                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     8977                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     9286                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7605                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7322                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     7382                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6746                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6645                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6645                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      340                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      300                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      278                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      175                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      200                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      165                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      179                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      141                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      135                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      160                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      124                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      165                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      130                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      171                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      175                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      126                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      185                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      158                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      107                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       92                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      118                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       89                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       85                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       86                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       87                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       59                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       58                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       49                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       28                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       32                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       11                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        60538                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      312.085896                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     184.679507                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     329.366687                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          22012     36.36%     36.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        14640     24.18%     60.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6552     10.82%     71.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3435      5.67%     77.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2639      4.36%     81.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1745      2.88%     84.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1057      1.75%     86.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1062      1.75%     87.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7396     12.22%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          60538                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6241                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        27.253805                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      580.495916                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6239     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-4095            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::45056-47103            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6241                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6241                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.046307                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.379346                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       13.281323                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5473     87.69%     87.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              55      0.88%     88.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              66      1.06%     89.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              37      0.59%     90.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             284      4.55%     94.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              48      0.77%     95.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              17      0.27%     95.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              11      0.18%     95.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51               9      0.14%     96.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               6      0.10%     96.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               4      0.06%     96.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              13      0.21%     96.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             157      2.52%     99.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               4      0.06%     99.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               3      0.05%     99.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               5      0.08%     99.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               5      0.08%     99.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               2      0.03%     99.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               1      0.02%     99.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               4      0.06%     99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.02%     99.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.02%     99.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             8      0.13%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            15      0.24%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             2      0.03%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             1      0.02%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.02%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             2      0.03%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             1      0.02%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             3      0.05%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-187             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6241                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1691091750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4880391750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    850480000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        9941.98                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29782.48                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           3.81                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.79                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        3.80                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.79                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  28691.98                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           3.82                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.81                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        3.81                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.80                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.79                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     139443                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     93842                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.93                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.21                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9562502.16                       # Average gap between requests
-system.physmem.pageHitRate                      79.09                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  244104840                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  133192125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 697678800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                416203920                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           186735603600                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            86851227465                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1639211384250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1914289395000                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.567370                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2726812979000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     95468100000                       # Time in different power states
+system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        26.93                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     140142                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     94524                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.39                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.54                       # Row buffer hit rate for writes
+system.physmem.avgGap                      9534982.29                       # Average gap between requests
+system.physmem.pageHitRate                      79.49                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  235894680                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  128712375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 691064400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                413670240                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           186366389040                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            83561921055                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1638705050250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1910102702040                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.426569                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2725994839000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     95279340000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     36713387250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     32067469750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  222067440                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  121167750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 629795400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                392234400                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           186735603600                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            85246386480                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1640619139500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1913966394570                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.454393                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2729170897750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     95468100000                       # Time in different power states
+system.physmem_1.actEnergy                  221772600                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  121006875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 635676600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                397036080                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           186366389040                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            82367679285                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1639752630750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1909862191230                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.342278                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2727746913750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     95279340000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     34358196250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     30317548250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
 system.realview.nvmem.bytes_read::cpu.inst          512                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           512                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu.inst          512                       # Number of instructions bytes read from this memory
@@ -326,30 +330,30 @@ system.realview.nvmem.bw_inst_read::cpu.inst          179
 system.realview.nvmem.bw_inst_read::total          179                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.inst          179                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total             179                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups                31086887                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          16880230                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           2489626                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             18671153                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                10424859                       # Number of BTB hits
+system.cpu.branchPred.lookups                31062999                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          16869066                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           2486744                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             18728785                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                10415318                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             55.834040                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 7822517                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            1524102                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups         3081262                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits            2891722                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses           189540                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted       109414                       # Number of mispredicted indirect branches.
+system.cpu.branchPred.BTBHitPct             55.611285                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 7833584                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            1520957                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         3075291                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits            2886933                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses           188358                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted       109527                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -379,57 +383,59 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks                     67741                       # Table walker walks requested
-system.cpu.dtb.walker.walksShort                67741                       # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walksShortTerminationLevel::Level1        45017                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksShortTerminationLevel::Level2        22724                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walkWaitTime::samples        67741                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0           67741    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total        67741                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples         7842                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 12675.784239                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 10493.995103                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev  8407.754568                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-32767         7835     99.91%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-163839            6      0.08%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-294911            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total         7842                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples    517795000                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0       517795000    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total    517795000                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K          6453     82.29%     82.29% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::1M          1389     17.71%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total         7842                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        67741                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.walks                     68003                       # Table walker walks requested
+system.cpu.dtb.walker.walksShort                68003                       # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1        44606                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2        23397                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walkWaitTime::samples        68003                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0           68003    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total        68003                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples         7897                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 10035.266557                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean  8419.099443                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev  6813.200210                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-16383         7021     88.91%     88.91% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::16384-32767          869     11.00%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::81920-98303            5      0.06%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::147456-163839            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::196608-212991            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total         7897                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples    271390000                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0       271390000    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total    271390000                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K          6503     82.35%     82.35% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::1M          1394     17.65%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total         7897                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        68003                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total        67741                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7842                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total        68003                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7897                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7842                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total        75583                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7897                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total        75900                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     24787454                       # DTB read hits
-system.cpu.dtb.read_misses                      60877                       # DTB read misses
-system.cpu.dtb.write_hits                    19460962                       # DTB write hits
-system.cpu.dtb.write_misses                      6864                       # DTB write misses
+system.cpu.dtb.read_hits                     24771188                       # DTB read hits
+system.cpu.dtb.read_misses                      61134                       # DTB read misses
+system.cpu.dtb.write_hits                    19449290                       # DTB write hits
+system.cpu.dtb.write_misses                      6869                       # DTB write misses
 system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     4270                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                      1452                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   1793                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries                     4279                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                      1418                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                   1775                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                       741                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 24848331                       # DTB read accesses
-system.cpu.dtb.write_accesses                19467826                       # DTB write accesses
+system.cpu.dtb.perms_faults                       770                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 24832322                       # DTB read accesses
+system.cpu.dtb.write_accesses                19456159                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          44248416                       # DTB hits
-system.cpu.dtb.misses                           67741                       # DTB misses
-system.cpu.dtb.accesses                      44316157                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.hits                          44220478                       # DTB hits
+system.cpu.dtb.misses                           68003                       # DTB misses
+system.cpu.dtb.accesses                      44288481                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -459,37 +465,39 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks                      5895                       # Table walker walks requested
-system.cpu.itb.walker.walksShort                 5895                       # Table walker walks initiated with short descriptors
-system.cpu.itb.walker.walksShortTerminationLevel::Level1          321                       # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksShortTerminationLevel::Level2         5574                       # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walkWaitTime::samples         5895                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0            5895    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total         5895                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples         3205                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 12907.644306                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 10876.938214                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev  7322.763550                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-16383         2473     77.16%     77.16% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::16384-32767          731     22.81%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-147455            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total         3205                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples    517140500                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0       517140500    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total    517140500                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K          2896     90.36%     90.36% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::1M           309      9.64%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total         3205                       # Table walker page sizes translated
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.walks                      5856                       # Table walker walks requested
+system.cpu.itb.walker.walksShort                 5856                       # Table walker walks initiated with short descriptors
+system.cpu.itb.walker.walksShortTerminationLevel::Level1          325                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksShortTerminationLevel::Level2         5531                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walkWaitTime::samples         5856                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0            5856    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total         5856                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples         3193                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 10411.838396                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean  8598.635311                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev  6896.589649                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-8191         1843     57.72%     57.72% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::8192-16383          807     25.27%     82.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::16384-24575          535     16.76%     99.75% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::24576-32767            7      0.22%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::81920-90111            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total         3193                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples    270980500                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0       270980500    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total    270980500                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K          2883     90.29%     90.29% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::1M           310      9.71%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total         3193                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst         5895                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total         5895                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst         5856                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total         5856                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3205                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total         3205                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total         9100                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                     57517109                       # ITB inst hits
-system.cpu.itb.inst_misses                       5895                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3193                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total         3193                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total         9049                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                     57483193                       # ITB inst hits
+system.cpu.itb.inst_misses                       5856                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -498,45 +506,45 @@ system.cpu.itb.flush_tlb                           64                       # Nu
 system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     2926                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     2912                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                      8405                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                      8279                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 57523004                       # ITB inst accesses
-system.cpu.itb.hits                          57517109                       # DTB hits
-system.cpu.itb.misses                            5895                       # DTB misses
-system.cpu.itb.accesses                      57523004                       # DTB accesses
-system.cpu.numPwrStateTransitions                6068                       # Number of power state transitions
-system.cpu.pwrStateClkGateDist::samples          3034                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::mean     887205873.057680                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::stdev    17434832353.062756                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::underflows         2969     97.86%     97.86% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1000-5e+10           59      1.94%     99.80% # Distribution of time spent in the clock gated state
+system.cpu.itb.inst_accesses                 57489049                       # ITB inst accesses
+system.cpu.itb.hits                          57483193                       # DTB hits
+system.cpu.itb.misses                            5856                       # DTB misses
+system.cpu.itb.accesses                      57489049                       # DTB accesses
+system.cpu.numPwrStateTransitions                6066                       # Number of power state transitions
+system.cpu.pwrStateClkGateDist::samples          3033                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean     888351102.639301                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev    17445509399.919735                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::underflows         2969     97.89%     97.89% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1000-5e+10           58      1.91%     99.80% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::1.5e+11-2e+11            1      0.03%     99.84% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::2e+11-2.5e+11            1      0.03%     99.87% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::2.5e+11-3e+11            1      0.03%     99.90% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::4.5e+11-5e+11            3      0.10%    100.00% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::max_value 499967463084                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::total            3034                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateResidencyTicks::ON    167214720643                       # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::CLK_GATED 2691782618857                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                        334432391                       # number of cpu cycles simulated
+system.cpu.pwrStateClkGateDist::max_value 499967553028                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::total            3033                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateResidencyTicks::ON    158975005195                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 2694368894305                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                        317952965                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   112217626                       # Number of instructions committed
-system.cpu.committedOps                     135683579                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       7838903                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends                      3034                       # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles                   5383627132                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi                               2.980213                       # CPI: cycles per instruction
-system.cpu.ipc                               0.335547                       # IPC: instructions per cycle
+system.cpu.committedInsts                   112146750                       # Number of instructions committed
+system.cpu.committedOps                     135598813                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                       7821624                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                      3033                       # Number of times Execute suspended instruction fetching
+system.cpu.quiesceCycles                   5388799101                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi                               2.835151                       # CPI: cycles per instruction
+system.cpu.ipc                               0.352715                       # IPC: instructions per cycle
 system.cpu.op_class_0::No_OpClass                2337      0.00%      0.00% # Class of committed instruction
-system.cpu.op_class_0::IntAlu                90974393     67.05%     67.05% # Class of committed instruction
-system.cpu.op_class_0::IntMult                 113069      0.08%     67.13% # Class of committed instruction
+system.cpu.op_class_0::IntAlu                90918529     67.05%     67.05% # Class of committed instruction
+system.cpu.op_class_0::IntMult                 113133      0.08%     67.13% # Class of committed instruction
 system.cpu.op_class_0::IntDiv                       0      0.00%     67.13% # Class of committed instruction
 system.cpu.op_class_0::FloatAdd                     0      0.00%     67.13% # Class of committed instruction
 system.cpu.op_class_0::FloatCmp                     0      0.00%     67.13% # Class of committed instruction
@@ -560,666 +568,663 @@ system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     67.13% # Cl
 system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     67.13% # Class of committed instruction
 system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     67.13% # Class of committed instruction
 system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     67.13% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMisc             8525      0.01%     67.14% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc             8487      0.01%     67.14% # Class of committed instruction
 system.cpu.op_class_0::SimdFloatMult                0      0.00%     67.14% # Class of committed instruction
 system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     67.14% # Class of committed instruction
 system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     67.14% # Class of committed instruction
-system.cpu.op_class_0::MemRead               24296976     17.91%     85.05% # Class of committed instruction
-system.cpu.op_class_0::MemWrite              20288279     14.95%    100.00% # Class of committed instruction
+system.cpu.op_class_0::MemRead               24279497     17.91%     85.05% # Class of committed instruction
+system.cpu.op_class_0::MemWrite              20276830     14.95%    100.00% # Class of committed instruction
 system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
-system.cpu.op_class_0::total                135683579                       # Class of committed instruction
+system.cpu.op_class_0::total                135598813                       # Class of committed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     3034                       # number of quiesce instructions executed
-system.cpu.tickCycles                       218593350                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       115839041                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements            844257                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.899744                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            42705909                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            844769                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             50.553357                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         594757500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.899744                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999804                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999804                       # Average percentage of cache occupancy
+system.cpu.kern.inst.quiesce                     3033                       # number of quiesce instructions executed
+system.cpu.tickCycles                       217828985                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       100123980                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements            845168                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.946266                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            42678256                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            845680                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             50.466200                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         322165500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.946266                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999895                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999895                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           97                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          362                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           53                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          354                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           59                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         176476854                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        176476854                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data     23143905                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        23143905                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     18298058                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       18298058                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       356964                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        356964                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       443845                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       443845                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       460247                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       460247                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      41441963                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         41441963                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     41798927                       # number of overall hits
-system.cpu.dcache.overall_hits::total        41798927                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       464900                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        464900                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       548479                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       548479                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       169396                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       169396                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        22217                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        22217                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses         176368054                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        176368054                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data     23126363                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23126363                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     18288488                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       18288488                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       357151                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        357151                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       443374                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       443374                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       459996                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       459996                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      41414851                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         41414851                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     41772002                       # number of overall hits
+system.cpu.dcache.overall_hits::total        41772002                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       466466                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        466466                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       547177                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       547177                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       169147                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       169147                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        22423                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        22423                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      1013379                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1013379                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1182775                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1182775                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   7474682000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   7474682000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  35725670480                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  35725670480                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    298069500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    298069500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       167000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       167000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  43200352480                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  43200352480                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  43200352480                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  43200352480                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     23608805                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     23608805                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     18846537                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     18846537                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       526360                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       526360                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       466062                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       466062                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       460249                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       460249                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     42455342                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     42455342                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     42981702                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     42981702                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.019692                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.019692                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.029102                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.029102                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.321825                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.321825                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.047670                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.047670                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_misses::cpu.data      1013643                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1013643                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1182790                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1182790                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   6859105500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   6859105500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  23368526480                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  23368526480                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    290513500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    290513500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       169000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       169000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  30227631980                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  30227631980                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  30227631980                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  30227631980                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     23592829                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     23592829                       # number of ReadReq accesses(hits+misses)
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+system.cpu.dcache.SoftPFReq_accesses::total       526298                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       465797                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       465797                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       459998                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       459998                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     42428494                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     42428494                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     42954792                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     42954792                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.019772                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.019772                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.029050                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.029050                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.321390                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.321390                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.048139                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.048139                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000004                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.023869                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.023869                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.027518                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.027518                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16078.042590                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16078.042590                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65135.894866                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 65135.894866                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13416.280326                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13416.280326                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        83500                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total        83500                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 42630.005635                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 42630.005635                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 36524.573549                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 36524.573549                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          235                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.023891                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.023891                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.027536                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.027536                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14704.406109                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14704.406109                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42707.435583                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 42707.435583                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12956.049592                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12956.049592                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        84500                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total        84500                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 29820.786983                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 29820.786983                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 25556.211990                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 25556.211990                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          210                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                22                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                21                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    10.681818                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs           10                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks       701092                       # number of writebacks
-system.cpu.dcache.writebacks::total            701092                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        45747                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        45747                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       249493                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       249493                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        13970                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        13970                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       295240                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       295240                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       295240                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       295240                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       419153                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       419153                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       298986                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       298986                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       121200                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       121200                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8247                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total         8247                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       700399                       # number of writebacks
+system.cpu.dcache.writebacks::total            700399                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        45619                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        45619                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       248851                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       248851                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        14095                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        14095                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       294470                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       294470                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       294470                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       294470                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       420847                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       420847                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       298326                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       298326                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       121014                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       121014                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8328                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total         8328                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       718139                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       718139                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       839339                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       839339                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31130                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.ReadReq_mshr_uncacheable::total        31130                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27584                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58714                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total        58714                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6559792500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   6559792500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19260233000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  19260233000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1701865000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1701865000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    115452000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    115452000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       165000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       165000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  25820025500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  25820025500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  27521890500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  27521890500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6298878000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6298878000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6298878000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   6298878000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017754                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017754                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015864                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015864                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.230261                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.230261                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017695                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017695                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data       719173                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       719173                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       840187                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       840187                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31128                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.ReadReq_mshr_uncacheable::total        31128                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27583                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total        27583                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58711                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total        58711                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6004353500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   6004353500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12472700000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  12472700000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1605906500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1605906500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    111255000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    111255000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       167000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       167000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  18477053500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  18477053500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  20082960000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  20082960000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6301797000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6301797000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6301797000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   6301797000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017838                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017838                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015838                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015838                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.229934                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.229934                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017879                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017879                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000004                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016915                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.016915                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019528                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.019528                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15650.114636                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15650.114636                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64418.511235                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64418.511235                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14041.790429                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14041.790429                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13999.272463                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13999.272463                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        82500                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        82500                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35954.077832                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 35954.077832                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32789.957931                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 32789.957931                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 202341.085769                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202341.085769                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107280.682631                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107280.682631                       # average overall mshr uncacheable latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements           2894242                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.201941                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            54613603                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           2894754                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             18.866406                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       18510731500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.201941                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.998441                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.998441                       # Average percentage of cache occupancy
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016950                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.016950                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019560                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.019560                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14267.307359                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14267.307359                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41808.960667                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41808.960667                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13270.419125                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13270.419125                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13359.149856                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13359.149856                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        83500                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        83500                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25692.084519                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25692.084519                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23902.964459                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 23902.964459                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 202447.860447                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202447.860447                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107335.882543                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107335.882543                       # average overall mshr uncacheable latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements           2889133                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.392140                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            54584955                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           2889645                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             18.889848                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       15688442500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.392140                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.998813                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.998813                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          107                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          205                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          200                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          112                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          203                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          197                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          60403134                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         60403134                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst     54613603                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        54613603                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      54613603                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         54613603                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     54613603                       # number of overall hits
-system.cpu.icache.overall_hits::total        54613603                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      2894766                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       2894766                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      2894766                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        2894766                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      2894766                       # number of overall misses
-system.cpu.icache.overall_misses::total       2894766                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  40456280000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  40456280000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  40456280000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  40456280000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  40456280000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  40456280000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     57508369                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     57508369                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     57508369                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     57508369                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     57508369                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     57508369                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.050336                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.050336                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.050336                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.050336                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.050336                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.050336                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13975.665045                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13975.665045                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13975.665045                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13975.665045                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13975.665045                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13975.665045                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          60364268                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         60364268                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst     54584955                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        54584955                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      54584955                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         54584955                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     54584955                       # number of overall hits
+system.cpu.icache.overall_hits::total        54584955                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      2889657                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       2889657                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      2889657                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        2889657                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      2889657                       # number of overall misses
+system.cpu.icache.overall_misses::total       2889657                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  39245614500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  39245614500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  39245614500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  39245614500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  39245614500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  39245614500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     57474612                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     57474612                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     57474612                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     57474612                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     57474612                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     57474612                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.050277                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.050277                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.050277                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.050277                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.050277                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.050277                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13581.409316                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13581.409316                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13581.409316                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13581.409316                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13581.409316                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13581.409316                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks      2894242                       # number of writebacks
-system.cpu.icache.writebacks::total           2894242                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      2894766                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      2894766                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      2894766                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      2894766                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      2894766                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      2894766                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         3758                       # number of ReadReq MSHR uncacheable
-system.cpu.icache.ReadReq_mshr_uncacheable::total         3758                       # number of ReadReq MSHR uncacheable
-system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3758                       # number of overall MSHR uncacheable misses
-system.cpu.icache.overall_mshr_uncacheable_misses::total         3758                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  37561515000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  37561515000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  37561515000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  37561515000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  37561515000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  37561515000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    485617000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    485617000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    485617000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total    485617000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.050336                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.050336                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.050336                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.050336                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.050336                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.050336                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12975.665391                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12975.665391                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12975.665391                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12975.665391                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12975.665391                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12975.665391                       # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 129222.192656                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 129222.192656                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 129222.192656                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 129222.192656                       # average overall mshr uncacheable latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements            96413                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65014.111647                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            7029815                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           161656                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            43.486261                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 47147.953940                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    65.794382                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.010019                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 12263.315434                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  5537.037871                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.719421                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.001004                       # Average percentage of cache occupancy
+system.cpu.icache.writebacks::writebacks      2889133                       # number of writebacks
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+system.cpu.icache.ReadReq_mshr_uncacheable::total         3267                       # number of ReadReq MSHR uncacheable
+system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3267                       # number of overall MSHR uncacheable misses
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+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    258265000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    258265000                       # number of ReadReq MSHR uncacheable cycles
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+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.050277                       # mshr miss rate for ReadReq accesses
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+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.050277                       # mshr miss rate for demand accesses
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12581.409662                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12581.409662                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12581.409662                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12581.409662                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12581.409662                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12581.409662                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 79052.647689                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 79052.647689                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 79052.647689                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 79052.647689                       # average overall mshr uncacheable latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.replacements            96859                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65151.144064                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            7317028                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           162271                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            45.091409                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      94922732000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    70.044406                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.023437                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 12290.016649                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 52791.059572                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.001069                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.187123                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.084488                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.992037                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023           54                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65189                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4           54                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           26                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           85                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2263                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6860                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55955                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000824                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994705                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         60474648                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        60474648                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        73812                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         4869                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total          78681                       # number of ReadReq hits
-system.cpu.l2cache.WritebackDirty_hits::writebacks       701092                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       701092                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks      2843365                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total      2843365                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           49                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           49                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       165406                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       165406                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      2871798                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total      2871798                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       534162                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       534162                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker        73812                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker         4869                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst      2871798                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       699568                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         3650047                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker        73812                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker         4869                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst      2871798                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       699568                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        3650047                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker          125                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          127                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         2735                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         2735                       # number of UpgradeReq misses
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.187531                       # Average percentage of cache occupancy
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+system.cpu.l2cache.tags.occ_task_id_blocks::1023           63                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65349                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4           63                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2           80                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4600                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        60668                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000961                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997147                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         60051875                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        60051875                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        67793                       # number of ReadReq hits
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+system.cpu.l2cache.WritebackDirty_hits::writebacks       700399                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total       700399                       # number of WritebackDirty hits
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+system.cpu.l2cache.WritebackClean_hits::total      2838445                       # number of WritebackClean hits
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 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       130801                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       130801                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        22943                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        22943                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data        14433                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total        14433                       # number of ReadSharedReq misses
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-system.cpu.l2cache.demand_misses::cpu.inst        22943                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       145234                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        168304                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker          125                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        22943                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       145234                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       168304                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker     17568500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       265500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     17834000                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      2884500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total      2884500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       162000                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::total       162000                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16851679500                       # number of ReadExReq miss cycles
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-system.cpu.l2cache.WritebackDirty_accesses::total       701092                       # number of WritebackDirty accesses(hits+misses)
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 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
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-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.001691                       # miss rate for ReadReq accesses
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 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.441586                       # miss rate for ReadExReq accesses
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-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  1054.661792                       # average UpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        81000                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        81000                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 128834.485210                       # average ReadExReq miss latency
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 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks        88095                       # number of writebacks
-system.cpu.l2cache.writebacks::total            88095                       # number of writebacks
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-system.cpu.l2cache.demand_mshr_hits::cpu.data          141                       # number of demand (read+write) MSHR hits
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-system.cpu.l2cache.overall_mshr_hits::cpu.data          141                       # number of overall MSHR hits
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-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2735                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         2735                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks        88448                       # number of writebacks
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+system.cpu.l2cache.demand_mshr_hits::total          154                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           18                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data          136                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total          154                       # number of overall MSHR hits
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+system.cpu.l2cache.UpgradeReq_mshr_misses::total            5                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       130801                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       130801                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        22923                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        22923                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        14292                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total        14292                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker          125                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        22923                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       145093                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       168143                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker          125                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        22923                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       145093                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       168143                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         3758                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31130                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total        34888                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        27584                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         3758                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58714                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total        62472                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     16318500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       245500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     16564000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    186014500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    186014500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       142000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       142000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  15543669500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  15543669500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2767321000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2767321000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1745198500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1745198500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker     16318500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       245500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2767321000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  17288868000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  20072753000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker     16318500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       245500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2767321000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  17288868000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  20072753000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    426993000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5909675000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6336668000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    426993000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5909675000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   6336668000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001691                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000411                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001612                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.982399                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.982399                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       129240                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       129240                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        22927                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        22927                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        14518                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        14518                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker          120                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            1                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        22927                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       143758                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       166806                       # number of demand (read+write) MSHR misses
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+system.cpu.l2cache.overall_mshr_misses::cpu.inst        22927                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       143758                       # number of overall MSHR misses
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+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         3267                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31128                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::total        34395                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        27583                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::total        27583                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         3267                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58711                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total        61978                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      9089000                       # number of ReadReq MSHR miss cycles
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::total      9162500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        95500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        95500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       144000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       144000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8947364000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8947364000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1624414500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1624414500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1078119000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1078119000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      9089000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker        73500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1624414500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  10025483000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  11659060000                       # number of demand (read+write) MSHR miss cycles
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+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1624414500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  10025483000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  11659060000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    207499500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5912622000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6120121500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    207499500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5912622000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   6120121500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001767                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000302                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001699                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.001780                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.001780                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.441586                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.441586                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.007919                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.007919                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.026052                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.026052                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001691                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000411                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.007919                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.171748                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.044036                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001691                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000411                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.007919                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.171748                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.044036                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker       130548                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker       122750                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 130425.196850                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68012.614260                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68012.614260                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        71000                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        71000                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 118834.485210                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 118834.485210                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120722.462156                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120722.462156                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122110.166527                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122110.166527                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker       130548                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker       122750                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120722.462156                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119157.147485                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119379.058302                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker       130548                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker       122750                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120722.462156                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119157.147485                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119379.058302                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113622.405535                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189838.580148                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181628.869525                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113622.405535                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100651.888817                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 101432.129594                       # average overall mshr uncacheable latency
-system.cpu.toL2Bus.snoop_filter.tot_requests      7509695                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      3770160                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        58111                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops          594                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops          594                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.437328                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.437328                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.007934                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.007934                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.026388                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.026388                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001767                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000302                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.007934                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.169986                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.043821                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001767                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000302                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.007934                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.169986                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.043821                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75741.666667                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        73500                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 75723.140496                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        19100                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        19100                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        72000                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        72000                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69230.609718                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69230.609718                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70851.594190                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70851.594190                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74260.848602                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74260.848602                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75741.666667                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        73500                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70851.594190                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69738.609330                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69895.927005                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75741.666667                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        73500                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70851.594190                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69738.609330                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69895.927005                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63513.774105                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189945.451041                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 177936.371566                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63513.774105                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100707.226925                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 98746.676240                       # average overall mshr uncacheable latency
+system.cpu.toL2Bus.snoop_filter.tot_requests      7504035                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      3768706                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        58030                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops          170                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops          170                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadReq         136822                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       3580395                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         27584                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        27584                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       825389                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean      2894242                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       151717                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2784                       # Transaction distribution
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadReq         137182                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       3577165                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         27583                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        27583                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       788847                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      2889133                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       153180                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2809                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2786                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       296207                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       296207                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      2894766                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       548829                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      8691264                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2657074                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        16340                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       164402                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          11529080                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    370735360                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     99133929                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        19484                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       295748                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          470184521                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      192671                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic               8062744                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples      4076067                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.021486                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.144999                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2811                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       295522                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       295522                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      2889657                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       550405                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq         4412                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      8674948                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2659767                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        14702                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       159313                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          11508730                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    370049536                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     99142941                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        13260                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       271652                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          469477389                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      133226                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic               5798108                       # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples      4004431                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.022424                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.148057                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            3988487     97.85%     97.85% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              87580      2.15%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            3914637     97.76%     97.76% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              89794      2.24%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        4076067                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     7431755500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        4004431                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     7421943500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       380377                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       275377                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    4348377811                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    4339894977                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1313662211                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1315039189                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      11470497                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      11390493                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      90488952                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      91431936                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
+system.iobus.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
 system.iobus.trans_dist::ReadReq                30183                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30183                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
@@ -1270,66 +1275,66 @@ system.iobus.pkt_size_system.bridge.master::total       159125
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321104                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321104                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2480229                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             46348000                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy             46364500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy               107000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               330500                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               324000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                30500                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy                15000                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy                14000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy                85500                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy                88000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer8.occupancy               623500                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy               618000                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy               22000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy               11500                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer14.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer15.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               51000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               50000                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer19.occupancy                2500                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer20.occupancy               10500                       # Layer occupancy (ticks)
+system.iobus.reqLayer20.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer21.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6076000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6096500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            38906500                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            39117500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           187130005                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           187733842                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer3.occupancy            36740000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
 system.iocache.tags.replacements                36424                       # number of replacements
-system.iocache.tags.tagsinuse                1.038429                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.032370                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36440                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         275018797000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.038429                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.064902                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.064902                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         270830421000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.032370                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.064523                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.064523                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
 system.iocache.tags.tag_accesses               328122                       # Number of tag accesses
 system.iocache.tags.data_accesses              328122                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
+system.iocache.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
 system.iocache.ReadReq_misses::realview.ide          234                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              234                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
@@ -1338,14 +1343,14 @@ system.iocache.demand_misses::realview.ide        36458                       #
 system.iocache.demand_misses::total             36458                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide        36458                       # number of overall misses
 system.iocache.overall_misses::total            36458                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     29054877                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     29054877                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4548884128                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4548884128                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide   4577939005                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   4577939005                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide   4577939005                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   4577939005                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     29494377                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     29494377                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4278402465                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4278402465                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide   4307896842                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   4307896842                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide   4307896842                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   4307896842                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          234                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            234                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
@@ -1362,14 +1367,14 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 124166.141026                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 124166.141026                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125576.527385                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 125576.527385                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 125567.475040                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 125567.475040                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 125567.475040                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 125567.475040                       # average overall miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 126044.346154                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 126044.346154                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118109.608685                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118109.608685                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 118160.536563                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 118160.536563                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 118160.536563                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 118160.536563                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
@@ -1386,14 +1391,14 @@ system.iocache.demand_mshr_misses::realview.ide        36458
 system.iocache.demand_mshr_misses::total        36458                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide        36458                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total        36458                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     17354877                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     17354877                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2736261614                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2736261614                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   2753616491                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   2753616491                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   2753616491                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   2753616491                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     17794377                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     17794377                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2465093924                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2465093924                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   2482888301                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   2482888301                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   2482888301                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   2482888301                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1402,84 +1407,90 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74166.141026                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 74166.141026                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75537.257454                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75537.257454                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 75528.457156                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 75528.457156                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 75528.457156                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 75528.457156                       # average overall mshr miss latency
-system.membus.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq               34888                       # Transaction distribution
-system.membus.trans_dist::ReadResp              72464                       # Transaction distribution
-system.membus.trans_dist::WriteReq              27584                       # Transaction distribution
-system.membus.trans_dist::WriteResp             27584                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       124285                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             8552                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4603                       # Transaction distribution
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76044.346154                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 76044.346154                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68051.400287                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68051.400287                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 68102.701766                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 68102.701766                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 68102.701766                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 68102.701766                       # average overall mshr miss latency
+system.membus.snoop_filter.tot_requests        336558                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests       137845                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests          488                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
+system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadReq               34395                       # Transaction distribution
+system.membus.trans_dist::ReadResp              72195                       # Transaction distribution
+system.membus.trans_dist::WriteReq              27583                       # Transaction distribution
+system.membus.trans_dist::WriteResp             27583                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       124638                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             8645                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              128                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            128933                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           128933                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         37576                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            129117                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           129117                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         37800                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           16                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2074                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       450661                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       558229                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2068                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       446466                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       554028                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72897                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total        72897                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 631126                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 626925                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          512                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4148                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16521376                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16685161                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4136                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16538656                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16702429                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                19002281                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                19019549                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              504                       # Total snoops (count)
 system.membus.snoopTraffic                      32128                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            402659                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::samples            265249                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.018541                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.134898                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  402659    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  260331     98.15%     98.15% # Request fanout histogram
+system.membus.snoop_fanout::1                    4918      1.85%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              402659                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            92669500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              265249                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            92904500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                8000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1708000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1693000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           910164615                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           906764526                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          990045000                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          989491000                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy            1264123                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy            1228623                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
 system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
 system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
 system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
 system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -1511,28 +1522,28 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
 system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500                       # Cumulative time (in ticks) in various power states
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500                       # Cumulative time (in ticks) in various power states
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
index 410d93856..e59cf51bf 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
@@ -1,122 +1,122 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.832894                       # Number of seconds simulated
-sim_ticks                                2832894126500                       # Number of ticks simulated
-final_tick                               2832894126500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.827853                       # Number of seconds simulated
+sim_ticks                                2827853096000                       # Number of ticks simulated
+final_tick                               2827853096000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  74117                       # Simulator instruction rate (inst/s)
-host_op_rate                                    89897                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1856270381                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 579324                       # Number of bytes of host memory used
-host_seconds                                  1526.12                       # Real time elapsed on the host
-sim_insts                                   113111333                       # Number of instructions simulated
-sim_ops                                     137193850                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  70378                       # Simulator instruction rate (inst/s)
+host_op_rate                                    85367                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1758794234                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 588628                       # Number of bytes of host memory used
+host_seconds                                  1607.84                       # Real time elapsed on the host
+sim_insts                                   113155640                       # Number of instructions simulated
+sim_ops                                     137255479                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.dtb.walker         1344                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker          448                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1321536                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9400296                       # Number of bytes read from this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.dtb.walker         1024                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker          384                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1322240                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9790440                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10724584                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1321536                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1321536                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8031104                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             11115048                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1322240                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1322240                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8407168                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8048628                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker           21                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            7                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              22896                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             147400                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           8424692                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker           16                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker            6                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              22907                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             153496                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                170339                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          125486                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                176440                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          131362                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               129867                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker            474                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker            158                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               466497                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3318266                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               135743                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker            362                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker            136                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               467577                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3462146                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              339                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3785734                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          466497                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             466497                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2834947                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data                6186                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2841133                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2834947                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           474                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker           158                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              466497                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3324452                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                 3930561                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          467577                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             467577                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2972986                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data                6197                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2979183                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2972986                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           362                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker           136                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              467577                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3468343                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             339                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6626867                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        170340                       # Number of read requests accepted
-system.physmem.writeReqs                       129867                       # Number of write requests accepted
-system.physmem.readBursts                      170340                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     129867                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10892352                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      9408                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8061056                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10724648                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8048628                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      147                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    3887                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bw_total::total                6909744                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        176441                       # Number of read requests accepted
+system.physmem.writeReqs                       135743                       # Number of write requests accepted
+system.physmem.readBursts                      176441                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     135743                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 11282432                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      9792                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8437824                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  11115112                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8424692                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      153                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    3886                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11036                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10507                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               10862                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               11068                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               13101                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10327                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               10639                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10985                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10460                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10167                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10435                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9511                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               9930                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10756                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10401                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10008                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8291                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7865                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8399                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8558                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7751                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7713                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7781                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8111                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7871                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7662                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7844                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7196                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7582                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8119                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7846                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7365                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               11743                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               11227                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               11041                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               10652                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               13485                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               11002                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               11432                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               11844                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10383                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10947                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10471                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9569                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10361                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              11110                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10361                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10660                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8764                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                8604                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8676                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8310                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                8074                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                8230                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8228                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8800                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7938                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                8472                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               8080                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7388                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               8035                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8487                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7854                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7901                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          17                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2832893894500                       # Total gap between requests
+system.physmem.numWrRetry                           4                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2827852861000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     542                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                    2996                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  166788                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  172889                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 125486                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    150867                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     16439                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      2150                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       721                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 131362                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    155219                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     17999                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      2225                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       829                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         6                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
@@ -160,164 +160,164 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1883                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2891                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6675                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6069                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     7147                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6554                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6489                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6585                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7283                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7048                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7591                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8460                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7511                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7926                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     8975                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7507                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7129                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7208                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1140                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      304                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      257                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      207                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      209                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      194                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      202                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      174                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      169                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      132                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      146                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      130                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      137                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      122                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      108                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      113                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      138                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       79                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      117                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       55                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       81                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       48                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       79                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       69                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       54                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       35                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       56                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        62108                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      305.167515                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     180.813202                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     324.494619                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          23016     37.06%     37.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        15104     24.32%     61.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6524     10.50%     71.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3665      5.90%     77.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2528      4.07%     81.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1637      2.64%     84.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1479      2.38%     86.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1102      1.77%     88.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7053     11.36%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          62108                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6142                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        27.706936                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      569.623530                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6141     99.98%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6142                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6142                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.507001                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.506831                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       14.607971                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5435     88.49%     88.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             129      2.10%     90.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              31      0.50%     91.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              49      0.80%     91.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              32      0.52%     92.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              17      0.28%     92.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              48      0.78%     93.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              14      0.23%     93.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             140      2.28%     95.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              11      0.18%     96.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               8      0.13%     96.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               8      0.13%     96.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67              65      1.06%     97.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               1      0.02%     97.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              21      0.34%     97.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              93      1.51%     99.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               3      0.05%     99.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.02%     99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.02%     99.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               1      0.02%     99.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             2      0.03%     99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             3      0.05%     99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.02%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            11      0.18%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.02%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.02%     99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.03%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             7      0.11%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             1      0.02%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.02%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             1      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             2      0.03%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-211             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6142                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2108320500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5299439250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    850965000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12387.82                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::15                     2095                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2964                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5951                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6509                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6942                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6801                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7294                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7733                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     8218                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     8271                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     9582                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     9943                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     8295                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     8200                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     8031                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7326                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7196                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7152                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      364                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      327                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      266                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      134                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      133                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      125                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      139                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      101                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      130                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      109                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      104                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      129                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                       98                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      150                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      136                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       91                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       90                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       92                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       70                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       70                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       83                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       59                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       64                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       79                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       57                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       31                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       26                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       28                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       32                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       12                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       10                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        64990                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      303.434251                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     179.571710                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     325.070143                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          24166     37.18%     37.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        15993     24.61%     61.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6821     10.50%     72.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3792      5.83%     78.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2758      4.24%     82.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1633      2.51%     84.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1086      1.67%     86.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1085      1.67%     88.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7656     11.78%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          64990                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6662                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        26.461423                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      559.657587                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6661     99.98%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::45056-47103            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6662                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6662                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        19.790003                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.288798                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       12.351415                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5875     88.19%     88.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              70      1.05%     89.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              75      1.13%     90.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              36      0.54%     90.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             259      3.89%     94.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              62      0.93%     95.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              25      0.38%     96.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              19      0.29%     96.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51               9      0.14%     96.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               7      0.11%     96.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               3      0.05%     96.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               4      0.06%     96.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             160      2.40%     99.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               6      0.09%     99.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               8      0.12%     99.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               2      0.03%     99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               6      0.09%     99.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.02%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               3      0.05%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.02%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.02%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111            10      0.15%     99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.02%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.02%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             8      0.12%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.02%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             1      0.02%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.02%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             1      0.02%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             2      0.03%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             2      0.03%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6662                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2116192000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5421592000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    881440000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12004.17                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31137.82                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           3.84                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.85                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        3.79                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.84                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  30754.17                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           3.99                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.98                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        3.93                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.98                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.42                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     139937                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     94101                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.22                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  74.70                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9436468.49                       # Average gap between requests
-system.physmem.pageHitRate                      79.02                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  243454680                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  132837375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 690495000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                417759120                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           185030401920                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            83647548450                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1626357251250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1896519747795                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.465335                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2705450093000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     94596320000                       # Time in different power states
+system.physmem.avgWrQLen                        23.03                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     145153                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     97985                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.34                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  74.31                       # Row buffer hit rate for writes
+system.physmem.avgGap                      9058288.90                       # Average gap between requests
+system.physmem.pageHitRate                      78.90                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  256087440                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  139730250                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 720922800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                438605280                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           184701363600                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            81077227785                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1625589296250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1892923233405                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.386141                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2704185411500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     94428100000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     32840757000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     29235954750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  226081800                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  123358125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 637002600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                398422800                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           185030401920                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            82216233135                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1627612791000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1896244291380                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.368099                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2707556632500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     94596320000                       # Time in different power states
+system.physmem_1.actEnergy                  235236960                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  128353500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 654115800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                415724400                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           184701363600                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            80292349755                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1626277785750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1892704929765                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.308944                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2705344853000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     94428100000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     30741160500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     28080129500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
 system.realview.nvmem.bytes_read::cpu.inst          112                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           112                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu.inst          112                       # Number of instructions bytes read from this memory
@@ -330,30 +330,30 @@ system.realview.nvmem.bw_inst_read::cpu.inst           40
 system.realview.nvmem.bw_inst_read::total           40                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.inst           40                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total              40                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups                46812529                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          23980713                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1174980                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             29461889                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                13525990                       # Number of BTB hits
+system.cpu.branchPred.lookups                46859222                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          23995015                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1174256                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             29489294                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                13535968                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             45.910125                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                11726513                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              34925                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups         7916092                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits            7770128                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses           145964                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted        60126                       # Number of mispredicted indirect branches.
+system.cpu.branchPred.BTBHitPct             45.901296                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                11745095                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              35189                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         7931554                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits            7786304                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses           145250                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted        60170                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
 system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -383,47 +383,47 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.checker.dstage2_mmu.stage2_tlb.hits            0                       # DTB hits
 system.cpu.checker.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.cpu.checker.dtb.walker.walks              9712                       # Table walker walks requested
-system.cpu.checker.dtb.walker.walksShort         9712                       # Table walker walks initiated with short descriptors
-system.cpu.checker.dtb.walker.walkWaitTime::samples         9712                       # Table walker wait (enqueue to first request) latency
-system.cpu.checker.dtb.walker.walkWaitTime::0         9712    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.checker.dtb.walker.walkWaitTime::total         9712                       # Table walker wait (enqueue to first request) latency
-system.cpu.checker.dtb.walker.walksPending::samples    375751000                       # Table walker pending requests distribution
-system.cpu.checker.dtb.walker.walksPending::0    375751000    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.checker.dtb.walker.walksPending::total    375751000                       # Table walker pending requests distribution
-system.cpu.checker.dtb.walker.walkPageSizes::4K         6218     82.38%     82.38% # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkPageSizes::1M         1330     17.62%    100.00% # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkPageSizes::total         7548                       # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data         9712                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.cpu.checker.dtb.walker.walks              9867                       # Table walker walks requested
+system.cpu.checker.dtb.walker.walksShort         9867                       # Table walker walks initiated with short descriptors
+system.cpu.checker.dtb.walker.walkWaitTime::samples         9867                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walkWaitTime::0         9867    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walkWaitTime::total         9867                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walksPending::samples    230261000                       # Table walker pending requests distribution
+system.cpu.checker.dtb.walker.walksPending::0    230261000    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.checker.dtb.walker.walksPending::total    230261000                       # Table walker pending requests distribution
+system.cpu.checker.dtb.walker.walkPageSizes::4K         6312     81.94%     81.94% # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkPageSizes::1M         1391     18.06%    100.00% # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkPageSizes::total         7703                       # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data         9867                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total         9712                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data         7548                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total         9867                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data         7703                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total         7548                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin::total        17260                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total         7703                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin::total        17570                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
 system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
-system.cpu.checker.dtb.read_hits             24578721                       # DTB read hits
-system.cpu.checker.dtb.read_misses               8315                       # DTB read misses
-system.cpu.checker.dtb.write_hits            19634427                       # DTB write hits
-system.cpu.checker.dtb.write_misses              1397                       # DTB write misses
+system.cpu.checker.dtb.read_hits             24589623                       # DTB read hits
+system.cpu.checker.dtb.read_misses               8439                       # DTB read misses
+system.cpu.checker.dtb.write_hits            19639356                       # DTB write hits
+system.cpu.checker.dtb.write_misses              1428                       # DTB write misses
 system.cpu.checker.dtb.flush_tlb                  128                       # Number of times complete TLB was flushed
 system.cpu.checker.dtb.flush_tlb_mva             1834                       # Number of times TLB was flushed by MVA
 system.cpu.checker.dtb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.checker.dtb.flush_tlb_asid               0                       # Number of times TLB was flushed by ASID
-system.cpu.checker.dtb.flush_entries             4219                       # Number of entries that have been flushed from TLB
+system.cpu.checker.dtb.flush_entries             4257                       # Number of entries that have been flushed from TLB
 system.cpu.checker.dtb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
-system.cpu.checker.dtb.prefetch_faults           1636                       # Number of TLB faults due to prefetch
+system.cpu.checker.dtb.prefetch_faults           1816                       # Number of TLB faults due to prefetch
 system.cpu.checker.dtb.domain_faults                0                       # Number of TLB faults due to domain restrictions
 system.cpu.checker.dtb.perms_faults               445                       # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses         24587036                       # DTB read accesses
-system.cpu.checker.dtb.write_accesses        19635824                       # DTB write accesses
+system.cpu.checker.dtb.read_accesses         24598062                       # DTB read accesses
+system.cpu.checker.dtb.write_accesses        19640784                       # DTB write accesses
 system.cpu.checker.dtb.inst_accesses                0                       # ITB inst accesses
-system.cpu.checker.dtb.hits                  44213148                       # DTB hits
-system.cpu.checker.dtb.misses                    9712                       # DTB misses
-system.cpu.checker.dtb.accesses              44222860                       # DTB accesses
-system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
+system.cpu.checker.dtb.hits                  44228979                       # DTB hits
+system.cpu.checker.dtb.misses                    9867                       # DTB misses
+system.cpu.checker.dtb.accesses              44238846                       # DTB accesses
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -453,27 +453,27 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.checker.istage2_mmu.stage2_tlb.hits            0                       # DTB hits
 system.cpu.checker.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.checker.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.cpu.checker.itb.walker.walks              4825                       # Table walker walks requested
-system.cpu.checker.itb.walker.walksShort         4825                       # Table walker walks initiated with short descriptors
-system.cpu.checker.itb.walker.walkWaitTime::samples         4825                       # Table walker wait (enqueue to first request) latency
-system.cpu.checker.itb.walker.walkWaitTime::0         4825    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.checker.itb.walker.walkWaitTime::total         4825                       # Table walker wait (enqueue to first request) latency
-system.cpu.checker.itb.walker.walksPending::samples    375090000                       # Table walker pending requests distribution
-system.cpu.checker.itb.walker.walksPending::0    375090000    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.checker.itb.walker.walksPending::total    375090000                       # Table walker pending requests distribution
-system.cpu.checker.itb.walker.walkPageSizes::4K         2798     88.26%     88.26% # Table walker page sizes translated
-system.cpu.checker.itb.walker.walkPageSizes::1M          372     11.74%    100.00% # Table walker page sizes translated
-system.cpu.checker.itb.walker.walkPageSizes::total         3170                       # Table walker page sizes translated
+system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.cpu.checker.itb.walker.walks              4826                       # Table walker walks requested
+system.cpu.checker.itb.walker.walksShort         4826                       # Table walker walks initiated with short descriptors
+system.cpu.checker.itb.walker.walkWaitTime::samples         4826                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.itb.walker.walkWaitTime::0         4826    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.checker.itb.walker.walkWaitTime::total         4826                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.itb.walker.walksPending::samples    229845000                       # Table walker pending requests distribution
+system.cpu.checker.itb.walker.walksPending::0    229845000    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.checker.itb.walker.walksPending::total    229845000                       # Table walker pending requests distribution
+system.cpu.checker.itb.walker.walkPageSizes::4K         2798     88.24%     88.24% # Table walker page sizes translated
+system.cpu.checker.itb.walker.walkPageSizes::1M          373     11.76%    100.00% # Table walker page sizes translated
+system.cpu.checker.itb.walker.walkPageSizes::total         3171                       # Table walker page sizes translated
 system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst         4825                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total         4825                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst         4826                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total         4826                       # Table walker requests started/completed, data/inst
 system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst         3170                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total         3170                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin::total         7995                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.inst_hits            115810053                       # ITB inst hits
-system.cpu.checker.itb.inst_misses               4825                       # ITB inst misses
+system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst         3171                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total         3171                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin::total         7997                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.inst_hits            115857502                       # ITB inst hits
+system.cpu.checker.itb.inst_misses               4826                       # ITB inst misses
 system.cpu.checker.itb.read_hits                    0                       # DTB read hits
 system.cpu.checker.itb.read_misses                  0                       # DTB read misses
 system.cpu.checker.itb.write_hits                   0                       # DTB write hits
@@ -482,22 +482,22 @@ system.cpu.checker.itb.flush_tlb                  128                       # Nu
 system.cpu.checker.itb.flush_tlb_mva             1834                       # Number of times TLB was flushed by MVA
 system.cpu.checker.itb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.checker.itb.flush_tlb_asid               0                       # Number of times TLB was flushed by ASID
-system.cpu.checker.itb.flush_entries             2912                       # Number of entries that have been flushed from TLB
+system.cpu.checker.itb.flush_entries             2913                       # Number of entries that have been flushed from TLB
 system.cpu.checker.itb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
 system.cpu.checker.itb.prefetch_faults              0                       # Number of TLB faults due to prefetch
 system.cpu.checker.itb.domain_faults                0                       # Number of TLB faults due to domain restrictions
 system.cpu.checker.itb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
 system.cpu.checker.itb.read_accesses                0                       # DTB read accesses
 system.cpu.checker.itb.write_accesses               0                       # DTB write accesses
-system.cpu.checker.itb.inst_accesses        115814878                       # ITB inst accesses
-system.cpu.checker.itb.hits                 115810053                       # DTB hits
-system.cpu.checker.itb.misses                    4825                       # DTB misses
-system.cpu.checker.itb.accesses             115814878                       # DTB accesses
-system.cpu.checker.pwrStateResidencyTicks::ON 2832894126500                       # Cumulative time (in ticks) in various power states
-system.cpu.checker.numCycles                139044613                       # number of cpu cycles simulated
+system.cpu.checker.itb.inst_accesses        115862328                       # ITB inst accesses
+system.cpu.checker.itb.hits                 115857502                       # DTB hits
+system.cpu.checker.itb.misses                    4826                       # DTB misses
+system.cpu.checker.itb.accesses             115862328                       # DTB accesses
+system.cpu.checker.pwrStateResidencyTicks::ON 2827853096000                       # Cumulative time (in ticks) in various power states
+system.cpu.checker.numCycles                139109385                       # number of cpu cycles simulated
 system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
 system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -527,82 +527,83 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks                     72186                       # Table walker walks requested
-system.cpu.dtb.walker.walksShort                72186                       # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walksShortTerminationLevel::Level1        29334                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksShortTerminationLevel::Level2        23181                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore        19671                       # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples        52515                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean   467.713986                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev  2821.743931                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-8191        51203     97.50%     97.50% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::8192-16383          905      1.72%     99.22% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::16384-24575          322      0.61%     99.84% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::24576-32767           40      0.08%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::32768-40959           18      0.03%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::40960-49151           21      0.04%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::49152-57343            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::57344-65535            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.walks                     72426                       # Table walker walks requested
+system.cpu.dtb.walker.walksShort                72426                       # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1        29716                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2        23400                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore        19310                       # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples        53116                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean   407.485503                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev  2469.018740                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-8191        51917     97.74%     97.74% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::8192-16383          937      1.76%     99.51% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::16384-24575          190      0.36%     99.86% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::24576-32767           37      0.07%     99.93% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::32768-40959           15      0.03%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::40960-49151           16      0.03%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::49152-57343            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::57344-65535            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::65536-73727            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::81920-90111            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::90112-98303            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total        52515                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples        17658                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 12583.333333                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 10066.135653                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev  8522.119991                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-32767        17438     98.75%     98.75% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::32768-65535          214      1.21%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-163839            4      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::163840-196607            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-360447            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total        17658                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 131358619316                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean     0.629965                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev     0.490082                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0-1  131298865316     99.95%     99.95% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::2-3      40695500      0.03%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::4-5       8747000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::6-7       6751500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::8-9       1053500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::10-11       584000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::12-13      1412000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::14-15       501000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walkWaitTime::total        53116                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples        17396                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean  9637.387905                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean  7803.906851                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev  6813.601039                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-16383        15561     89.45%     89.45% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::16384-32767         1740     10.00%     99.45% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::32768-49151           86      0.49%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::49152-65535            2      0.01%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-81919            1      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::81920-98303            4      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::147456-163839            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::245760-262143            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total        17396                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 117727604724                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean     0.629848                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev     0.489627                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1  117677681224     99.96%     99.96% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3      34838500      0.03%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5       7318000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7       4585500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9        935500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::10-11       533500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::12-13      1306000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::14-15       397000      0.00%    100.00% # Table walker pending requests distribution
 system.cpu.dtb.walker.walksPending::16-17         9500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 131358619316                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K          6349     82.25%     82.25% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::1M          1370     17.75%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total         7719                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        72186                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walksPending::total 117727604724                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K          6471     81.85%     81.85% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::1M          1435     18.15%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total         7906                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        72426                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total        72186                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7719                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total        72426                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7906                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7719                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total        79905                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7906                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total        80332                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     25413003                       # DTB read hits
-system.cpu.dtb.read_misses                      62542                       # DTB read misses
-system.cpu.dtb.write_hits                    19866296                       # DTB write hits
-system.cpu.dtb.write_misses                      9644                       # DTB write misses
+system.cpu.dtb.read_hits                     25423365                       # DTB read hits
+system.cpu.dtb.read_misses                      62664                       # DTB read misses
+system.cpu.dtb.write_hits                    19868926                       # DTB write hits
+system.cpu.dtb.write_misses                      9762                       # DTB write misses
 system.cpu.dtb.flush_tlb                          128                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                     1834                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     4253                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                       366                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   2075                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries                     4289                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                       358                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                   2236                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                      1321                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 25475545                       # DTB read accesses
-system.cpu.dtb.write_accesses                19875940                       # DTB write accesses
+system.cpu.dtb.perms_faults                      1258                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 25486029                       # DTB read accesses
+system.cpu.dtb.write_accesses                19878688                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          45279299                       # DTB hits
-system.cpu.dtb.misses                           72186                       # DTB misses
-system.cpu.dtb.accesses                      45351485                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.hits                          45292291                       # DTB hits
+system.cpu.dtb.misses                           72426                       # DTB misses
+system.cpu.dtb.accesses                      45364717                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -632,59 +633,58 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks                     12817                       # Table walker walks requested
-system.cpu.itb.walker.walksShort                12817                       # Table walker walks initiated with short descriptors
-system.cpu.itb.walker.walksShortTerminationLevel::Level1         3407                       # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksShortTerminationLevel::Level2         7692                       # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksSquashedBefore         1718                       # Table walks squashed before starting
-system.cpu.itb.walker.walkWaitTime::samples        11099                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::mean   742.229030                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::stdev  3116.397220                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0-4095        10521     94.79%     94.79% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::4096-8191          119      1.07%     95.86% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::8192-12287          227      2.05%     97.91% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::12288-16383          123      1.11%     99.02% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::16384-20479           47      0.42%     99.44% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::20480-24575           47      0.42%     99.86% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::24576-28671            3      0.03%     99.89% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::28672-32767            6      0.05%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::32768-36863            1      0.01%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::36864-40959            2      0.02%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::40960-45055            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::53248-57343            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::57344-61439            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total        11099                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples         5040                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 12026.488095                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean  9684.197840                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev  7608.176186                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-16383         4071     80.77%     80.77% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::16384-32767          955     18.95%     99.72% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::32768-49151           11      0.22%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::49152-65535            1      0.02%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-147455            2      0.04%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total         5040                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples  23984374916                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::mean     0.642154                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::stdev     0.479545                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0      8584682500     35.79%     35.79% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::1     15397812416     64.20%     99.99% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::2         1792000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::3           88000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total  23984374916                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K          2987     89.92%     89.92% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::1M           335     10.08%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total         3322                       # Table walker page sizes translated
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.walks                     12855                       # Table walker walks requested
+system.cpu.itb.walker.walksShort                12855                       # Table walker walks initiated with short descriptors
+system.cpu.itb.walker.walksShortTerminationLevel::Level1         3590                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksShortTerminationLevel::Level2         7693                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksSquashedBefore         1572                       # Table walks squashed before starting
+system.cpu.itb.walker.walkWaitTime::samples        11283                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean   605.778605                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev  2805.757421                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-8191        10907     96.67%     96.67% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::8192-16383          327      2.90%     99.57% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::16384-24575           40      0.35%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::24576-32767            5      0.04%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::40960-49151            1      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::57344-65535            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::65536-73727            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::81920-90111            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total        11283                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples         4887                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean  8961.019030                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean  7007.167188                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev  7172.888707                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-8191         3327     68.08%     68.08% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::8192-16383          829     16.96%     85.04% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::16384-24575          682     13.96%     99.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::24576-32767           38      0.78%     99.77% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::32768-40959            1      0.02%     99.80% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::40960-49151            7      0.14%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::49152-57343            1      0.02%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::81920-90111            2      0.04%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total         4887                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples  23237381212                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean     0.774797                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev     0.417824                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0      5234024500     22.52%     22.52% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1     18002578212     77.47%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::2          696500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::3           46500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::4           35500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total  23237381212                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K          2980     89.89%     89.89% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::1M           335     10.11%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total         3315                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst        12817                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total        12817                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst        12855                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total        12855                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3322                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total         3322                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total        16139                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                     65982481                       # ITB inst hits
-system.cpu.itb.inst_misses                      12817                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3315                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total         3315                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total        16170                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                     66060204                       # ITB inst hits
+system.cpu.itb.inst_misses                      12855                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -693,112 +693,113 @@ system.cpu.itb.flush_tlb                          128                       # Nu
 system.cpu.itb.flush_tlb_mva                     1834                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     3021                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     3013                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                      2147                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                      2175                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 65995298                       # ITB inst accesses
-system.cpu.itb.hits                          65982481                       # DTB hits
-system.cpu.itb.misses                           12817                       # DTB misses
-system.cpu.itb.accesses                      65995298                       # DTB accesses
-system.cpu.numPwrStateTransitions                6074                       # Number of power state transitions
-system.cpu.pwrStateClkGateDist::samples          3037                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::mean     886948130.312150                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::stdev    17421700028.084686                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::underflows         2966     97.66%     97.66% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1000-5e+10           65      2.14%     99.80% # Distribution of time spent in the clock gated state
+system.cpu.itb.inst_accesses                 66073059                       # ITB inst accesses
+system.cpu.itb.hits                          66060204                       # DTB hits
+system.cpu.itb.misses                           12855                       # DTB misses
+system.cpu.itb.accesses                      66073059                       # DTB accesses
+system.cpu.numPwrStateTransitions                6076                       # Number of power state transitions
+system.cpu.pwrStateClkGateDist::samples          3038                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean     887319797.866359                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev    17420812025.908409                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::underflows         2966     97.63%     97.63% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1000-5e+10           66      2.17%     99.80% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::1.5e+11-2e+11            1      0.03%     99.84% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::2e+11-2.5e+11            2      0.07%     99.90% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::2e+11-2.5e+11            1      0.03%     99.87% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::2.5e+11-3e+11            1      0.03%     99.90% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::4.5e+11-5e+11            3      0.10%    100.00% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::max_value 499972891000                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::total            3037                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateResidencyTicks::ON    139232654742                       # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::CLK_GATED 2693661471758                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                        278465363                       # number of cpu cycles simulated
+system.cpu.pwrStateClkGateDist::max_value 499973328096                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::total            3038                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateResidencyTicks::ON    132175550082                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 2695677545918                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                        264351157                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          104979858                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      184015649                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    46812529                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           33022631                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     161497089                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 6057652                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     189263                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                 8972                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        337056                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       558097                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          172                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  65981271                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               1027864                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    6246                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          270599333                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.829251                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.216918                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          105007140                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      184198118                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    46859222                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           33067367                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     149125653                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 6062128                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     177509                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                 8064                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        342285                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       500656                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          149                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  66059105                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1061874                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    6140                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          258192520                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.869926                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.232240                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                171686790     63.45%     63.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 29154260     10.77%     74.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 14034299      5.19%     79.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 55723984     20.59%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                159207105     61.66%     61.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 29153243     11.29%     72.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 14041371      5.44%     78.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 55790801     21.61%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            270599333                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.168109                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.660821                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 77964907                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             121895477                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  64303176                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               3866825                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                2568948                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3406986                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                467982                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              156982730                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               3511045                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                2568948                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 83721940                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                11815597                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       76560081                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  62413108                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              33519659                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              146432544                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts                918349                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents                465966                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  65322                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                  18586                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               30762818                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           150226924                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             676971311                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        163962292                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             10893                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             141750491                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  8476427                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            2839737                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        2644396                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13885386                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             26339908                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            21214343                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1703941                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2126584                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  143224778                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2118002                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 143047064                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            260478                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         8148926                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     14278560                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         121950                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     270599333                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.528631                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.865147                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            258192520                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.177261                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.696793                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 78121728                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             109293057                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  64347286                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               3858820                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                2571629                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3404933                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                467397                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              157054266                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               3508469                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                2571629                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 83876272                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                10707182                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       75777880                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  62454434                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              22805123                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              146493829                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts                914752                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents                447933                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  65579                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                  19295                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               20059867                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           150297562                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             677265731                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        164029738                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             11047                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             141819290                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                  8478266                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            2841903                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        2646616                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13881588                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             26350743                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            21216202                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1694356                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2155521                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  143287156                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2116266                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 143106706                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            261772                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         8147939                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     14286308                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         122067                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     258192520                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.554264                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.878016                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           182394036     67.40%     67.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            45259787     16.73%     84.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            31866202     11.78%     95.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            10262392      3.79%     99.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4              816883      0.30%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           169987358     65.84%     65.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            45210540     17.51%     83.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            31907168     12.36%     95.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            10268019      3.98%     99.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4              819402      0.32%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::5                  33      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
@@ -806,44 +807,44 @@ system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Nu
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       270599333                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       258192520                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 7342152     32.76%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     32      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                5622313     25.09%     57.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               9444091     42.14%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 7338606     32.76%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     32      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                5623411     25.10%     57.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               9440852     42.14%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              2337      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              95850690     67.01%     67.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               114288      0.08%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              95896760     67.01%     67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               115009      0.08%     67.09% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.09% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.09% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.09% # Type of FU issued
@@ -867,99 +868,99 @@ system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.09% # Ty
 system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.09% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.09% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc           8577      0.01%     67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             26130891     18.27%     85.36% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            20940281     14.64%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc           8592      0.01%     67.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.10% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             26141404     18.27%     85.37% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            20942604     14.63%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              143047064                       # Type of FU issued
-system.cpu.iq.rate                           0.513698                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    22408588                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.156652                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          579326888                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         153497201                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    139997351                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               35639                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              13116                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses        11369                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              165429916                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                   23399                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           323958                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              143106706                       # Type of FU issued
+system.cpu.iq.rate                           0.541351                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    22402901                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.156547                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          567034934                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         153556562                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    140052264                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               35671                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              13288                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses        11499                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              165483986                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                   23284                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           324130                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      1433781                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses          712                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        18665                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       622043                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1434023                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses          698                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        18538                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       619510                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        88844                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          6344                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        88631                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          6598                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                2568948                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 1241907                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                544667                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           145523405                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                2571629                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  994929                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                316385                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           145584227                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              26339908                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             21214343                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1094304                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  17849                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                508298                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          18665                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         277238                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       471000                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               748238                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             142148555                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              25736254                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            826428                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts              26350743                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             21216202                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1093451                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  17658                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                280514                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          18538                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         277676                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       470698                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               748374                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             142207045                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              25746206                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            827350                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        180625                       # number of nop insts executed
-system.cpu.iew.exec_refs                     46564673                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 26492434                       # Number of branches executed
-system.cpu.iew.exec_stores                   20828419                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.510471                       # Inst execution rate
-system.cpu.iew.wb_sent                      141779361                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     140008720                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  63240555                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  95712709                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       0.502787                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.660733                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts         7366290                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1996052                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            715102                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    267708008                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.513054                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.118068                       # Number of insts commited each cycle
+system.cpu.iew.exec_nop                        180805                       # number of nop insts executed
+system.cpu.iew.exec_refs                     46576895                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 26509940                       # Number of branches executed
+system.cpu.iew.exec_stores                   20830689                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.537948                       # Inst execution rate
+system.cpu.iew.wb_sent                      141837731                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     140063763                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  63261975                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  95760288                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       0.529840                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.660628                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts         7362260                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1994199                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            714821                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    255299551                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.538232                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.139550                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    194252968     72.56%     72.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     43305040     16.18%     88.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     15457612      5.77%     94.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      4371808      1.63%     96.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      6428406      2.40%     98.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1610065      0.60%     99.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       797962      0.30%     99.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       411830      0.15%     99.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      1072317      0.40%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    181839086     71.23%     71.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     43295063     16.96%     88.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     15470047      6.06%     94.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      4367483      1.71%     95.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      6400805      2.51%     98.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1643674      0.64%     99.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       799411      0.31%     99.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       417134      0.16%     99.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      1066848      0.42%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    267708008                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            113266238                       # Number of instructions committed
-system.cpu.commit.committedOps              137348755                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    255299551                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            113310545                       # Number of instructions committed
+system.cpu.commit.committedOps              137410384                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       45498427                       # Number of memory references committed
-system.cpu.commit.loads                      24906127                       # Number of loads committed
-system.cpu.commit.membars                      814995                       # Number of memory barriers committed
-system.cpu.commit.branches                   26026646                       # Number of branches committed
-system.cpu.commit.fp_insts                      11364                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 120175202                       # Number of committed integer instructions.
-system.cpu.commit.function_calls              4885014                       # Number of function calls committed.
+system.cpu.commit.refs                       45513412                       # Number of memory references committed
+system.cpu.commit.loads                      24916720                       # Number of loads committed
+system.cpu.commit.membars                      814165                       # Number of memory barriers committed
+system.cpu.commit.branches                   26044798                       # Number of branches committed
+system.cpu.commit.fp_insts                      11492                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                 120233477                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              4891928                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu         91728959     66.79%     66.79% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult          112792      0.08%     66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         91774855     66.79%     66.79% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult          113526      0.08%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::IntDiv                0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp              0      0.00%     66.87% # Class of committed instruction
@@ -983,693 +984,689 @@ system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     66.87% #
 system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc         8577      0.01%     66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead        24906127     18.13%     85.01% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite       20592300     14.99%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc         8591      0.01%     66.88% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     66.88% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.88% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.88% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        24916720     18.13%     85.01% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite       20596692     14.99%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         137348755                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               1072317                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    389160423                       # The number of ROB reads
-system.cpu.rob.rob_writes                   292308325                       # The number of ROB writes
-system.cpu.timesIdled                          890756                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         7866030                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   5387322891                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   113111333                       # Number of Instructions Simulated
-system.cpu.committedOps                     137193850                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               2.461870                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.461870                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.406195                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.406195                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                155535200                       # number of integer regfile reads
-system.cpu.int_regfile_writes                88495254                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      9528                       # number of floating regfile reads
+system.cpu.commit.op_class_0::total         137410384                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               1066848                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    376774257                       # The number of ROB reads
+system.cpu.rob.rob_writes                   292425270                       # The number of ROB writes
+system.cpu.timesIdled                          893722                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         6158637                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   5391355036                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   113155640                       # Number of Instructions Simulated
+system.cpu.committedOps                     137255479                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               2.336173                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.336173                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.428050                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.428050                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                155596461                       # number of integer regfile reads
+system.cpu.int_regfile_writes                88540194                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      9674                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                     2716                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 502191760                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 53133619                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               461629806                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                1521804                       # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements            838109                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.925913                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            40060330                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            838621                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             47.769290                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         441954500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.925913                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999855                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999855                       # Average percentage of cache occupancy
+system.cpu.cc_regfile_reads                 502394912                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 53149715                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               449419252                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                1520020                       # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements            839084                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.954165                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            40069527                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            839596                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             47.724771                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         270911500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.954165                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999910                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999910                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          130                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          358                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           24                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          124                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          362                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         179138470                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        179138470                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data     23266826                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        23266826                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     15542812                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       15542812                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       345885                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        345885                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       441505                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       441505                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       460387                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       460387                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      38809638                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         38809638                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     39155523                       # number of overall hits
-system.cpu.dcache.overall_hits::total        39155523                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       704207                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        704207                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      3608607                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      3608607                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       177503                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       177503                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        27219                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        27219                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses         179200286                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        179200286                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data     23273566                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23273566                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     15547100                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       15547100                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       345314                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        345314                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       441102                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       441102                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       459566                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       459566                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      38820666                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         38820666                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     39165980                       # number of overall hits
+system.cpu.dcache.overall_hits::total        39165980                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       709196                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        709196                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      3610101                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      3610101                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       177382                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       177382                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        26835                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        26835                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            5                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            5                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      4312814                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        4312814                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      4490317                       # number of overall misses
-system.cpu.dcache.overall_misses::total       4490317                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  11705123500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  11705123500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 232670418192                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 232670418192                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    376308000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    376308000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       275000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       275000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 244375541692                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 244375541692                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 244375541692                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 244375541692                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     23971033                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     23971033                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     19151419                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     19151419                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       523388                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       523388                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       468724                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       468724                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       460392                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       460392                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     43122452                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     43122452                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     43645840                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     43645840                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.029377                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.029377                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.188425                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.188425                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.339142                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.339142                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.058070                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.058070                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_misses::cpu.data      4319297                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        4319297                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      4496679                       # number of overall misses
+system.cpu.dcache.overall_misses::total       4496679                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  10317292500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  10317292500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 150336233192                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 150336233192                       # number of WriteReq miss cycles
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+system.cpu.dcache.LoadLockedReq_miss_latency::total    369753500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       213000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       213000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 160653525692                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 160653525692                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 160653525692                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 160653525692                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     23982762                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     23982762                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     19157201                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     19157201                       # number of WriteReq accesses(hits+misses)
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+system.cpu.dcache.SoftPFReq_accesses::total       522696                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       467937                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       467937                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       459571                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       459571                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     43139963                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     43139963                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     43662659                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     43662659                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.029571                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.029571                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.188446                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.188446                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.339360                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.339360                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.057347                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.057347                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000011                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000011                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.100013                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.100013                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.102881                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.102881                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16621.708532                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16621.708532                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64476.519109                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 64476.519109                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13825.195635                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13825.195635                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        55000                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total        55000                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 56662.666577                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 56662.666577                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 54422.781664                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 54422.781664                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       867732                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.100123                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.100123                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.102987                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.102987                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14547.871815                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14547.871815                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41643.220838                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 41643.220838                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13778.777716                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13778.777716                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        42600                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total        42600                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 37194.368827                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 37194.368827                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 35727.150124                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 35727.150124                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       590933                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              6871                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              7520                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs   126.289041                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    78.581516                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks       696134                       # number of writebacks
-system.cpu.dcache.writebacks::total            696134                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       290642                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       290642                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3308599                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      3308599                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        18782                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        18782                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      3599241                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      3599241                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      3599241                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      3599241                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       413565                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       413565                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       300008                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       300008                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       119442                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       119442                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8437                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total         8437                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       696178                       # number of writebacks
+system.cpu.dcache.writebacks::total            696178                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       295013                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       295013                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3309632                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      3309632                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        18459                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        18459                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      3604645                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      3604645                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      3604645                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      3604645                       # number of overall MSHR hits
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+system.cpu.dcache.WriteReq_mshr_misses::total       300469                       # number of WriteReq MSHR misses
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+system.cpu.dcache.SoftPFReq_mshr_misses::total       119358                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8376                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total         8376                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            5                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            5                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       713573                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       713573                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       833015                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       833015                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31129                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.ReadReq_mshr_uncacheable::total        31129                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27585                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total        27585                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58714                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total        58714                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6383877500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   6383877500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19987260971                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  19987260971                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1693165000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1693165000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    126972500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    126972500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       270000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       270000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26371138471                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  26371138471                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28064303471                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  28064303471                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6276254500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6276254500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6276254500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   6276254500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017253                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017253                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015665                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015665                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.228209                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.228209                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.018000                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.018000                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data       714652                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       714652                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       834010                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       834010                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31127                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.ReadReq_mshr_uncacheable::total        31127                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27584                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58711                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total        58711                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5890415000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   5890415000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  13426039479                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  13426039479                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1622684000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1622684000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    130358500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    130358500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       208000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       208000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  19316454479                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  19316454479                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  20939138479                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  20939138479                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6279502000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6279502000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6279502000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   6279502000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017270                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017270                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015684                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015684                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.228351                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.228351                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017900                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017900                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000011                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000011                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016548                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.016548                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019086                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.019086                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15436.213171                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15436.213171                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66622.426639                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66622.426639                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14175.624990                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14175.624990                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15049.484414                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15049.484414                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        54000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        54000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36956.469024                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 36956.469024                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33690.033758                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 33690.033758                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201620.819814                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201620.819814                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106895.365671                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106895.365671                       # average overall mshr uncacheable latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements           1886431                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.154202                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            64000082                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1886943                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             33.917337                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       16319051500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.154202                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.998348                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.998348                       # Average percentage of cache occupancy
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016566                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.016566                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019101                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.019101                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14221.769121                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14221.769121                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44683.609554                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44683.609554                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13595.100454                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13595.100454                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15563.335721                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15563.335721                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        41600                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        41600                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27029.175709                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 27029.175709                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25106.579632                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 25106.579632                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201738.105182                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201738.105182                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106956.141098                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106956.141098                       # average overall mshr uncacheable latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements           1887810                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.341026                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            64075895                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1888322                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             33.932716                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       13715039500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.341026                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.998713                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.998713                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          127                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          171                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          211                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          125                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          164                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          221                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          67865267                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         67865267                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst     64000082                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        64000082                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      64000082                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         64000082                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     64000082                       # number of overall hits
-system.cpu.icache.overall_hits::total        64000082                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1978185                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1978185                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1978185                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1978185                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1978185                       # number of overall misses
-system.cpu.icache.overall_misses::total       1978185                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  28158737492                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  28158737492                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  28158737492                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  28158737492                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  28158737492                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  28158737492                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     65978267                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     65978267                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     65978267                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     65978267                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     65978267                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     65978267                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.029982                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.029982                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.029982                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.029982                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.029982                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.029982                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14234.633006                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14234.633006                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14234.633006                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14234.633006                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14234.633006                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14234.633006                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         5390                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          67944454                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         67944454                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst     64075895                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        64075895                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      64075895                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         64075895                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     64075895                       # number of overall hits
+system.cpu.icache.overall_hits::total        64075895                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1980206                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1980206                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1980206                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1980206                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1980206                       # number of overall misses
+system.cpu.icache.overall_misses::total       1980206                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  26984355494                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  26984355494                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  26984355494                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  26984355494                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  26984355494                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  26984355494                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     66056101                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     66056101                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     66056101                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     66056101                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     66056101                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     66056101                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.029978                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.029978                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.029978                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.029978                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.029978                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.029978                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13627.044607                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13627.044607                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13627.044607                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13627.044607                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13627.044607                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13627.044607                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         2643                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               176                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               125                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    30.625000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    21.144000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks      1886431                       # number of writebacks
-system.cpu.icache.writebacks::total           1886431                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        91184                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        91184                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        91184                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        91184                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        91184                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        91184                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1887001                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1887001                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1887001                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1887001                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1887001                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1887001                       # number of overall MSHR misses
+system.cpu.icache.writebacks::writebacks      1887810                       # number of writebacks
+system.cpu.icache.writebacks::total           1887810                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        91852                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        91852                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        91852                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        91852                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        91852                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        91852                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1888354                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1888354                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1888354                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1888354                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1888354                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1888354                       # number of overall MSHR misses
 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         3003                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.ReadReq_mshr_uncacheable::total         3003                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3003                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses::total         3003                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  25189687497                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  25189687497                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  25189687497                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  25189687497                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  25189687497                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  25189687497                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    377605500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    377605500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    377605500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total    377605500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.028600                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.028600                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.028600                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.028600                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.028600                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.028600                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13349.058902                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13349.058902                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13349.058902                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13349.058902                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13349.058902                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13349.058902                       # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 125742.757243                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 125742.757243                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 125742.757243                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 125742.757243                       # average overall mshr uncacheable latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements            97066                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65034.676246                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            5004762                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           162374                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            30.822435                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 49586.658386                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    11.610418                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     2.677884                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 10386.588269                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  5047.141288                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.756632                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000177                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000041                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.158487                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.077013                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.992350                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023           15                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65293                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4           15                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          144                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2842                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6720                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55568                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000229                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.996292                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         44286849                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        44286849                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        57782                       # number of ReadReq hits
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-system.cpu.l2cache.ReadReq_hits::total          69841                       # number of ReadReq hits
-system.cpu.l2cache.WritebackDirty_hits::writebacks       696134                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       696134                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks      1848502                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total      1848502                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           60                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           60                       # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            2                       # number of SCUpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::total            2                       # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       161598                       # number of ReadExReq hits
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-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1866971                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total      1866971                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       527952                       # number of ReadSharedReq hits
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-system.cpu.l2cache.demand_hits::cpu.dtb.walker        57782                       # number of demand (read+write) hits
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-system.cpu.l2cache.overall_hits::cpu.dtb.walker        57782                       # number of overall hits
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-system.cpu.l2cache.overall_hits::cpu.inst      1866971                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       689550                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2626362                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           21                       # number of ReadReq misses
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-system.cpu.l2cache.ReadReq_misses::total           28                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         2746                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         2746                       # number of UpgradeReq misses
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-system.cpu.l2cache.SCUpgradeReq_misses::total            3                       # number of SCUpgradeReq misses
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-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        19929                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        19929                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data        13357                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total        13357                       # number of ReadSharedReq misses
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-system.cpu.l2cache.demand_misses::cpu.inst        19929                       # number of demand (read+write) misses
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-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      2978500                       # number of ReadReq miss cycles
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-system.cpu.l2cache.ReadReq_miss_latency::total      3907500                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      2730500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total      2730500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       162000                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::total       162000                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  17623320500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  17623320500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2639049500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total   2639049500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1797637500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   1797637500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      2978500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       929000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   2639049500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  19420958000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  22063915000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      2978500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       929000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   2639049500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  19420958000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  22063915000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        57803                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        12066                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total        69869                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       696134                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       696134                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks      1848502                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total      1848502                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2806                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         2806                       # number of UpgradeReq accesses(hits+misses)
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+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    229048500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total    229048500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.028587                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.028587                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.028587                       # mshr miss rate for demand accesses
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+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.028587                       # mshr miss rate for overall accesses
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12829.446437                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12829.446437                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12829.446437                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12829.446437                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12829.446437                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12829.446437                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 76273.226773                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 76273.226773                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 76273.226773                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 76273.226773                       # average overall mshr uncacheable latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.replacements           103423                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65159.012032                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            5300281                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           168782                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            31.403118                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      93779484000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     9.961762                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     3.729813                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 10177.791609                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 54967.528848                       # Average occupied blocks per requestor
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+system.cpu.l2cache.tags.age_task_id_blocks_1023::4           14                       # Occupied blocks per task id
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+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5571                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        59599                       # Occupied blocks per task id
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+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997086                       # Percentage of cache occupancy per task id
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+system.cpu.l2cache.tags.data_accesses        43992446                       # Number of data accesses
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+system.cpu.l2cache.WritebackDirty_hits::writebacks       696178                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total       696178                       # number of WritebackDirty hits
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 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            5                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::total            5                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       297337                       # number of ReadExReq accesses(hits+misses)
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-system.cpu.l2cache.ReadCleanReq_accesses::total      1886900                       # number of ReadCleanReq accesses(hits+misses)
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-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000363                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000580                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.000401                       # miss rate for ReadReq accesses
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-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.978617                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.600000                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.600000                       # miss rate for SCUpgradeReq accesses
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-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.010562                       # miss rate for ReadCleanReq accesses
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-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132422.575142                       # average ReadCleanReq miss latency
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-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134583.926031                       # average ReadSharedReq miss latency
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 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks        89296                       # number of writebacks
-system.cpu.l2cache.writebacks::total            89296                       # number of writebacks
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           26                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total           26                       # number of ReadCleanReq MSHR hits
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 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          112                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::total          112                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           26                       # number of demand (read+write) MSHR hits
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 system.cpu.l2cache.demand_mshr_hits::cpu.data          112                       # number of demand (read+write) MSHR hits
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 system.cpu.l2cache.overall_mshr_hits::cpu.data          112                       # number of overall MSHR hits
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-system.cpu.l2cache.UpgradeReq_mshr_misses::total         2746                       # number of UpgradeReq MSHR misses
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-system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
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+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           11                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total           11                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       139010                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       139010                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        19914                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        19914                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        14324                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        14324                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           16                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            6                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        19914                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       153334                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       173270                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           16                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            6                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        19914                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       153334                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       173270                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         3003                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31129                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total        34132                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        27585                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total        27585                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31127                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::total        34130                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        27584                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         3003                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58714                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total        61717                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      2768500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       859000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total      3627500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    186762000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    186762000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       210500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       210500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  16265930500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  16265930500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2437107003                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2437107003                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1651792000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1651792000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      2768500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       859000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2437107003                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  17917722500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  20358457003                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      2768500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       859000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2437107003                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  17917722500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  20358457003                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    340067500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5887129500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6227197000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    340067500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5887129500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   6227197000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000363                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000580                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000401                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.978617                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.978617                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.600000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.600000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.456516                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.456516                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.010548                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.010548                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.024468                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.024468                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000363                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000580                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010548                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.177648                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.060426                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000363                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000580                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010548                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.177648                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.060426                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 131833.333333                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122714.285714                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 129553.571429                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68012.381646                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68012.381646                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70166.666667                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70166.666667                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119832.402626                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119832.402626                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122449.228910                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122449.228910                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124710.607777                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124710.607777                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 131833.333333                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122714.285714                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122449.228910                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120266.085620                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120524.861635                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 131833.333333                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122714.285714                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122449.228910                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120266.085620                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120524.861635                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113242.590743                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189120.418260                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182444.538849                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113242.590743                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100267.900330                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 100899.217396                       # average overall mshr uncacheable latency
-system.cpu.toL2Bus.snoop_filter.tot_requests      5483160                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2757544                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        45002                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops          381                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops          381                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58711                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total        61714                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      1337500                       # number of ReadReq MSHR miss cycles
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::total      1779500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       210500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       210500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       147000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       147000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   9885640500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   9885640500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1458480000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1458480000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1091561500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1091561500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      1337500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       442000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1458480000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  10977202000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  12437461500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      1337500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       442000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1458480000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  10977202000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  12437461500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    191510500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5890404500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6081915000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    191510500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5890404500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   6081915000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000294                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000587                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000341                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.003974                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.003974                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.400000                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.400000                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.466737                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.466737                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.010546                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.010546                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.026439                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.026439                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000294                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000587                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010546                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.182624                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.062049                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000294                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000587                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010546                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.182624                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.062049                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 83593.750000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 73666.666667                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 80886.363636                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19136.363636                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19136.363636                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        73500                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        73500                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71114.599669                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71114.599669                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73238.927388                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73238.927388                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76205.075398                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76205.075398                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 83593.750000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 73666.666667                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73238.927388                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71590.136565                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71780.813182                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 83593.750000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 73666.666667                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73238.927388                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71590.136565                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71780.813182                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63773.060273                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189237.783917                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 178198.505713                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63773.060273                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100328.805505                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 98550.004861                       # average overall mshr uncacheable latency
+system.cpu.toL2Bus.snoop_filter.tot_requests      5488560                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2760615                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        44763                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops          238                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops          238                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadReq         128619                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2557060                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         27585                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        27585                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       821637                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean      1886431                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       149968                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2806                       # Transaction distribution
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadReq         129622                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2559974                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         27584                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        27584                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       791350                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      1887810                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       151157                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2768                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            5                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2811                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       297337                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       297337                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      1887001                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       541532                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5666337                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2638583                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        30857                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       133499                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8469276                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    241541168                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98417449                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        48264                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       231212                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          340238093                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      194794                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic               8145576                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples      3054607                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.024758                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.155386                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2773                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       297834                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       297834                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1888354                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       542004                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq         4368                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5670459                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2641503                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        29194                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       130873                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8472029                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    241718384                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98487773                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        40872                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       217428                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          340464457                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      139207                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic               6232532                       # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples      2995964                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.025358                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.157210                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            2978982     97.52%     97.52% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              75625      2.48%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2919992     97.46%     97.46% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              75972      2.54%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3054607                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     5400960498                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        2995964                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     5405204997                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       258877                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       383377                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    2834452098                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    2836467127                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1304519551                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1305988986                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      18799483                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      18982487                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      75755880                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      76565899                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq                30172                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               30172                       # Transaction distribution
+system.iobus.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.iobus.trans_dist::ReadReq                30182                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               30182                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
@@ -1692,9 +1689,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72894                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total        72894                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  178372                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72914                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total        72914                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  178392                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
@@ -1715,22 +1712,22 @@ system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321016                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      2321016                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2480141                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             43088500                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321096                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      2321096                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2480221                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             43094500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               100500                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               101000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               326000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               325500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                28000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                28500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy                14500                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy                92500                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy                91500                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer8.occupancy               651500                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy               649500                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy               20500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
@@ -1752,56 +1749,56 @@ system.iobus.reqLayer20.occupancy                9000                       # La
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer21.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6158500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6172500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            33063500                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            33854000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           187149991                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           187760330                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36718000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36738000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements                36413                       # number of replacements
-system.iocache.tags.tagsinuse                1.005857                       # Cycle average of tags in use
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.replacements                36423                       # number of replacements
+system.iocache.tags.tagsinuse                1.000676                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                36429                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                36439                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         256506730000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.005857                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.062866                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.062866                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         252706881000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.000676                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.062542                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.062542                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               328023                       # Number of tag accesses
-system.iocache.tags.data_accesses              328023                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.iocache.ReadReq_misses::realview.ide          223                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              223                       # number of ReadReq misses
+system.iocache.tags.tag_accesses               328113                       # Number of tag accesses
+system.iocache.tags.data_accesses              328113                       # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.iocache.ReadReq_misses::realview.ide          233                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              233                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide        36447                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             36447                       # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide        36447                       # number of overall misses
-system.iocache.overall_misses::total            36447                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     28156877                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     28156877                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4551348114                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4551348114                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide   4579504991                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   4579504991                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide   4579504991                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   4579504991                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ide          223                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            223                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::realview.ide        36457                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             36457                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide        36457                       # number of overall misses
+system.iocache.overall_misses::total            36457                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide     28964877                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     28964877                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4277512453                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4277512453                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide   4306477330                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   4306477330                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide   4306477330                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   4306477330                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ide          233                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            233                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide        36447                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           36447                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide        36447                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          36447                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::realview.ide        36457                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           36457                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide        36457                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          36457                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
@@ -1810,14 +1807,14 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 126264.022422                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 126264.022422                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125644.548200                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 125644.548200                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 125648.338437                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 125648.338437                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 125648.338437                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 125648.338437                       # average overall miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 124312.776824                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 124312.776824                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118085.039007                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118085.039007                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 118124.841046                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 118124.841046                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 118124.841046                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 118124.841046                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
@@ -1826,22 +1823,22 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.writebacks::writebacks           36190                       # number of writebacks
 system.iocache.writebacks::total                36190                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ide          223                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          223                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide          233                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          233                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide        36447                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        36447                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide        36447                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        36447                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     17006877                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     17006877                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2738747578                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2738747578                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   2755754455                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   2755754455                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   2755754455                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   2755754455                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::realview.ide        36457                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        36457                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide        36457                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        36457                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     17314877                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     17314877                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2464212681                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2464212681                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   2481527558                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   2481527558                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   2481527558                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   2481527558                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1850,84 +1847,90 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76264.022422                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 76264.022422                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75605.884993                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75605.884993                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 75609.911790                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 75609.911790                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 75609.911790                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 75609.911790                       # average overall mshr miss latency
-system.membus.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq               34132                       # Transaction distribution
-system.membus.trans_dist::ReadResp              67530                       # Transaction distribution
-system.membus.trans_dist::WriteReq              27585                       # Transaction distribution
-system.membus.trans_dist::WriteResp             27585                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       125486                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             7993                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4611                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74312.776824                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 74312.776824                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68027.072687                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68027.072687                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 68067.245193                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 68067.245193                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 68067.245193                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 68067.245193                       # average overall mshr miss latency
+system.membus.snoop_filter.tot_requests        349590                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests       144366                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests          482                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
+system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadReq               34130                       # Transaction distribution
+system.membus.trans_dist::ReadResp              68622                       # Transaction distribution
+system.membus.trans_dist::WriteReq              27584                       # Transaction distribution
+system.membus.trans_dist::WriteResp             27584                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       131362                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             8484                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              130                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            133874                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           133874                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         33399                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            138891                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           138891                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         34493                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           14                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2076                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       451368                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       558936                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72875                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        72875                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 631811                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2070                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       465445                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       573007                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72895                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        72895                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 645902                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          112                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4152                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16456092                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16619481                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4140                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17222620                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     17385997                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                18936601                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              487                       # Total snoops (count)
-system.membus.snoopTraffic                      31040                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            403324                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.pkt_size::total                19703117                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              497                       # Total snoops (count)
+system.membus.snoopTraffic                      31680                       # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples            271454                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.017933                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.132708                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  403324    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  266586     98.21%     98.21% # Request fanout histogram
+system.membus.snoop_fanout::1                    4868      1.79%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              403324                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            83656500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              271454                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            84464500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                9000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1736499                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1723499                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           876921354                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           908168519                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          979994750                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1012308500                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy            1182123                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy            1273123                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
 system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
 system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
 system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
 system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -1959,30 +1962,30 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
 system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     3037                       # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce                     3038                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
index d38a658b5..ab0dc0047 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
@@ -1,167 +1,167 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.825947                       # Number of seconds simulated
-sim_ticks                                2825947406000                       # Number of ticks simulated
-final_tick                               2825947406000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.826111                       # Number of seconds simulated
+sim_ticks                                2826111083000                       # Number of ticks simulated
+final_tick                               2826111083000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 132633                       # Simulator instruction rate (inst/s)
-host_op_rate                                   160894                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3120208803                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 618508                       # Number of bytes of host memory used
-host_seconds                                   905.69                       # Real time elapsed on the host
-sim_insts                                   120124543                       # Number of instructions simulated
-sim_ops                                     145720076                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  93135                       # Simulator instruction rate (inst/s)
+host_op_rate                                   112984                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2190118612                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 627176                       # Number of bytes of host memory used
+host_seconds                                  1290.39                       # Real time elapsed on the host
+sim_insts                                   120180681                       # Number of instructions simulated
+sim_ops                                     145794019                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.dtb.walker         1664                       # Number of bytes read from this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu0.dtb.walker         1920                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          192                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          1303616                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          1321960                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher      8513856                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker          384                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           181024                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           635732                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher       529024                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          1301824                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          1315176                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher      8404800                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker          512                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           186528                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           599252                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher       416192                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             12488540                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      1303616                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       181024                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1484640                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8962368                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             12227420                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      1301824                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       186528                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1488352                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8794944                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8979932                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker           26                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           8812508                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker           30                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            3                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             22616                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             21176                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       133029                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker            6                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              2896                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data              9954                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher         8266                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             22588                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             21070                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       131325                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker            8                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              2982                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data              9384                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher         6503                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                197989                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          140037                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                193909                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          137421                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               144428                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker           589                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               141812                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker           679                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            68                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              461302                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              467794                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher      3012744                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           136                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker            45                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               64058                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              224962                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       187202                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              460641                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              465366                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher      2973981                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           181                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               66002                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              212041                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       147267                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              340                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4419240                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         461302                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          64058                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             525360                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3171456                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4326589                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         460641                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          66002                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             526643                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3112031                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data               6201                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3177671                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3171456                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker          589                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                3118245                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3112031                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker          679                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           68                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             461302                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             473995                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher      3012744                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          136                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker           45                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              64058                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             224977                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       187202                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             460641                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             471567                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher      2973981                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          181                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              66002                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             212055                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       147267                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             340                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7596911                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        197990                       # Number of read requests accepted
-system.physmem.writeReqs                       144428                       # Number of write requests accepted
-system.physmem.readBursts                      197990                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     144428                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 12662400                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      8960                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8992448                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  12488604                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8979932                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      140                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total                7444834                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        193910                       # Number of read requests accepted
+system.physmem.writeReqs                       141812                       # Number of write requests accepted
+system.physmem.readBursts                      193910                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     141812                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 12399936                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     10304                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8824960                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  12227484                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8812508                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      161                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    3897                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               12407                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               12295                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               12935                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               12653                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               14543                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               12106                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               12653                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               12509                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               12223                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               12064                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              11718                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              11008                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              11914                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              13060                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              12107                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              11655                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                9105                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                9127                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                9615                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                9150                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                8481                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                8750                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8993                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8806                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8720                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                8569                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               8518                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               8119                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8743                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               9182                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8573                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               8056                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               12140                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               12135                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               12398                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               12886                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               14558                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               12353                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               12494                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               12590                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               12207                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               12490                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              11644                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              10772                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              11273                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              11534                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              11359                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10916                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8885                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                8987                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                9257                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                9509                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                8433                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                8902                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                9078                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8908                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                8674                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                9007                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               8474                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               8031                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               8318                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8000                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7983                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7444                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           6                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2825947136000                       # Total gap between requests
+system.physmem.numWrRetry                           9                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2826110796000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     551                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
 system.physmem.readPktSize::4                    3086                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  194325                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  190245                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 140037                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     60161                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     72217                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     15830                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     12957                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      8715                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      7515                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      6523                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      5382                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      4740                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      1512                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      989                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      744                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      304                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      256                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        5                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 137421                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     59620                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     70390                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     15526                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     12745                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      8439                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      7276                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      6358                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      5209                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      4584                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      1421                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      930                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      679                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      302                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      262                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
@@ -189,165 +189,162 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2737                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3737                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4277                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4910                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5685                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6030                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6974                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7661                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8663                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     8689                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    10204                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    10681                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     9419                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     9434                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    10925                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     9108                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     8385                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7984                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      686                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      515                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      357                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::40                      144                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      165                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      149                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      132                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      171                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      144                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      164                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      129                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      129                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       96                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       98                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       88                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       72                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       59                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       44                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       41                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       27                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       14                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       26                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        92378                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      234.414947                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     132.500025                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     299.048436                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          50794     54.98%     54.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        17715     19.18%     74.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5941      6.43%     80.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3366      3.64%     84.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2816      3.05%     87.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1529      1.66%     88.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          925      1.00%     89.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          990      1.07%     91.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8302      8.99%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          92378                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6992                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        28.296339                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      556.591514                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6990     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     2582                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3484                       # What write queue length does an incoming req see
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+system.physmem.bytesPerActivate::samples        84734                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      250.487785                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     142.325533                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     306.970890                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          42837     50.55%     50.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        17738     20.93%     71.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6168      7.28%     78.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3519      4.15%     82.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2713      3.20%     86.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1549      1.83%     87.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          945      1.12%     89.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1056      1.25%     90.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8209      9.69%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          84734                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6846                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        28.300175                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      562.386287                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6844     99.97%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6992                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6992                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.095395                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.609227                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       12.295574                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5854     83.72%     83.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             392      5.61%     89.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              80      1.14%     90.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              62      0.89%     91.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             277      3.96%     95.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              20      0.29%     95.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              15      0.21%     95.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              24      0.34%     96.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              25      0.36%     96.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              12      0.17%     96.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               9      0.13%     96.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              14      0.20%     97.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             142      2.03%     99.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               4      0.06%     99.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              10      0.14%     99.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               7      0.10%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               6      0.09%     99.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.01%     99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               2      0.03%     99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.01%     99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               3      0.04%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             2      0.03%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             3      0.04%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.01%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.01%     99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            14      0.20%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             2      0.03%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             1      0.01%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             3      0.04%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             2      0.03%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171             1      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183             1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6992                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     6748582846                       # Total ticks spent queuing
-system.physmem.totMemAccLat               10458270346                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    989250000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       34109.59                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            6846                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6846                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.141689                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.636499                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       12.164291                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5708     83.38%     83.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             378      5.52%     88.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              91      1.33%     90.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              47      0.69%     90.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             276      4.03%     94.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              33      0.48%     95.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              21      0.31%     95.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              23      0.34%     96.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              19      0.28%     96.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              10      0.15%     96.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               2      0.03%     96.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               9      0.13%     96.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             166      2.42%     99.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               9      0.13%     99.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               4      0.06%     99.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              11      0.16%     99.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               6      0.09%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               2      0.03%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               3      0.04%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               2      0.03%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.01%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             3      0.04%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             2      0.03%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             3      0.04%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             7      0.10%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             2      0.03%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             2      0.03%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             2      0.03%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             3      0.04%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6846                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     6600075879                       # Total ticks spent queuing
+system.physmem.totMemAccLat               10232869629                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    968745000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       34065.08                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  52859.59                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           4.48                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.18                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        4.42                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.18                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  52815.08                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           4.39                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.12                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        4.33                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        3.12                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.04                       # Data bus utilization in percentage for reads
+system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.52                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     165284                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     80694                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.54                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  57.42                       # Row buffer hit rate for writes
-system.physmem.avgGap                      8252916.42                       # Average gap between requests
-system.physmem.pageHitRate                      72.69                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  361058040                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  197005875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 796387800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                466734960                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           184576766400                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            79734690540                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1625622381750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1891755025365                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.424618                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2704272847388                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     94364400000                       # Time in different power states
+system.physmem.avgRdQLen                         1.08                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        26.81                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     161373                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     85531                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   83.29                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  62.02                       # Row buffer hit rate for writes
+system.physmem.avgGap                      8418008.94                       # Average gap between requests
+system.physmem.pageHitRate                      74.44                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  338612400                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  184758750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 792121200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                466294320                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           184587446160                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            79311033765                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1626092117250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1891772383845                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.392029                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2705053539598                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     94369860000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     27304587612                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     26681946652                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  337319640                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  184053375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 746834400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                443750400                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           184576766400                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            79554512970                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1625780432250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1891623669435                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.378136                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2704538486760                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     94364400000                       # Time in different power states
+system.physmem_1.actEnergy                  301976640                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  164769000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 719113200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                427232880                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           184587446160                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            78534447525                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1626773333250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1891508318655                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.298592                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2706191706230                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     94369860000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     27044516240                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     25549496770                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
 system.realview.nvmem.bytes_read::cpu0.inst          112                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst          176                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           288                       # Number of bytes read from this memory
@@ -366,30 +363,30 @@ system.realview.nvmem.bw_inst_read::total          102                       # I
 system.realview.nvmem.bw_total::cpu0.inst           40                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu1.inst           62                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total             102                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups               53058502                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         24374377                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           933450                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            32093175                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               13944864                       # Number of BTB hits
+system.cpu0.branchPred.lookups               23913557                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         15655751                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           926443                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            14584665                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits                9536401                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            43.451182                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               15470259                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             33206                       # Number of incorrect RAS predictions.
-system.cpu0.branchPred.indirectLookups       10120086                       # Number of indirect predictor lookups.
-system.cpu0.branchPred.indirectHits           9964746                       # Number of indirect target hits.
-system.cpu0.branchPred.indirectMisses          155340                       # Number of indirect misses.
-system.cpu0.branchPredindirectMispredicted        48572                       # Number of mispredicted indirect branches.
+system.cpu0.branchPred.BTBHitPct            65.386493                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                3854213                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             33180                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.indirectLookups        1360238                       # Number of indirect predictor lookups.
+system.cpu0.branchPred.indirectHits           1204672                       # Number of indirect target hits.
+system.cpu0.branchPred.indirectMisses          155566                       # Number of indirect misses.
+system.cpu0.branchPredindirectMispredicted        48773                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -419,84 +416,84 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dtb.walker.walks                    67164                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort               67164                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        25323                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        19031                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore        22810                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples        44354                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean   458.594490                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev  2953.911408                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-8191        43233     97.47%     97.47% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::8192-16383          862      1.94%     99.42% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::16384-24575          108      0.24%     99.66% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::24576-32767          108      0.24%     99.90% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::32768-40959            9      0.02%     99.92% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::40960-49151           18      0.04%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::57344-65535           14      0.03%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.walker.walks                    65918                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort               65918                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        25327                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        18922                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore        21669                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples        44249                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean   506.926710                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev  3129.335275                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-8191        43005     97.19%     97.19% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::8192-16383          929      2.10%     99.29% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::16384-24575          148      0.33%     99.62% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::24576-32767          108      0.24%     99.87% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::32768-40959           23      0.05%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::40960-49151           20      0.05%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::49152-57343            1      0.00%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::57344-65535           13      0.03%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::65536-73727            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::73728-81919            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total        44354                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples        17047                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 11038.716490                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean  9658.702439                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev  6683.029230                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-16383        15750     92.39%     92.39% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::16384-32767         1185      6.95%     99.34% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-49151           75      0.44%     99.78% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::49152-65535           14      0.08%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::81920-98303            5      0.03%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::98304-114687           14      0.08%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::114688-131071            2      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-147455            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkWaitTime::total        44249                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples        16055                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 11307.848022                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean  9898.999015                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev  6813.334576                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-16383        14595     90.91%     90.91% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::16384-32767         1294      8.06%     98.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-49151          134      0.83%     99.80% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::49152-65535            9      0.06%     99.86% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::81920-98303            4      0.02%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::98304-114687           17      0.11%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::114688-131071            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walkCompletionTime::180224-196607            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total        17047                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples  85757506152                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     0.515718                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev     0.512261                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-1  85699757152     99.93%     99.93% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::2-3     40650000      0.05%     99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-5      7189500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::6-7      4730000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-9      1448500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::10-11      1006500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-13      1064000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::14-15      1646000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-17        14500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total  85757506152                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         5272     77.42%     77.42% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         1538     22.58%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         6810                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        67164                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkCompletionTime::total        16055                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples  85920956152                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.541941                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.508329                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-1  85862493152     99.93%     99.93% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::2-3     40323000      0.05%     99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-5      8212500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::6-7      5190500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-9      2626000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::10-11       844500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-13       886000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::14-15       336500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-17        44000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total  85920956152                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K         5102     78.63%     78.63% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1387     21.37%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         6489                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        65918                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        67164                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6810                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        65918                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6489                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6810                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total        73974                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6489                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        72407                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    23645826                       # DTB read hits
-system.cpu0.dtb.read_misses                     56383                       # DTB read misses
-system.cpu0.dtb.write_hits                   17571331                       # DTB write hits
-system.cpu0.dtb.write_misses                    10781                       # DTB write misses
+system.cpu0.dtb.read_hits                    17729387                       # DTB read hits
+system.cpu0.dtb.read_misses                     55806                       # DTB read misses
+system.cpu0.dtb.write_hits                   14606301                       # DTB write hits
+system.cpu0.dtb.write_misses                    10112                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3487                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      213                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  2243                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                    3431                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      353                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  2188                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      818                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                23702209                       # DTB read accesses
-system.cpu0.dtb.write_accesses               17582112                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      939                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                17785193                       # DTB read accesses
+system.cpu0.dtb.write_accesses               14616413                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         41217157                       # DTB hits
-system.cpu0.dtb.misses                          67164                       # DTB misses
-system.cpu0.dtb.accesses                     41284321                       # DTB accesses
-system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.hits                         32335688                       # DTB hits
+system.cpu0.dtb.misses                          65918                       # DTB misses
+system.cpu0.dtb.accesses                     32401606                       # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -526,59 +523,58 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.cpu0.itb.walker.walks                    10883                       # Table walker walks requested
-system.cpu0.itb.walker.walksShort               10883                       # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walksShortTerminationLevel::Level1         3898                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2         5925                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore         1060                       # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples         9823                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean   449.709865                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev  2327.234590                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-4095         9434     96.04%     96.04% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::4096-8191          184      1.87%     97.91% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::8192-12287          123      1.25%     99.17% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::12288-16383           44      0.45%     99.61% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::16384-20479            7      0.07%     99.68% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::20480-24575           18      0.18%     99.87% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::24576-28671            4      0.04%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::28672-32767            4      0.04%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-36863            3      0.03%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::36864-40959            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::40960-45055            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total         9823                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples         3631                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 11923.299367                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 11119.549027                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev  4771.165368                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-8191          614     16.91%     16.91% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::8192-16383         2801     77.14%     94.05% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-24575          142      3.91%     97.96% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::24576-32767           43      1.18%     99.15% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-40959           27      0.74%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::40960-49151            3      0.08%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.cpu0.itb.walker.walks                    10845                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort               10845                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1         3752                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2         6021                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore         1072                       # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples         9773                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean   438.606364                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev  2276.348067                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-4095         9409     96.28%     96.28% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::4096-8191          161      1.65%     97.92% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::8192-12287          121      1.24%     99.16% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::12288-16383           47      0.48%     99.64% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::16384-20479            7      0.07%     99.71% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::20480-24575           16      0.16%     99.88% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::24576-28671            6      0.06%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-36863            4      0.04%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::36864-40959            2      0.02%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total         9773                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples         3657                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 12272.627837                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 11484.483595                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev  4878.254960                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-8191          514     14.06%     14.06% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::8192-16383         2884     78.86%     92.92% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-24575          170      4.65%     97.57% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::24576-32767           55      1.50%     99.07% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-40959           31      0.85%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::40960-49151            1      0.03%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::49152-57343            1      0.03%     99.97% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::90112-98303            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total         3631                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples  21332036712                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     0.795904                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev     0.403169                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0     4354826000     20.41%     20.41% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1    16976239212     79.58%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2         901500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3          70000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total  21332036712                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K         2243     87.24%     87.24% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M          328     12.76%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total         2571                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkCompletionTime::total         3657                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples  21495635712                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     0.820169                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev     0.384194                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0     3866725500     17.99%     17.99% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1    17627832712     82.01%     99.99% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2        1008500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3          69000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total  21495635712                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K         2254     87.20%     87.20% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          331     12.80%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         2585                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        10883                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        10883                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        10845                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        10845                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2571                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2571                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total        13454                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    72708520                       # ITB inst hits
-system.cpu0.itb.inst_misses                     10883                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2585                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2585                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total        13430                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    37503849                       # ITB inst hits
+system.cpu0.itb.inst_misses                     10845                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
@@ -587,1047 +583,1055 @@ system.cpu0.itb.flush_tlb                          66                       # Nu
 system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2280                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    2291                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     1927                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     1944                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                72719403                       # ITB inst accesses
-system.cpu0.itb.hits                         72708520                       # DTB hits
-system.cpu0.itb.misses                          10883                       # DTB misses
-system.cpu0.itb.accesses                     72719403                       # DTB accesses
-system.cpu0.numPwrStateTransitions               3678                       # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples         1839                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean    1481668762.034258                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev   23877600166.586662                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::underflows         1061     57.69%     57.69% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10          773     42.03%     99.73% # Distribution of time spent in the clock gated state
+system.cpu0.itb.inst_accesses                37514694                       # ITB inst accesses
+system.cpu0.itb.hits                         37503849                       # DTB hits
+system.cpu0.itb.misses                          10845                       # DTB misses
+system.cpu0.itb.accesses                     37514694                       # DTB accesses
+system.cpu0.numPwrStateTransitions               3712                       # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples         1856                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean    1487215700.959052                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev   23895599673.728432                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows         1080     58.19%     58.19% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10          769     41.43%     99.62% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::5e+10-1e+11            2      0.11%     99.73% # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11            1      0.05%     99.78% # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11            4      0.22%    100.00% # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::max_value 499971949600                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total           1839                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON   101158552619                       # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 2724788853381                       # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles                       202318013                       # number of cpu cycles simulated
+system.cpu0.pwrStateClkGateDist::max_value 499971395296                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total           1856                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON    65838742020                       # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 2760272340980                       # Cumulative time (in ticks) in various power states
+system.cpu0.numCycles                       131678547                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          20370009                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     195788924                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                   53058502                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          39379869                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                    174489676                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                5690920                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                    148682                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles               56911                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles       412776                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       413906                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles        90774                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                 72708226                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               258373                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                   5359                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         198828194                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             1.203611                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            1.307839                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          19262499                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     112028029                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                   23913557                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          14595286                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                    106047706                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                2739238                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                    149116                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles               57008                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles       423158                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       407524                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles        94244                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                 37503537                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               259263                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                   5228                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         127810874                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             1.056272                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            1.258048                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                93974548     47.26%     47.26% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                30342793     15.26%     62.53% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                14563641      7.32%     69.85% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                59947212     30.15%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                65678610     51.39%     51.39% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                21331326     16.69%     68.08% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                 8731054      6.83%     74.91% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                32069884     25.09%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           198828194                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.262253                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.967729                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                25600367                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles            106949118                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                 58799478                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles              4963264                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               2515967                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved             3058039                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred               333585                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts             154217934                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts              3811468                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               2515967                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                34209280                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               12450122                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      83570932                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                 55016631                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             11065262                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts             137539344                       # Number of instructions processed by rename
-system.cpu0.rename.SquashedInsts              1033397                       # Number of squashed instructions processed by rename
-system.cpu0.rename.ROBFullEvents              1452682                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents                164882                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                 58749                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents               6858829                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands          141646141                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            634543216                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       152633070                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups             9368                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps            130461493                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                11184637                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts           2697680                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts       2556046                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 22573700                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads            24576087                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           19059052                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1700091                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         2321608                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                 134608055                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            1714170                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                132746710                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued           453040                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined       10578491                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     21717645                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        121089                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    198828194                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.667645                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       0.963186                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           127810874                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.181606                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.850769                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                19867897                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles             60850603                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                 41086114                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles              4967748                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               1038512                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved             3035925                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred               335186                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts             110135169                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts              3776324                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               1038512                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                25520251                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               12577304                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      37369361                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                 40264186                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles             11041260                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts             105172145                       # Number of instructions processed by rename
+system.cpu0.rename.SquashedInsts              1006076                       # Number of squashed instructions processed by rename
+system.cpu0.rename.ROBFullEvents              1476626                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents                165177                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                 58768                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents               6832387                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands          109365921                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            480109573                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups       120259513                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups             9447                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             98266494                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                11099416                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts           1228555                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts       1085594                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 12372656                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads            18663457                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           16076197                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1697816                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         2228906                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                 102290291                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1693186                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                100457201                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued           451571                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined        9045594                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     21384310                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        120136                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    127810874                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.785983                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.028831                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0          122140771     61.43%     61.43% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1           33611714     16.90%     78.34% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2           31218891     15.70%     94.04% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3           10730115      5.40%     99.43% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            1126646      0.57%    100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5                 57      0.00%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0           71664386     56.07%     56.07% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1           23315575     18.24%     74.31% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2           22454220     17.57%     91.88% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            9273638      7.26%     99.14% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            1103003      0.86%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5                 52      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      198828194                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      127810874                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu               10786366     43.89%     43.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                    65      0.00%     43.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     43.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     43.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     43.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     43.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     43.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     43.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     43.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     43.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     43.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     43.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     43.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     43.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     43.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     43.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     43.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     43.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     43.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     43.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     43.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     43.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     43.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     43.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     43.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     43.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     43.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     43.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     43.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead               5629308     22.91%     66.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite              8160859     33.21%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                9324082     40.55%     40.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                    74      0.00%     40.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     40.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     40.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     40.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     40.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     40.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     40.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     40.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     40.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     40.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     40.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     40.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     40.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     40.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     40.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     40.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     40.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     40.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     40.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     40.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     40.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     40.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     40.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     40.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     40.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     40.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     40.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     40.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead               5582954     24.28%     64.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite              8086742     35.17%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.FU_type_0::No_OpClass             2273      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             89668905     67.55%     67.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult              111084      0.08%     67.63% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     67.63% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     67.63% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     67.63% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     67.63% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     67.63% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     67.63% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     67.63% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     67.63% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     67.63% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     67.63% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     67.63% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     67.63% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     67.63% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     67.63% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     67.63% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     67.63% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.63% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     67.63% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.63% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.63% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.63% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.63% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     67.63% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc          8099      0.01%     67.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     67.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead            24336393     18.33%     85.97% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           18619956     14.03%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             66279940     65.98%     65.98% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               93468      0.09%     66.07% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     66.07% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     66.07% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     66.07% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     66.07% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     66.07% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     66.07% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     66.07% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     66.07% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     66.07% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     66.07% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     66.07% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     66.07% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     66.07% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     66.07% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     66.07% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     66.07% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.07% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     66.07% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.07% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.07% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.07% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.07% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.07% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc          8018      0.01%     66.08% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.08% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.08% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.08% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead            18419781     18.34%     84.42% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           15653721     15.58%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total             132746710                       # Type of FU issued
-system.cpu0.iq.rate                          0.656129                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                   24576598                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.185139                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         489318685                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes        146908772                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses    129217545                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads              32566                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes             11248                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses         9717                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses             157299800                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                  21235                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          365614                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total             100457201                       # Type of FU issued
+system.cpu0.iq.rate                          0.762897                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                   22993852                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.228892                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         352138149                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes        113036952                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     98428366                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads              32549                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes             11294                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses         9716                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses             123427553                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                  21227                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          365954                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      1914996                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         2485                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        19372                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores       896753                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      1901526                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         2478                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        19250                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores       882682                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads       121022                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked       362352                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads       110051                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked       360569                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               2515967                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                1594217                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles               188418                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts          136474692                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewSquashCycles               1038512                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                1592668                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles               210705                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts          104136429                       # Number of instructions dispatched to IQ
 system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts             24576087                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            19059052                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts            876204                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 28441                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents               136041                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         19372                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        261507                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       398935                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              660442                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts            131715074                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts             23894149                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           964599                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewDispLoadInsts             18663457                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            16076197                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts            876152                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 28505                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents               158159                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         19250                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        253073                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       398879                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              651952                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             99436169                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts             17977378                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           955231                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       152467                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    42353114                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                25555008                       # Number of branches executed
-system.cpu0.iew.exec_stores                  18458965                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.651030                       # Inst execution rate
-system.cpu0.iew.wb_sent                     131158694                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                    129227262                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 65946343                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                106655009                       # num instructions consuming a value
-system.cpu0.iew.wb_rate                      0.638733                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.618315                       # average fanout of values written-back
-system.cpu0.commit.commitSquashedInsts        9548145                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls        1593081                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           603957                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    195669167                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.643258                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.340979                       # Number of insts commited each cycle
+system.cpu0.iew.exec_nop                       152952                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    33471315                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                16838084                       # Number of branches executed
+system.cpu0.iew.exec_stores                  15493937                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.755143                       # Inst execution rate
+system.cpu0.iew.wb_sent                      98890175                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     98438082                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 51269761                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 84681895                       # num instructions consuming a value
+system.cpu0.iew.wb_rate                      0.747564                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.605439                       # average fanout of values written-back
+system.cpu0.commit.commitSquashedInsts        8044326                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls        1573050                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           595336                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    126126769                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.753686                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.472161                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0    135298586     69.15%     69.15% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1     33412613     17.08%     86.22% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2     12639367      6.46%     92.68% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      3246710      1.66%     94.34% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4      4896676      2.50%     96.84% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5      2794942      1.43%     98.27% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      1306268      0.67%     98.94% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       556762      0.28%     99.22% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1517243      0.78%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0     81783872     64.84%     64.84% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1     24707932     19.59%     84.43% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      8259395      6.55%     90.98% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      3211630      2.55%     93.53% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      3438301      2.73%     96.25% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5      1493917      1.18%     97.44% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      1163537      0.92%     98.36% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       551177      0.44%     98.80% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1517008      1.20%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    195669167                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts           103932879                       # Number of instructions committed
-system.cpu0.commit.committedOps             125865777                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    126126769                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            79016795                       # Number of instructions committed
+system.cpu0.commit.committedOps              95059926                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      40823389                       # Number of memory references committed
-system.cpu0.commit.loads                     22661090                       # Number of loads committed
-system.cpu0.commit.membars                     647148                       # Number of memory barriers committed
-system.cpu0.commit.branches                  24954311                       # Number of branches committed
+system.cpu0.commit.refs                      31955445                       # Number of memory references committed
+system.cpu0.commit.loads                     16761930                       # Number of loads committed
+system.cpu0.commit.membars                     647782                       # Number of memory barriers committed
+system.cpu0.commit.branches                  16235143                       # Number of branches committed
 system.cpu0.commit.fp_insts                      9708                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                109885490                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls             4835541                       # Number of function calls committed.
+system.cpu0.commit.int_insts                 81982870                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls             1931434                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu        84925464     67.47%     67.47% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult         108825      0.09%     67.56% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv               0      0.00%     67.56% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     67.56% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     67.56% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     67.56% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     67.56% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     67.56% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     67.56% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     67.56% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     67.56% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     67.56% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     67.56% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     67.56% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     67.56% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     67.56% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     67.56% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     67.56% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     67.56% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     67.56% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     67.56% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     67.56% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     67.56% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     67.56% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     67.56% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc         8099      0.01%     67.57% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     67.57% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.57% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.57% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       22661090     18.00%     85.57% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      18162299     14.43%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu        63005341     66.28%     66.28% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult          91123      0.10%     66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv               0      0.00%     66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc         8017      0.01%     66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       16761930     17.63%     84.02% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      15193515     15.98%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total        125865777                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events              1517243                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                   306278084                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  273977566                       # The number of ROB writes
-system.cpu0.timesIdled                         123981                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                        3489819                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  5449576943                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                  103810827                       # Number of Instructions Simulated
-system.cpu0.committedOps                    125743725                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.948911                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.948911                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.513107                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.513107                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               142709258                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               81672792                       # number of integer regfile writes
+system.cpu0.commit.op_class_0::total         95059926                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events              1517008                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                   223519030                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  207883288                       # The number of ROB writes
+system.cpu0.timesIdled                         136700                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                        3867673                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  5520543918                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   78894743                       # Number of Instructions Simulated
+system.cpu0.committedOps                     94937874                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.669041                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.669041                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.599147                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.599147                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads               110427579                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               59611828                       # number of integer regfile writes
 system.cpu0.fp_regfile_reads                     8185                       # number of floating regfile reads
 system.cpu0.fp_regfile_writes                    2264                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                464864695                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes                49723023                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads              392114938                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes               1224736                       # number of misc regfile writes
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements           709879                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          499.426037                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           37661762                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           710391                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            53.015539                       # Average number of references to valid blocks.
+system.cpu0.cc_regfile_reads                350340790                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes                41062621                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads              252371624                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes               1225237                       # number of misc regfile writes
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.tags.replacements           711089                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          494.347987                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           28802334                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           711601                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            40.475398                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle        278078500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   499.426037                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.975441                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.975441                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   494.347987                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.965523                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.965523                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          174                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          322                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           16                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          155                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          338                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           19                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         81162963                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        81162963                       # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data     21452365                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       21452365                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     14987011                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      14987011                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       308699                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       308699                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       363086                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       363086                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       361018                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       361018                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     36439376                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        36439376                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     36748075                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       36748075                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       646473                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       646473                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1887751                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1887751                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       147620                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       147620                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        25081                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        25081                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20154                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total        20154                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      2534224                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       2534224                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      2681844                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2681844                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   8640238000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   8640238000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  29904279351                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  29904279351                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    399794500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    399794500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    485945500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total    485945500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       390500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total       390500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  38544517351                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  38544517351                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  38544517351                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  38544517351                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     22098838                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     22098838                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     16874762                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     16874762                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       456319                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       456319                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       388167                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       388167                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       381172                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       381172                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     38973600                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     38973600                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     39429919                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     39429919                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.029254                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.029254                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.111868                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.111868                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.323502                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.323502                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.064614                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.064614                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.052874                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.052874                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.065024                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.065024                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.068015                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.068015                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13365.195453                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 13365.195453                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15841.220241                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 15841.220241                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15940.133966                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15940.133966                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24111.615560                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24111.615560                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses         63463455                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        63463455                       # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.ReadReq_hits::cpu0.data     15558905                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       15558905                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     12019658                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      12019658                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       308619                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       308619                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       363044                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       363044                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       361281                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       361281                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     27578563                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        27578563                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     27887182                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       27887182                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       648058                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       648058                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1895809                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1895809                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       147818                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       147818                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        25317                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        25317                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20174                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total        20174                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      2543867                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       2543867                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      2691685                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      2691685                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   8928091500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   8928091500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  29690163364                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  29690163364                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    404195500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    404195500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    475433000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total    475433000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       570500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total       570500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  38618254864                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  38618254864                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  38618254864                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  38618254864                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     16206963                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     16206963                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     13915467                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     13915467                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       456437                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       456437                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       388361                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       388361                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       381455                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       381455                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     30122430                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     30122430                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     30578867                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     30578867                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.039986                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.039986                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.136238                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.136238                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.323852                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.323852                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.065189                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.065189                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.052887                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.052887                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.084451                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.084451                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.088024                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.088024                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13776.685883                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 13776.685883                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15660.946522                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 15660.946522                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15965.378994                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15965.378994                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23566.620402                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23566.620402                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15209.593687                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 15209.593687                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14372.393529                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 14372.393529                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs          691                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets      4275244                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs               43                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets         201901                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    16.069767                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    21.174952                       # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks       709879                       # number of writebacks
-system.cpu0.dcache.writebacks::total           709879                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       258972                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       258972                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1563802                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1563802                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        18565                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18565                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1822774                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1822774                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1822774                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1822774                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       387501                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       387501                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       323949                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       323949                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       101413                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       101413                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6516                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6516                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20154                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total        20154                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       711450                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       711450                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       812863                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       812863                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        31772                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31772                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        28451                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        28451                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        60223                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        60223                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4575351000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4575351000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6134433385                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6134433385                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1666291000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1666291000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    103051000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    103051000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    465800500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    465800500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       381500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       381500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  10709784385                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  10709784385                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  12376075385                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  12376075385                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6621057500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6621057500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6621057500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6621057500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.017535                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.017535                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019197                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019197                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.222241                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.222241                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016787                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016787                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.052874                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.052874                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.018255                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.018255                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.020615                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.020615                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11807.326949                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11807.326949                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18936.417106                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18936.417106                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16430.743593                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16430.743593                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15815.070595                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15815.070595                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23112.062122                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23112.062122                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15180.925286                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 15180.925286                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14347.241547                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 14347.241547                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs         1034                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets      4271446                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs               48                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets         202383                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    21.541667                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    21.105755                       # average number of cycles each access was blocked
+system.cpu0.dcache.writebacks::writebacks       711089                       # number of writebacks
+system.cpu0.dcache.writebacks::total           711089                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       260039                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       260039                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1570278                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1570278                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        18696                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18696                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1830317                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1830317                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1830317                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1830317                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       388019                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       388019                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       325531                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       325531                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       101607                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       101607                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6621                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6621                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20174                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total        20174                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       713550                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       713550                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       815157                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       815157                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        20336                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        20336                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        19032                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        19032                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        39368                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        39368                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4833813000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4833813000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5968230399                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5968230399                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1672759500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1672759500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    104692000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    104692000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    455274000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    455274000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       555500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       555500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  10802043399                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  10802043399                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  12474802899                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  12474802899                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   4534406000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   4534406000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   4534406000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   4534406000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.023941                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.023941                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.023393                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.023393                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.222609                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.222609                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.017049                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.017049                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.052887                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.052887                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023688                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.023688                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.026658                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.026658                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12457.670887                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12457.670887                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18333.831184                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18333.831184                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16463.034043                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16463.034043                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15812.112974                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15812.112974                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22567.363934                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22567.363934                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15053.460377                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15053.460377                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15225.290590                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15225.290590                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208392.845902                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208392.845902                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 109942.339306                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 109942.339306                       # average overall mshr uncacheable latency
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements          1252995                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.762307                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           71397425                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1253507                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            56.958138                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       7880422000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.762307                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999536                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999536                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          152                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          232                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          128                       # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        146662859                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       146662859                       # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst     71397425                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       71397425                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     71397425                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        71397425                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     71397425                       # number of overall hits
-system.cpu0.icache.overall_hits::total       71397425                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      1307231                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1307231                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      1307231                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1307231                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      1307231                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1307231                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  13217921463                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  13217921463                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  13217921463                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  13217921463                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  13217921463                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  13217921463                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     72704656                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     72704656                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     72704656                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     72704656                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     72704656                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     72704656                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.017980                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.017980                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.017980                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.017980                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.017980                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.017980                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10111.389236                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 10111.389236                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10111.389236                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 10111.389236                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10111.389236                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 10111.389236                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs      1578280                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets          443                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs           112202                       # number of cycles access was blocked
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15138.453366                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15138.453366                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15303.558577                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15303.558577                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222974.331235                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222974.331235                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115179.993904                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115179.993904                       # average overall mshr uncacheable latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.tags.replacements          1254577                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.762789                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           36189840                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1255088                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            28.834504                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle       6511134000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.762789                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999537                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999537                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          143                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          238                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          130                       # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses         76255085                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        76255085                       # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.ReadReq_hits::cpu0.inst     36189843                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       36189843                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     36189843                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        36189843                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     36189843                       # number of overall hits
+system.cpu0.icache.overall_hits::total       36189843                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      1310126                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1310126                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      1310126                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1310126                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      1310126                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1310126                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  13674177457                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  13674177457                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  13674177457                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  13674177457                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  13674177457                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  13674177457                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     37499969                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     37499969                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     37499969                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     37499969                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     37499969                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     37499969                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.034937                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.034937                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.034937                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.034937                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.034937                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.034937                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10437.299509                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 10437.299509                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10437.299509                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 10437.299509                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10437.299509                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 10437.299509                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs      1615389                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets          855                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs           113956                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets             10                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    14.066416                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets    44.300000                       # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks      1252995                       # number of writebacks
-system.cpu0.icache.writebacks::total          1252995                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        53683                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        53683                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        53683                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        53683                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        53683                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        53683                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1253548                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1253548                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      1253548                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1253548                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      1253548                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1253548                       # number of overall MSHR misses
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    14.175550                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets    85.500000                       # average number of cycles each access was blocked
+system.cpu0.icache.writebacks::writebacks      1254577                       # number of writebacks
+system.cpu0.icache.writebacks::total          1254577                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        54978                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        54978                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        54978                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        54978                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        54978                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        54978                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1255148                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1255148                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      1255148                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1255148                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      1255148                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1255148                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         3003                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total         3003                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         3003                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total         3003                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11993376465                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  11993376465                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11993376465                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  11993376465                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11993376465                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  11993376465                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12423139434                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  12423139434                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12423139434                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  12423139434                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12423139434                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  12423139434                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    269145498                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    269145498                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    269145498                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total    269145498                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.017242                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.017242                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.017242                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.017242                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.017242                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.017242                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9567.544653                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9567.544653                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9567.544653                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total  9567.544653                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9567.544653                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total  9567.544653                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.033471                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.033471                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.033471                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.033471                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.033471                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.033471                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9897.748659                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9897.748659                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9897.748659                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total  9897.748659                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9897.748659                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total  9897.748659                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89625.540460                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89625.540460                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      1837427                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      1839978                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit         2305                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      1846782                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      1849282                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit         2270                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage       236878                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.tags.replacements          277234                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16111.552153                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs           3276769                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs          293338                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs           11.170626                       # Average number of references to valid blocks.
+system.cpu0.l2cache.prefetcher.pfSpanPage       236718                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.cpu0.l2cache.tags.replacements          273792                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       15633.615902                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs           1886952                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs          289401                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            6.520199                       # Average number of references to valid blocks.
 system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 14693.899751                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    11.282247                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.429995                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1405.940159                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.896844                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000689                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000026                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.085812                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.983371                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1005                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_blocks::writebacks 14449.190897                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    12.342760                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.746834                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1171.335411                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.881909                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000753                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000046                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.071493                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.954200                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022          271                       # Occupied blocks per task id
 system.cpu0.l2cache.tags.occ_task_id_blocks::1023           10                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15089                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           38                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          280                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          408                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          279                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            3                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            4                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            3                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          460                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4705                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7019                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2801                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.061340                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15328                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1            4                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2           66                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          120                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4           81                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            5                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          311                       # Occupied blocks per task id
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 system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000610                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.920959                       # Percentage of cache occupancy per task id
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+system.cpu0.l2cache.demand_accesses::total      2090635                       # number of demand (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        56056                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker        13406                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst      1255100                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data       766073                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total      2090635                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.008902                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.013800                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.009847                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.999928                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.999928                       # miss rate for UpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.177655                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.177655                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.042631                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.042631                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.195310                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.195310                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.007514                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.011370                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.042631                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.189095                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.095135                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.007514                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.011370                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.042631                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.189095                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.095135                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 28405.952381                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23605.960265                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 27136.602452                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  1984.112268                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  1984.112268                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  1180.767131                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  1180.767131                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       365500                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       365500                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 58366.283163                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 58366.283163                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 52276.264082                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 52276.264082                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 30529.377379                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 30529.377379                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 28405.952381                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23605.960265                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 52276.264082                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 39736.387123                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 43074.982348                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 28405.952381                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23605.960265                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 52276.264082                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 39736.387123                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 43074.982348                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs          102                       # number of cycles access was blocked
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.180847                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.180847                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.056770                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.056770                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.218143                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.218143                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.008902                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.013800                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.056770                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.205001                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.109527                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.008902                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.013800                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.056770                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.205001                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.109527                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 28160.320641                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23275.675676                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 26839.181287                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data   675.093230                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total   675.093230                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data   474.491820                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total   474.491820                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 132999.500000                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 132999.500000                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 55757.881476                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 55757.881476                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 46933.054511                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 46933.054511                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 30435.839710                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 30435.839710                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 28160.320641                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23275.675676                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 46933.054511                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38307.075608                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 40956.952931                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 28160.320641                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23275.675676                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 46933.054511                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38307.075608                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 40956.952931                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs          201                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs               3                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs               6                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs           34                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    33.500000                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.l2cache.unused_prefetches           10219                       # number of HardPF blocks evicted w/o reference
-system.cpu0.l2cache.writebacks::writebacks       230013                       # number of writebacks
-system.cpu0.l2cache.writebacks::total          230013                       # number of writebacks
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         5832                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total         5832                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           47                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           47                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          763                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          763                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           47                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data         6595                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total         6642                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           47                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data         6595                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total         6642                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          420                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          151                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total          571                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       257265                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       257265                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        55011                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total        55011                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        20153                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        20153                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            1                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        41978                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total        41978                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        53391                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        53391                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data        95978                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total        95978                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          420                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          151                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        53391                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data       137956                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total       191918                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          420                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          151                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        53391                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data       137956                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       257265                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total       449183                       # number of overall MSHR misses
+system.cpu0.l2cache.unused_prefetches           10619                       # number of HardPF blocks evicted w/o reference
+system.cpu0.l2cache.writebacks::writebacks       231332                       # number of writebacks
+system.cpu0.l2cache.writebacks::total          231332                       # number of writebacks
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            1                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker            4                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_hits::total            5                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         5717                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::total         5717                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           36                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           36                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          739                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          739                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            1                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker            4                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           36                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.data         6456                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::total         6497                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker            1                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker            4                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           36                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.data         6456                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::total         6497                       # number of overall MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          498                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          181                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::total          679                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       265620                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::total       265620                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        55776                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total        55776                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        20170                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        20170                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            4                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            4                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        43100                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::total        43100                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        71216                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        71216                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       107490                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       107490                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          498                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          181                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        71216                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.data       150590                       # number of demand (read+write) MSHR misses
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+system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        71216                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.data       150590                       # number of overall MSHR misses
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+system.cpu0.l2cache.overall_mshr_misses::total       488105                       # number of overall MSHR misses
 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         3003                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        31772                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        34775                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        28451                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        28451                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        20336                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        23339                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        19032                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        19032                       # number of WriteReq MSHR uncacheable
 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         3003                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        60223                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        63226                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker      9410500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      2658500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     12069000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  15460252226                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  15460252226                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   1068009500                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   1068009500                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    313481500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    313481500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       311500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       311500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   1799415000                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1799415000                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   2471910000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   2471910000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2337830497                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2337830497                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker      9410500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      2658500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   2471910000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   4137245497                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total   6621224497                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker      9410500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      2658500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   2471910000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   4137245497                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  15460252226                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total  22081476723                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        39368                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        42371                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     11046000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      3157500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     14203500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  15282370178                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  15282370178                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    964881000                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    964881000                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    302897000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    302897000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       441998                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       441998                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   1759055000                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1759055000                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   2915623000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   2915623000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2607419996                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2607419996                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     11046000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      3157500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   2915623000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   4366474996                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total   7296301496                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     11046000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      3157500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   2915623000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   4366474996                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  15282370178                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total  22578671674                       # number of overall MSHR miss cycles
 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    246621000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   6366599000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6613220000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   4371369500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   4617990500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    246621000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   6366599000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   6613220000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.007514                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.011370                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.008254                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   4371369500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   4617990500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.008884                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.013501                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.009775                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.999982                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.999982                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.999928                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.999928                       # mshr miss rate for UpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.155984                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.155984                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.042593                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.042593                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.193770                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.193770                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.007514                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.011370                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.042593                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.180467                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.091953                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.007514                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.011370                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.042593                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.180467                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.159667                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.159667                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.056741                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.056741                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.216654                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.216654                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.008884                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.013501                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.056741                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.196574                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.106420                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.008884                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.013501                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.056741                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.196574                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.215216                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 22405.952381                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17605.960265                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21136.602452                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60094.658138                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 60094.658138                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19414.471651                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19414.471651                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15555.078648                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15555.078648                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       311500                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       311500                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 42865.667731                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 42865.667731                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 46298.252514                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 46298.252514                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24357.983048                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24357.983048                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 22405.952381                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17605.960265                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 46298.252514                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29989.601735                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34500.278749                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 22405.952381                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17605.960265                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 46298.252514                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29989.601735                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60094.658138                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 49159.199531                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.233472                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 22180.722892                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17444.751381                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20918.262150                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 57534.711912                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 57534.711912                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17299.214716                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17299.214716                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15017.203768                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15017.203768                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 110499.500000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 110499.500000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40813.341067                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40813.341067                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 40940.561110                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 40940.561110                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24257.326226                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24257.326226                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 22180.722892                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17444.751381                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 40940.561110                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28995.783226                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32794.577145                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 22180.722892                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17444.751381                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 40940.561110                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28995.783226                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 57534.711912                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46257.816810                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82124.875125                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200383.954425                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 190171.675054                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 214957.194138                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 197865.825442                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 82124.875125                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105717.068230                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 104596.526745                       # average overall mshr uncacheable latency
-system.cpu0.toL2Bus.snoop_filter.tot_requests      4076758                       # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests      2058809                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        31269                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops       324106                       # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       319070                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         5036                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.cpu0.toL2Bus.trans_dist::ReadReq        113929                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp      1910818                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        28451                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        28451                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty       712670                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean      1480466                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict       204485                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq       327834                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq        86644                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42628                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       112569                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           27                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           35                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq       287578                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp       284142                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1253548                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq       576173                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq         3244                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3766063                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2610032                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        29029                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       119282                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total          6524406                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    160464624                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     98586020                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        53124                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       223588                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total         259327356                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    1029792                       # Total snoops (count)
-system.cpu0.toL2Bus.snoopTraffic             18816792                       # Total snoop traffic (bytes)
-system.cpu0.toL2Bus.snoop_fanout::samples      3154811                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       0.120834                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.330795                       # Request fanout histogram
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111038.648141                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 108989.414930                       # average overall mshr uncacheable latency
+system.cpu0.toL2Bus.snoop_filter.tot_requests      4083931                       # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests      2062737                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        31284                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops       216422                       # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       214567                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         1855                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.cpu0.toL2Bus.trans_dist::ReadReq        102316                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp      1901889                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        19032                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        19032                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty       714747                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean      1482534                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict        90142                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       335134                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq        87548                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42677                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       113494                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq            8                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           19                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq       288350                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp       285091                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1255148                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq       586492                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq         3253                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3770830                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2574893                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        29200                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       119227                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total          6494150                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    160667312                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     98708808                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        53624                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       224224                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total         259653968                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                     933771                       # Total snoops (count)
+system.cpu0.toL2Bus.snoopTraffic             18925704                       # Total snoop traffic (bytes)
+system.cpu0.toL2Bus.snoop_fanout::samples      3041721                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       0.089004                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.286883                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0           2778640     88.08%     88.08% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1            371135     11.76%     99.84% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2              5036      0.16%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0           2772852     91.16%     91.16% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1            267014      8.78%     99.94% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2              1855      0.06%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total       3154811                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy    4076288994                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total       3041721                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy    4067278494                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    113402059                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    114026414                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   1883892360                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   1886176090                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   1231592300                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   1218391120                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy     15761972                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy     15802982                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy     63433401                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy     63205426                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups                4691512                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted          2780704                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           269312                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups             2468444                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                1570862                       # Number of BTB hits
+system.cpu1.branchPred.lookups               33853439                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         11509465                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           280542                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            18730917                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                5987349                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            63.637741                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                 878870                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect              7026                       # Number of incorrect RAS predictions.
-system.cpu1.branchPred.indirectLookups         249224                       # Number of indirect predictor lookups.
-system.cpu1.branchPred.indirectHits            213650                       # Number of indirect target hits.
-system.cpu1.branchPred.indirectMisses           35574                       # Number of indirect misses.
-system.cpu1.branchPredindirectMispredicted        10610                       # Number of mispredicted indirect branches.
-system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
+system.cpu1.branchPred.BTBHitPct            31.965061                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS               12496464                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect              7318                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.indirectLookups        9007806                       # Number of indirect predictor lookups.
+system.cpu1.branchPred.indirectHits           8970953                       # Number of indirect target hits.
+system.cpu1.branchPred.indirectMisses           36853                       # Number of indirect misses.
+system.cpu1.branchPredindirectMispredicted        10907                       # Number of mispredicted indirect branches.
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1657,90 +1661,89 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dtb.walker.walks                    21486                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort               21486                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1         8656                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         5913                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore         6917                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples        14569                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean   593.417530                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev  3219.344489                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-4095        13924     95.57%     95.57% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::4096-8191          194      1.33%     96.90% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::8192-12287          239      1.64%     98.54% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::12288-16383           88      0.60%     99.15% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::16384-20479           24      0.16%     99.31% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::20480-24575           16      0.11%     99.42% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::24576-28671            5      0.03%     99.46% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::28672-32767           66      0.45%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::32768-36863            2      0.01%     99.92% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::36864-40959            7      0.05%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.walker.walks                    21636                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort               21636                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1         8665                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         5933                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore         7038                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples        14598                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean   649.780792                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev  3376.631612                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-4095        13908     95.27%     95.27% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::4096-8191          186      1.27%     96.55% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::8192-12287          234      1.60%     98.15% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::12288-16383          108      0.74%     98.89% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::16384-20479           46      0.32%     99.21% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::20480-24575           30      0.21%     99.41% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::24576-28671            8      0.05%     99.47% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::28672-32767           66      0.45%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::32768-36863            4      0.03%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::36864-40959            4      0.03%     99.97% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::40960-45055            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::45056-49151            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::49152-53247            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::53248-57343            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total        14569                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples         5700                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 11230.789474                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean  9917.122912                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev  6183.592938                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-8191         1944     34.11%     34.11% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::8192-16383         3149     55.25%     89.35% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-24575          398      6.98%     96.33% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::24576-32767          155      2.72%     99.05% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-40959           22      0.39%     99.44% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::40960-49151           24      0.42%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::49152-57343            5      0.09%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::57344-65535            1      0.02%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::90112-98303            1      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkWaitTime::53248-57343            2      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total        14598                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples         5531                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 11435.002712                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 10101.039860                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  6336.393968                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-8191         1833     33.14%     33.14% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::8192-16383         3041     54.98%     88.12% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-24575          457      8.26%     96.38% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::24576-32767          138      2.50%     98.88% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-40959           31      0.56%     99.44% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::40960-49151           23      0.42%     99.86% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::49152-57343            4      0.07%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::57344-65535            2      0.04%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::98304-106495            1      0.02%     99.98% # Table walker service (enqueue to completion) latency
 system.cpu1.dtb.walker.walkCompletionTime::106496-114687            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total         5700                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples  72594020264                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.245062                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.433850                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0-1  72572506264     99.97%     99.97% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::2-3     16659500      0.02%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4-5      2233500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::6-7      1798000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8-9       337000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::10-11       155000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12-13       183000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::14-15       133000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::16-17        15000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total  72594020264                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K         1956     73.89%     73.89% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M          691     26.11%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         2647                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        21486                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkCompletionTime::total         5531                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples  68460974968                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.179525                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.388721                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0-1  68438733968     99.97%     99.97% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::2-3     17027000      0.02%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4-5      2383000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::6-7      1817500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8-9       437500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::10-11       205000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12-13       153500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::14-15       216500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::16-17         1000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total  68460974968                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K         1927     75.51%     75.51% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M          625     24.49%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         2552                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        21636                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        21486                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2647                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        21636                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2552                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2647                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total        24133                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2552                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        24188                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     4198525                       # DTB read hits
-system.cpu1.dtb.read_misses                     18524                       # DTB read misses
-system.cpu1.dtb.write_hits                    3495808                       # DTB write hits
-system.cpu1.dtb.write_misses                     2962                       # DTB write misses
+system.cpu1.dtb.read_hits                    10130487                       # DTB read hits
+system.cpu1.dtb.read_misses                     18672                       # DTB read misses
+system.cpu1.dtb.write_hits                    6476473                       # DTB write hits
+system.cpu1.dtb.write_misses                     2964                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    1985                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                       48                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   390                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries                    1961                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                       63                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                   385                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      375                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 4217049                       # DTB read accesses
-system.cpu1.dtb.write_accesses                3498770                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      370                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                10149159                       # DTB read accesses
+system.cpu1.dtb.write_accesses                6479437                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                          7694333                       # DTB hits
-system.cpu1.dtb.misses                          21486                       # DTB misses
-system.cpu1.dtb.accesses                      7715819                       # DTB accesses
-system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.hits                         16606960                       # DTB hits
+system.cpu1.dtb.misses                          21636                       # DTB misses
+system.cpu1.dtb.accesses                     16628596                       # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1770,62 +1773,57 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.cpu1.itb.walker.walks                     5992                       # Table walker walks requested
-system.cpu1.itb.walker.walksShort                5992                       # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1         2735                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2646                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore          611                       # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples         5381                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean   357.461438                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev  2249.604382                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-2047         5186     96.38%     96.38% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::2048-4095           43      0.80%     97.18% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::4096-6143           39      0.72%     97.90% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::6144-8191           21      0.39%     98.29% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::8192-10239           21      0.39%     98.68% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::10240-12287           16      0.30%     98.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::12288-14335           17      0.32%     99.29% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::14336-16383            9      0.17%     99.46% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::16384-18431            6      0.11%     99.57% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::18432-20479            2      0.04%     99.61% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::20480-22527            6      0.11%     99.72% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::22528-24575            3      0.06%     99.78% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::24576-26623            4      0.07%     99.85% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::26624-28671            4      0.07%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::28672-30719            2      0.04%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::30720-32767            2      0.04%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total         5381                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples         1781                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 11779.618192                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 10714.112038                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev  6875.589868                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-16383         1655     92.93%     92.93% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-32767           93      5.22%     98.15% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-49151           29      1.63%     99.78% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::49152-65535            1      0.06%     99.83% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-81919            1      0.06%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-147455            2      0.11%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total         1781                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples  16739710416                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean     0.877376                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev     0.328141                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0     2053443264     12.27%     12.27% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1    14685521152     87.73%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2         746000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total  16739710416                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K          995     85.04%     85.04% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M          175     14.96%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total         1170                       # Table walker page sizes translated
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.cpu1.itb.walker.walks                     6064                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                6064                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1         2840                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2623                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore          601                       # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples         5463                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean   343.950211                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev  2166.504505                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-4095         5312     97.24%     97.24% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::4096-8191           57      1.04%     98.28% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::8192-12287           43      0.79%     99.07% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::12288-16383           29      0.53%     99.60% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::16384-20479            6      0.11%     99.71% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::20480-24575            5      0.09%     99.80% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::24576-28671            5      0.09%     99.89% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::28672-32767            5      0.09%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::32768-36863            1      0.02%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total         5463                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples         1764                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 12147.108844                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 11115.999882                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  5636.944380                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-8191          277     15.70%     15.70% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-16383         1298     73.58%     89.29% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-24575          111      6.29%     95.58% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-32767           59      3.34%     98.92% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-40959            9      0.51%     99.43% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-49151            7      0.40%     99.83% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::49152-57343            2      0.11%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-73727            1      0.06%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total         1764                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples  16901758916                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean     0.861276                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev     0.345783                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0     2345411264     13.88%     13.88% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1    14555617152     86.12%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2         730500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total  16901758916                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K          989     85.04%     85.04% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          174     14.96%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total         1163                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         5992                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total         5992                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         6064                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total         6064                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1170                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1170                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total         7162                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                     8257878                       # ITB inst hits
-system.cpu1.itb.inst_misses                      5992                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1163                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1163                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total         7227                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                    43493383                       # ITB inst hits
+system.cpu1.itb.inst_misses                      6064                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
@@ -1834,1032 +1832,1023 @@ system.cpu1.itb.flush_tlb                          66                       # Nu
 system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    1134                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    1129                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                      574                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                      581                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                 8263870                       # ITB inst accesses
-system.cpu1.itb.hits                          8257878                       # DTB hits
-system.cpu1.itb.misses                           5992                       # DTB misses
-system.cpu1.itb.accesses                      8263870                       # DTB accesses
-system.cpu1.numPwrStateTransitions               5517                       # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples         2759                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean    1017941071.285973                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev   25840669198.429722                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::underflows         1966     71.26%     71.26% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1000-5e+10          787     28.52%     99.78% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::5e+10-1e+11            2      0.07%     99.86% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11            1      0.04%     99.89% # Distribution of time spent in the clock gated state
+system.cpu1.itb.inst_accesses                43499447                       # ITB inst accesses
+system.cpu1.itb.hits                         43493383                       # DTB hits
+system.cpu1.itb.misses                           6064                       # DTB misses
+system.cpu1.itb.accesses                     43499447                       # DTB accesses
+system.cpu1.numPwrStateTransitions               5513                       # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples         2757                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean    1005805033.413856                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev   25768715425.209221                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows         1955     70.91%     70.91% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10          798     28.94%     99.85% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5e+10-1e+11            1      0.04%     99.89% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11            1      0.04%     99.93% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11            1      0.04%     99.96% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12            1      0.04%    100.00% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::max_value 959984595936                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total           2759                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON    17447990322                       # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 2808499415678                       # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles                        34896767                       # number of cpu cycles simulated
+system.cpu1.pwrStateClkGateDist::min_value          500                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::max_value 959983620244                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total           2757                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON    53106605878                       # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 2773004477122                       # Cumulative time (in ticks) in various power states
+system.cpu1.numCycles                       106214002                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles           8573013                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                      24834691                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                    4691512                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches           2663382                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                     24575638                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                 780918                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                     78787                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles               29336                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles       166978                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       305850                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles        23292                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                  8256698                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes               107917                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                   2264                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples          34143353                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             0.885357                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            1.219701                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles          10283907                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                     108683336                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                   33853439                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches          27454766                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                     92513470                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                3739662                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                     81877                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles               30058                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles       180666                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       303073                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles        23077                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                 43492215                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes               108878                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                   2205                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         105285959                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.278787                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            1.339334                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                20247760     59.30%     59.30% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                 4892921     14.33%     73.63% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                 1671892      4.90%     78.53% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                 7330780     21.47%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                48617714     46.18%     46.18% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                13927599     13.23%     59.41% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                 7511266      7.13%     66.54% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                35229380     33.46%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total            34143353                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.134440                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.711662                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                 7142387                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles             16886237                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                  8753269                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles              1097578                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles                263882                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved              709919                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred               129188                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              23442151                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts              1047211                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles                263882                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                 8565513                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                2371212                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles      11834998                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                  8406528                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles              2701220                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              22274891                       # Number of instructions processed by rename
-system.cpu1.rename.SquashedInsts               187368                       # Number of squashed instructions processed by rename
-system.cpu1.rename.ROBFullEvents               265665                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                 37047                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                 14963                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents               1683318                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands           22278743                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            103710935                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups        25664622                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups             1667                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps             19882725                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                 2396018                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts            407656                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts        334437                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                  2896541                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads             4450446                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores            3799896                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads           626454                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores          628235                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  21459278                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded             560382                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 21266552                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued            92050                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined        2043308                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined      4721488                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved         43321                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples     34143353                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.622861                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       0.949388                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total           105285959                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.318729                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       1.023249                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                13161149                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles             62754723                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                 26539387                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles              1087783                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               1742917                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved              736717                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred               129511                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              67619846                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts              1094387                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               1742917                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                17542611                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                2352209                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles      57806856                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                 23225004                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles              2616362                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              54744976                       # Number of instructions processed by rename
+system.cpu1.rename.SquashedInsts               213737                       # Number of squashed instructions processed by rename
+system.cpu1.rename.ROBFullEvents               258070                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                 37169                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                 15433                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents               1611507                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands           54654605                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            258629758                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups        58168286                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups             1683                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps             52142746                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                 2511859                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts           1875660                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts       1802517                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                 13071586                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads            10382439                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            6812181                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads           622946                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores          790955                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  53883918                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded             580977                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 53654093                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            93763                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined        3608749                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined      5111945                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved         44050                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    105285959                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.509603                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       0.847754                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           21621380     63.33%     63.33% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1            6152293     18.02%     81.34% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2            4252408     12.45%     93.80% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3            1859652      5.45%     99.25% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4             257613      0.75%    100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5                  7      0.00%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           72150462     68.53%     68.53% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1           16497460     15.67%     84.20% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2           13036209     12.38%     96.58% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3            3323109      3.16%     99.74% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4             278707      0.26%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5                 12      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total       34143353                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      105285959                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                1436712     29.87%     29.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                   667      0.01%     29.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%     29.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     29.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     29.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     29.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     29.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     29.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     29.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     29.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     29.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     29.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     29.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     29.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     29.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     29.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     29.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     29.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     29.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     29.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     29.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     29.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     29.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     29.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     29.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     29.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     29.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     29.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     29.88% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead               1615148     33.58%     63.46% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite              1757949     36.54%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                2901953     45.47%     45.47% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                   671      0.01%     45.48% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%     45.48% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     45.48% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     45.48% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     45.48% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%     45.48% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     45.48% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     45.48% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     45.48% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     45.48% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     45.48% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     45.48% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     45.48% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     45.48% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%     45.48% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     45.48% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%     45.48% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     45.48% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     45.48% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     45.48% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     45.48% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     45.48% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     45.48% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     45.48% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     45.48% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     45.48% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.48% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     45.48% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead               1666030     26.11%     71.59% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite              1813313     28.41%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.FU_type_0::No_OpClass               66      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu             13152288     61.84%     61.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               28200      0.13%     61.98% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     61.98% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     61.98% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     61.98% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     61.98% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     61.98% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     61.98% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     61.98% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     61.98% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     61.98% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     61.98% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     61.98% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     61.98% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     61.98% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     61.98% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     61.98% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     61.98% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     61.98% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     61.98% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     61.98% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     61.98% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     61.98% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     61.98% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     61.98% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc          3301      0.02%     61.99% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     61.99% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.99% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     61.99% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead             4404606     20.71%     82.70% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite            3678091     17.30%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu             36596131     68.21%     68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               45838      0.09%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc          3311      0.01%     68.30% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.30% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.30% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.30% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead            10338451     19.27%     87.57% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite            6670296     12.43%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              21266552                       # Type of FU issued
-system.cpu1.iq.rate                          0.609413                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                    4810476                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.226199                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads          81572724                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         24071099                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     20803651                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads               6259                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes              2054                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses         1789                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              26072828                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                   4134                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads           87634                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total              53654093                       # Type of FU issued
+system.cpu1.iq.rate                          0.505151                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                    6381967                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.118947                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads         219063644                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         58081406                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     51689844                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads               6231                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes              2072                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses         1788                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses              60031897                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                   4097                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads           89933                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads       411414                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses          595                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation        10207                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores       255357                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads       434041                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses          639                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation         9872                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores       275866                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads        40430                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked        77958                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads        52151                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked        77961                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles                263882                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                 544522                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles                96828                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           22060743                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewSquashCycles               1742917                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                 520776                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles               103336                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           54505946                       # Number of instructions dispatched to IQ
 system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts              4450446                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts             3799896                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            297241                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                  7639                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents                82763                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents         10207                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect         34804                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       119058                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              153862                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             21034955                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts              4309085                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts           210133                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewDispLoadInsts             10382439                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts             6812181                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            296650                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                  7746                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents                89089                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents          9872                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect         44543                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect       120099                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              164642                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             53411917                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts             10242028                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           220561                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                        41083                       # number of nop insts executed
-system.cpu1.iew.exec_refs                     7936975                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                 3061868                       # Number of branches executed
-system.cpu1.iew.exec_stores                   3627890                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.602777                       # Inst execution rate
-system.cpu1.iew.wb_sent                      20903580                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     20805440                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                 10431521                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                 16355895                       # num instructions consuming a value
-system.cpu1.iew.wb_rate                      0.596200                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.637784                       # average fanout of values written-back
-system.cpu1.commit.commitSquashedInsts        1829884                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls         517061                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           142735                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples     33733433                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.593157                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.351929                       # Number of insts commited each cycle
+system.cpu1.iew.exec_nop                        41051                       # number of nop insts executed
+system.cpu1.iew.exec_refs                    16861277                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                11793508                       # Number of branches executed
+system.cpu1.iew.exec_stores                   6619249                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.502871                       # Inst execution rate
+system.cpu1.iew.wb_sent                      53270244                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     51691632                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                 25129407                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                 38339279                       # num instructions consuming a value
+system.cpu1.iew.wb_rate                      0.486674                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.655448                       # average fanout of values written-back
+system.cpu1.commit.commitSquashedInsts        3369485                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         536927                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           153628                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    103395222                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.492179                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.152090                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     24180502     71.68%     71.68% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1      5607484     16.62%     88.30% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2      1690092      5.01%     93.31% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3       667448      1.98%     95.29% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4       524113      1.55%     96.85% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5       341983      1.01%     97.86% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6       221163      0.66%     98.52% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7       119335      0.35%     98.87% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8       381313      1.13%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     77830115     75.27%     75.27% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1     14293086     13.82%     89.10% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2      6071280      5.87%     94.97% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3       693599      0.67%     95.64% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4      1980010      1.91%     97.56% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5      1625143      1.57%     99.13% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6       382099      0.37%     99.50% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       124911      0.12%     99.62% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8       394979      0.38%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total     33733433                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts            16346571                       # Number of instructions committed
-system.cpu1.commit.committedOps              20009206                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    103395222                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts            41318794                       # Number of instructions committed
+system.cpu1.commit.committedOps              50889001                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                       7583571                       # Number of memory references committed
-system.cpu1.commit.loads                      4039032                       # Number of loads committed
-system.cpu1.commit.membars                     208429                       # Number of memory barriers committed
-system.cpu1.commit.branches                   2907402                       # Number of branches committed
+system.cpu1.commit.refs                      16484713                       # Number of memory references committed
+system.cpu1.commit.loads                      9948398                       # Number of loads committed
+system.cpu1.commit.membars                     208127                       # Number of memory barriers committed
+system.cpu1.commit.branches                  11637916                       # Number of branches committed
 system.cpu1.commit.fp_insts                      1784                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                 17776817                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls              462681                       # Number of function calls committed.
+system.cpu1.commit.int_insts                 45745086                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls             3368055                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu        12395212     61.95%     61.95% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult          27122      0.14%     62.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv               0      0.00%     62.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     62.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     62.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     62.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     62.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     62.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     62.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     62.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     62.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     62.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     62.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     62.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     62.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     62.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     62.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     62.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     62.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     62.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     62.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     62.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     62.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     62.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     62.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc         3301      0.02%     62.10% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     62.10% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     62.10% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     62.10% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead        4039032     20.19%     82.29% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite       3544539     17.71%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu        34356210     67.51%     67.51% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult          44767      0.09%     67.60% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.60% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.60% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.60% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.60% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.60% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.60% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.60% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.60% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.60% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.60% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.60% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.60% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.60% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.60% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.60% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.60% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.60% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.60% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.60% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.60% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.60% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.60% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.60% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc         3311      0.01%     67.61% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.61% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.61% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.61% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead        9948398     19.55%     87.16% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite       6536315     12.84%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total         20009206                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events               381313                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                    54211090                       # The number of ROB reads
-system.cpu1.rob.rob_writes                   44079362                       # The number of ROB writes
-system.cpu1.timesIdled                          55353                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                         753414                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  5616440201                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                   16313716                       # Number of Instructions Simulated
-system.cpu1.committedOps                     19976351                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              2.139106                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        2.139106                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.467485                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.467485                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                23597502                       # number of integer regfile reads
-system.cpu1.int_regfile_writes               13487852                       # number of integer regfile writes
+system.cpu1.commit.op_class_0::total         50889001                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events               394979                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                   137189075                       # The number of ROB reads
+system.cpu1.rob.rob_writes                  110398979                       # The number of ROB writes
+system.cpu1.timesIdled                          58975                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                         928043                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  5545446856                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                   41285938                       # Number of Instructions Simulated
+system.cpu1.committedOps                     50856145                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              2.572644                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        2.572644                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.388705                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.388705                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                55995090                       # number of integer regfile reads
+system.cpu1.int_regfile_writes               35603094                       # number of integer regfile writes
 system.cpu1.fp_regfile_reads                     1401                       # number of floating regfile reads
 system.cpu1.fp_regfile_writes                     516                       # number of floating regfile writes
-system.cpu1.cc_regfile_reads                 75515975                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes                 6821727                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads               68877879                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                387520                       # number of misc regfile writes
-system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.tags.replacements           189327                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          472.259638                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            6803525                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           189662                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            35.871840                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     103705106000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   472.259638                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.922382                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.922382                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          335                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          318                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3           17                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.654297                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         15106665                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        15106665                       # Number of data accesses
-system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.ReadReq_hits::cpu1.data      3632818                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        3632818                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      2917516                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       2917516                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data        48925                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total        48925                       # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        78194                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        78194                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        70603                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        70603                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      6550334                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         6550334                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      6599259                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        6599259                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       216356                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       216356                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       400081                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       400081                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data        30281                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total        30281                       # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        18627                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        18627                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23453                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        23453                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       616437                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        616437                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       646718                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       646718                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   3492190500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   3492190500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  10142172955                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  10142172955                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    366644000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    366644000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    571781000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total    571781000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1485000                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1485000                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  13634363455                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  13634363455                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  13634363455                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  13634363455                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      3849174                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      3849174                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      3317597                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      3317597                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        79206                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total        79206                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        96821                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        96821                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        94056                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        94056                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      7166771                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      7166771                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      7245977                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      7245977                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.056208                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.056208                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.120594                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.120594                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.382307                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.382307                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.192386                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.192386                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.249351                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.249351                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.086013                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.086013                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.089252                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.089252                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16140.945941                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 16140.945941                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25350.298952                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 25350.298952                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19683.470231                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19683.470231                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24379.866115                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24379.866115                       # average StoreCondReq miss latency
+system.cpu1.cc_regfile_reads                190376100                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes                15518701                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads              209095836                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                386203                       # number of misc regfile writes
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.tags.replacements           187149                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          469.748213                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs           15687000                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           187502                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            83.663108                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle      93899473000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   469.748213                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.917477                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.917477                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          353                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          348                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.689453                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         32860265                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        32860265                       # Number of data accesses
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.ReadReq_hits::cpu1.data      9540081                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        9540081                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      5893568                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       5893568                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data        48959                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total        48959                       # number of SoftPFReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        77987                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        77987                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        70168                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        70168                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data     15433649                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total        15433649                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data     15482608                       # number of overall hits
+system.cpu1.dcache.overall_hits::total       15482608                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       215586                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       215586                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       396166                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       396166                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data        30156                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total        30156                       # number of SoftPFReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        18335                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        18335                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23429                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        23429                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       611752                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        611752                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       641908                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       641908                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   3514528500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   3514528500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   9742278459                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   9742278459                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    360181500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    360181500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    551095500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total    551095500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       166500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total       166500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  13256806959                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  13256806959                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  13256806959                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  13256806959                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      9755667                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      9755667                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      6289734                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      6289734                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        79115                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total        79115                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        96322                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        96322                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        93597                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        93597                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data     16045401                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total     16045401                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data     16124516                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total     16124516                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.022099                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.022099                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.062986                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.062986                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.381167                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.381167                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.190351                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.190351                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.250318                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.250318                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.038126                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.038126                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.039809                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.039809                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16302.211183                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 16302.211183                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24591.404762                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 24591.404762                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19644.477775                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19644.477775                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23521.938623                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23521.938623                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22118.016042                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 22118.016042                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21082.393648                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 21082.393648                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs          336                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets      1512378                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs               30                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets          40281                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs    11.200000                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets    37.545692                       # average number of cycles each access was blocked
-system.cpu1.dcache.writebacks::writebacks       189327                       # number of writebacks
-system.cpu1.dcache.writebacks::total           189327                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        79455                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total        79455                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       309049                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total       309049                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        13259                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        13259                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data       388504                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total       388504                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data       388504                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total       388504                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       136901                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       136901                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        91032                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        91032                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        28913                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total        28913                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5368                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5368                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23453                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        23453                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       227933                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       227933                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       256846                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       256846                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         3081                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total         3081                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2438                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2438                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         5519                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total         5519                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1914813500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1914813500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2474458965                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2474458965                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    498834500                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    498834500                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     96515500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     96515500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    548354000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    548354000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1459000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1459000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4389272465                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   4389272465                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4888106965                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   4888106965                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    442121000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    442121000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    442121000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total    442121000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035566                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035566                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027439                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027439                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.365035                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.365035                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.055443                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.055443                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.249351                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.249351                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.031804                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.031804                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035447                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.035447                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13986.848160                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13986.848160                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27182.298148                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27182.298148                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17252.948501                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17252.948501                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17979.787630                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17979.787630                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23380.974715                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23380.974715                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21670.230680                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 21670.230680                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20652.191527                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 20652.191527                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs          350                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets      1431753                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs               38                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets          39808                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs     9.210526                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets    35.966464                       # average number of cycles each access was blocked
+system.cpu1.dcache.writebacks::writebacks       187150                       # number of writebacks
+system.cpu1.dcache.writebacks::total           187150                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        79090                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total        79090                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       306284                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total       306284                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        13036                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        13036                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data       385374                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total       385374                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data       385374                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total       385374                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       136496                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       136496                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        89882                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        89882                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        28741                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total        28741                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5299                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5299                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23429                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        23429                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       226378                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       226378                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       255119                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       255119                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        14517                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total        14517                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        11855                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total        11855                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        26372                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total        26372                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1963325500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1963325500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2363104967                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2363104967                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    488593500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    488593500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     93065000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     93065000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    527670500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    527670500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       162500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       162500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4326430467                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   4326430467                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4815023967                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   4815023967                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2528366000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2528366000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   2528366000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   2528366000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.013991                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.013991                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014290                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.014290                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.363281                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.363281                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.055013                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.055013                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.250318                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.250318                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.014109                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.014109                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.015822                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.015822                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14383.758498                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14383.758498                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26291.192530                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26291.192530                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16999.878223                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16999.878223                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17562.747688                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17562.747688                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22522.109352                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22522.109352                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19256.853834                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19256.853834                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19031.275414                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19031.275414                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143499.188575                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143499.188575                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 80108.896539                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 80108.896539                       # average overall mshr uncacheable latency
-system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.cpu1.icache.tags.replacements           586343                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          499.448153                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs            7647462                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           586855                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            13.031263                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle      79062638500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.448153                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975485                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.975485                       # Average percentage of cache occupancy
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19111.532335                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19111.532335                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18873.639231                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18873.639231                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174165.874492                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174165.874492                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95873.123009                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95873.123009                       # average overall mshr uncacheable latency
+system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.cpu1.icache.tags.replacements           589510                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          499.449637                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs           42880129                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           590022                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            72.675475                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle      79021423000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.449637                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975488                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.975488                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          495                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3           17                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          496                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3           16                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         17099739                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        17099739                       # Number of data accesses
-system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.cpu1.icache.ReadReq_hits::cpu1.inst      7647462                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        7647462                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst      7647462                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         7647462                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst      7647462                       # number of overall hits
-system.cpu1.icache.overall_hits::total        7647462                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       608974                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       608974                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       608974                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        608974                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       608974                       # number of overall misses
-system.cpu1.icache.overall_misses::total       608974                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   5478938231                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   5478938231                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   5478938231                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   5478938231                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   5478938231                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   5478938231                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst      8256436                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total      8256436                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst      8256436                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total      8256436                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst      8256436                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total      8256436                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.073757                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.073757                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.073757                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.073757                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.073757                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.073757                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8996.998609                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total  8996.998609                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8996.998609                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total  8996.998609                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8996.998609                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total  8996.998609                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs       488402                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets           32                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs            41185                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              1                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs    11.858735                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets           32                       # average number of cycles each access was blocked
-system.cpu1.icache.writebacks::writebacks       586343                       # number of writebacks
-system.cpu1.icache.writebacks::total           586343                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        22107                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total        22107                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst        22107                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total        22107                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst        22107                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total        22107                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       586867                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       586867                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       586867                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       586867                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       586867                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       586867                       # number of overall MSHR misses
+system.cpu1.icache.tags.tag_accesses         87573930                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        87573930                       # Number of data accesses
+system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.cpu1.icache.ReadReq_hits::cpu1.inst     42880129                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       42880129                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     42880129                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        42880129                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     42880129                       # number of overall hits
+system.cpu1.icache.overall_hits::total       42880129                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       611823                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       611823                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       611823                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        611823                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       611823                       # number of overall misses
+system.cpu1.icache.overall_misses::total       611823                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   5700309356                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   5700309356                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   5700309356                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   5700309356                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   5700309356                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   5700309356                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     43491952                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     43491952                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     43491952                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     43491952                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     43491952                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     43491952                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.014067                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.014067                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.014067                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.014067                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.014067                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.014067                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9316.925575                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total  9316.925575                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9316.925575                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total  9316.925575                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9316.925575                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total  9316.925575                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs       502398                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs            42118                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs    11.928344                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu1.icache.writebacks::writebacks       589510                       # number of writebacks
+system.cpu1.icache.writebacks::total           589510                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        21797                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total        21797                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst        21797                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total        21797                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst        21797                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total        21797                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       590026                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       590026                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       590026                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       590026                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       590026                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       590026                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          101                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total          101                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          101                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total          101                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5026245111                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   5026245111                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5026245111                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   5026245111                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5026245111                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   5026245111                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9125500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      9125500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      9125500                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total      9125500                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.071080                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.071080                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.071080                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.071080                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.071080                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.071080                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8564.538662                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8564.538662                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8564.538662                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  8564.538662                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8564.538662                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  8564.538662                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90351.485149                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90351.485149                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90351.485149                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90351.485149                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.prefetcher.num_hwpf_issued       204963                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified       205672                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit          636                       # number of redundant prefetches already in prefetch queue
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5243631193                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   5243631193                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5243631193                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   5243631193                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5243631193                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   5243631193                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8747999                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      8747999                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      8747999                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total      8747999                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.013566                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.013566                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.013566                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.013566                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.013566                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.013566                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8887.118861                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8887.118861                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8887.118861                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  8887.118861                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8887.118861                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  8887.118861                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86613.851485                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86613.851485                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86613.851485                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86613.851485                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.cpu1.l2cache.prefetcher.num_hwpf_issued       195371                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified       196016                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit          576                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage        59720                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.tags.replacements           51812                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       15242.895875                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs           1332238                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs           66423                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs           20.056878                       # Average number of references to valid blocks.
+system.cpu1.l2cache.prefetcher.pfSpanPage        57640                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.cpu1.l2cache.tags.replacements           44567                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       14592.313259                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs            696647                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs           58721                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs           11.863677                       # Average number of references to valid blocks.
 system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 14783.108783                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     9.856539                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.176183                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   447.754371                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.902289                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000602                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000133                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.027329                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.930353                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022          977                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           32                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13602                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2           14                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          835                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          128                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           11                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           13                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            8                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          439                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         8705                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         4458                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.059631                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.001953                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.830200                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses        26728427                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses       26728427                       # Number of data accesses
-system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        16758                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         6223                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total         22981                       # number of ReadReq hits
-system.cpu1.l2cache.WritebackDirty_hits::writebacks       115160                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackDirty_hits::total       115160                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackClean_hits::writebacks       648098                       # number of WritebackClean hits
-system.cpu1.l2cache.WritebackClean_hits::total       648098                       # number of WritebackClean hits
-system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data            1                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::total            1                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data        27344                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total        27344                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       570840                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total       570840                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data       101859                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total       101859                       # number of ReadSharedReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        16758                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker         6223                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst       570840                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data       129203                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total         723024                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        16758                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker         6223                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst       570840                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data       129203                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total        723024                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          453                       # number of ReadReq misses
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-system.cpu1.l2cache.ReadReq_misses::total          702                       # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29938                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total        29938                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        23451                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total        23451                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            1                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::total            1                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data        34420                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total        34420                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        16015                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total        16015                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        69307                       # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total        69307                       # number of ReadSharedReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          453                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker          249                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst        16015                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data       103727                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total       120444                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          453                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker          249                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst        16015                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data       103727                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total       120444                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker      9914500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      5311000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total     15225500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data     63914000                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total     63914000                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data     34438500                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total     34438500                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1420000                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1420000                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1452051999                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total   1452051999                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    660407500                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::total    660407500                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1570017499                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1570017499                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker      9914500                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      5311000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst    660407500                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data   3022069498                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total   3697702498                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker      9914500                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      5311000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst    660407500                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data   3022069498                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total   3697702498                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        17211                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         6472                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total        23683                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::writebacks       115160                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::total       115160                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::writebacks       648098                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::total       648098                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        29938                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total        29938                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23452                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total        23452                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        61764                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total        61764                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       586855                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total       586855                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       171166                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total       171166                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        17211                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         6472                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst       586855                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data       232930                       # number of demand (read+write) accesses
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-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        17211                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         6472                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst       586855                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data       232930                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total       843468                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.026320                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.038473                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.029642                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.tags.occ_blocks::writebacks 14188.463877                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    10.825483                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.061403                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   390.962497                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.865995                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000661                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000126                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.023862                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.890644                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022          294                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           30                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13830                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            8                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          181                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          105                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            9                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           12                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            9                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         1785                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         8625                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3420                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.017944                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.001831                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.844116                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses        27388422                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses       27388422                       # Number of data accesses
+system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        17107                       # number of ReadReq hits
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+system.cpu1.l2cache.ReadReq_hits::total         23466                       # number of ReadReq hits
+system.cpu1.l2cache.WritebackDirty_hits::writebacks       113848                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackDirty_hits::total       113848                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackClean_hits::writebacks       650456                       # number of WritebackClean hits
+system.cpu1.l2cache.WritebackClean_hits::total       650456                       # number of WritebackClean hits
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+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       565476                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::total       565476                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data        99207                       # number of ReadSharedReq hits
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+system.cpu1.l2cache.demand_hits::cpu1.inst       565476                       # number of demand (read+write) hits
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+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        17107                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker         6359                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst       565476                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data       126115                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total        715057                       # number of overall hits
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+system.cpu1.l2cache.ReadReq_misses::total          782                       # number of ReadReq misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29684                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total        29684                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        23429                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total        23429                       # number of SCUpgradeReq misses
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+system.cpu1.l2cache.ReadExReq_misses::total        33964                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        24548                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::total        24548                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        71313                       # number of ReadSharedReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::total        71313                       # number of ReadSharedReq misses
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+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          487                       # number of overall misses
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+system.cpu1.l2cache.overall_misses::cpu1.inst        24548                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data       105277                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total       130607                       # number of overall misses
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     10682500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      6004000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::total     16686500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data     13705500                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total     13705500                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data     20860500                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total     20860500                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data       156500                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total       156500                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1388167997                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::total   1388167997                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    916991000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::total    916991000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1624894996                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1624894996                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     10682500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      6004000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.inst    916991000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.data   3013062993                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::total   3946740493                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     10682500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      6004000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst    916991000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.data   3013062993                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total   3946740493                       # number of overall miss cycles
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        17594                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         6654                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total        24248                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::writebacks       113848                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::total       113848                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::writebacks       650456                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::total       650456                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        29684                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total        29684                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23429                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total        23429                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        60872                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total        60872                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       590024                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::total       590024                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       170520                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::total       170520                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        17594                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         6654                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst       590024                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data       231392                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total       845664                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        17594                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         6654                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst       590024                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data       231392                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total       845664                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.027680                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.044334                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.032250                       # miss rate for ReadReq accesses
 system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.999957                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.999957                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.557283                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.557283                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.027290                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.027290                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.404911                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.404911                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.026320                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.038473                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.027290                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.445314                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.142796                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.026320                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.038473                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.027290                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.445314                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.142796                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21886.313466                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 21329.317269                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21688.746439                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  2134.878749                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  2134.878749                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  1468.530127                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  1468.530127                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data      1420000                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total      1420000                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 42186.287013                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 42186.287013                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 41236.809241                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 41236.809241                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22653.086975                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22653.086975                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21886.313466                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 21329.317269                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 41236.809241                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29134.839511                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 30700.595281                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21886.313466                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 21329.317269                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 41236.809241                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29134.839511                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 30700.595281                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs          122                       # number of cycles access was blocked
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.557958                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.557958                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.041605                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.041605                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.418209                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.418209                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.027680                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.044334                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.041605                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.454973                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.154443                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.027680                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.044334                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.041605                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.454973                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.154443                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21935.318275                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20352.542373                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21338.235294                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data   461.713381                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total   461.713381                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data   890.370908                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total   890.370908                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 40871.746467                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 40871.746467                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 37355.018739                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 37355.018739                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22785.396716                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22785.396716                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21935.318275                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20352.542373                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 37355.018739                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28620.334859                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 30218.445359                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21935.318275                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20352.542373                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 37355.018739                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28620.334859                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 30218.445359                       # average overall miss latency
+system.cpu1.l2cache.blocked_cycles::no_mshrs          266                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs               4                       # number of cycles access was blocked
+system.cpu1.l2cache.blocked::no_mshrs               7                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    30.500000                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs           38                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.l2cache.unused_prefetches             841                       # number of HardPF blocks evicted w/o reference
-system.cpu1.l2cache.writebacks::writebacks        37209                       # number of writebacks
-system.cpu1.l2cache.writebacks::total           37209                       # number of writebacks
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          554                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total          554                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            4                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            4                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data           67                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total           67                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            4                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data          621                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total          625                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            4                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data          621                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total          625                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          453                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          249                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total          702                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        27386                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total        27386                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29938                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29938                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23451                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23451                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        33866                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total        33866                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        16011                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        16011                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        69240                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        69240                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          453                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          249                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        16011                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data       103106                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total       119819                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          453                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          249                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        16011                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data       103106                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        27386                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total       147205                       # number of overall MSHR misses
+system.cpu1.l2cache.unused_prefetches             797                       # number of HardPF blocks evicted w/o reference
+system.cpu1.l2cache.writebacks::writebacks        31759                       # number of writebacks
+system.cpu1.l2cache.writebacks::total           31759                       # number of writebacks
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker            2                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_hits::total            2                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          426                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total          426                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            9                       # number of ReadCleanReq MSHR hits
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            9                       # number of ReadCleanReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data           74                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::total           74                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker            2                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            9                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.data          500                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total          511                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker            2                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            9                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.data          500                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::total          511                       # number of overall MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          487                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          293                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::total          780                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        24893                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total        24893                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29684                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29684                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23429                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23429                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        33538                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::total        33538                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        24539                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        24539                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        71239                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        71239                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          487                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          293                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        24539                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.data       104777                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::total       130096                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          487                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          293                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        24539                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.data       104777                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        24893                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::total       154989                       # number of overall MSHR misses
 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          101                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         3081                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         3182                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         2438                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         2438                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        14517                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        14618                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        11855                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        11855                       # number of WriteReq MSHR uncacheable
 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          101                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data         5519                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total         5620                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      7196500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3817000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     11013500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1234227220                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   1234227220                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    500545000                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    500545000                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    372231000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    372231000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1264000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1264000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1182076500                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1182076500                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    564261500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    564261500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1152682499                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1152682499                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      7196500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3817000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    564261500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2334758999                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total   2910033999                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      7196500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3817000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    564261500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2334758999                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1234227220                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total   4144261219                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8368000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    417428000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    425796000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      8368000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    417428000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    425796000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.026320                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.038473                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.029642                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        26372                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        26473                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      7760500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      4210000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     11970500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1022179654                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   1022179654                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    459449500                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    459449500                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    351583000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    351583000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       132500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       132500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1131738499                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1131738499                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    769613500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    769613500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1195688496                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1195688496                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      7760500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      4210000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    769613500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2327426995                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total   3109010995                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      7760500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      4210000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    769613500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2327426995                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1022179654                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total   4131190649                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      7990000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2412179500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2420169500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      7990000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   2412179500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   2420169500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.027680                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.044034                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.032168                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.999957                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.999957                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.548313                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.548313                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.027283                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.027283                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.404520                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.404520                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.026320                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.038473                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.027283                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.442648                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.142055                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.026320                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.038473                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.027283                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.442648                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.550959                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.550959                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.041590                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.041590                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.417775                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.417775                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.027680                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.044034                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.041590                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.452812                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.153839                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.027680                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.044034                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.041590                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.452812                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.174524                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15886.313466                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 15329.317269                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15688.746439                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45067.816403                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 45067.816403                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16719.386733                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16719.386733                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15872.713317                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15872.713317                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data      1264000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total      1264000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34904.520758                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34904.520758                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 35242.114796                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 35242.114796                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16647.638634                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16647.638634                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15886.313466                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 15329.317269                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 35242.114796                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22644.259296                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24286.916090                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15886.313466                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 15329.317269                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 35242.114796                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22644.259296                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45067.816403                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28152.992215                       # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 82851.485149                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135484.582928                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133813.953488                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 82851.485149                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75634.716434                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75764.412811                       # average overall mshr uncacheable latency
-system.cpu1.toL2Bus.snoop_filter.tot_requests      1659506                       # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests       839728                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        12423                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops       183739                       # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       180899                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         2840                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.cpu1.toL2Bus.trans_dist::ReadReq         31691                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp       827645                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq         2438                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp         2438                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty       153507                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean       660509                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict       108712                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq        33822                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq        71296                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41636                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp        86274                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           10                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           35                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq        68587                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp        66399                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq       586867                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq       252106                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq          259                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1760267                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       848480                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        14499                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        37693                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total          2660939                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     75086288                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     29768550                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        25888                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        68844                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total         104949570                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                     408766                       # Total snoops (count)
-system.cpu1.toL2Bus.snoopTraffic              5198376                       # Total snoop traffic (bytes)
-system.cpu1.toL2Bus.snoop_fanout::samples      1235773                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       0.169662                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.381410                       # Request fanout histogram
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.183275                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15935.318275                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14368.600683                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15346.794872                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41062.935524                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41062.935524                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15478.018461                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15478.018461                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15006.316958                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15006.316958                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33744.960910                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33744.960910                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31362.871348                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31362.871348                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16784.184169                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16784.184169                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15935.318275                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14368.600683                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31362.871348                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22213.147876                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23897.821570                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15935.318275                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14368.600683                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31362.871348                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22213.147876                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41062.935524                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26654.734523                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 79108.910891                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 166162.395812                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165560.918046                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 79108.910891                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 91467.446534                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 91420.296151                       # average overall mshr uncacheable latency
+system.cpu1.toL2Bus.snoop_filter.tot_requests      1661462                       # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests       840058                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        12360                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops       115637                       # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       106952                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         8685                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.cpu1.toL2Bus.trans_dist::ReadReq         43235                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp       842502                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq        11855                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp        11855                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty       146735                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean       662812                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict        29649                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq        30154                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq        72596                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41626                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp        86297                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           15                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           19                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq        68185                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp        65527                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq       590026                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq       275295                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq          251                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1769762                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       885483                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        14740                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        38125                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total          2708110                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     75491792                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     29665722                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        26616                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        70376                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total         105254506                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                     347103                       # Total snoops (count)
+system.cpu1.toL2Bus.snoopTraffic              4899396                       # Total snoop traffic (bytes)
+system.cpu1.toL2Bus.snoop_fanout::samples      1195777                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       0.122893                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.349738                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0           1028949     83.26%     83.26% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1            203984     16.51%     99.77% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2              2840      0.23%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0           1057509     88.44%     88.44% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1            129583     10.84%     99.27% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2              8685      0.73%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total       1235773                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy    1618384496                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total       1195777                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy    1635737987                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy     80334899                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy     81718473                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy    880530739                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy    885241795                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy    381648033                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy    395391898                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy      8035982                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy      8093984                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy     20499963                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy     20543974                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
+system.iobus.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
 system.iobus.trans_dist::ReadReq                31012                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               31012                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59421                       # Transaction distribution
@@ -2910,33 +2899,33 @@ system.iobus.pkt_size_system.bridge.master::total       162794
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321248                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321248                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2484042                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             40384000                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy             40381000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               112000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               112500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               328500                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               325000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer3.occupancy                31000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy                15500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy                16000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy                89500                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy                92000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer8.occupancy               582500                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy               575500                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy               22500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy               12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy               11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer14.occupancy               12000                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy               12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy               11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer16.occupancy               51500                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy               12000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer19.occupancy                2500                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
@@ -2944,32 +2933,32 @@ system.iobus.reqLayer20.occupancy                9000                       # La
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer21.occupancy               11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6095500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6080500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            33840000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            33803000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           187690100                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           187681355                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            84717000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer3.occupancy            36776000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
 system.iocache.tags.replacements                36458                       # number of replacements
-system.iocache.tags.tagsinuse               14.555462                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse               14.555440                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36474                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         255127474000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide    14.555462                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.909716                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.909716                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         255145986000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide    14.555440                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.909715                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.909715                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
 system.iocache.tags.tag_accesses               328284                       # Number of tag accesses
 system.iocache.tags.data_accesses              328284                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
+system.iocache.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
 system.iocache.ReadReq_misses::realview.ide          252                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              252                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
@@ -2978,14 +2967,14 @@ system.iocache.demand_misses::realview.ide        36476                       #
 system.iocache.demand_misses::total             36476                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide        36476                       # number of overall misses
 system.iocache.overall_misses::total            36476                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     32581877                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     32581877                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4303830223                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4303830223                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide   4336412100                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   4336412100                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide   4336412100                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   4336412100                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     32543877                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     32543877                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4303510478                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4303510478                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide   4336054355                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   4336054355                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide   4336054355                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   4336054355                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          252                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            252                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
@@ -3002,19 +2991,19 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 129293.162698                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 129293.162698                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118811.567552                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 118811.567552                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 118883.981248                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 118883.981248                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 118883.981248                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 118883.981248                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs            32                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 129142.369048                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 129142.369048                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118802.740669                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118802.740669                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 118874.173566                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 118874.173566                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 118874.173566                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 118874.173566                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs            36                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    6                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     5.333333                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs            6                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.writebacks::writebacks           36206                       # number of writebacks
 system.iocache.writebacks::total                36206                       # number of writebacks
@@ -3026,14 +3015,14 @@ system.iocache.demand_mshr_misses::realview.ide        36476
 system.iocache.demand_mshr_misses::total        36476                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide        36476                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total        36476                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     19981877                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     19981877                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2490259225                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2490259225                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   2510241102                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   2510241102                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   2510241102                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   2510241102                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     19943877                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     19943877                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2489987873                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2489987873                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   2509931750                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   2509931750                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   2509931750                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   2509931750                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -3042,620 +3031,618 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79293.162698                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 79293.162698                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68746.113764                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68746.113764                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 68818.979658                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 68818.979658                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 68818.979658                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 68818.979658                       # average overall mshr miss latency
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements                   132786                       # number of replacements
-system.l2c.tags.tagsinuse                63192.932289                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     445408                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   196622                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     2.265301                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   13716.070006                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    16.287927                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     1.059977                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     8086.686479                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2783.200527                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33654.604995                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     4.598228                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker     0.910717                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     1777.688460                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      638.769137                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  2513.055836                       # Average occupied blocks per requestor
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 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000016                       # Average percentage of cache occupancy
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 system.l2c.tags.occ_percent::cpu1.itb.walker     0.000014                       # Average percentage of cache occupancy
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-system.l2c.WritebackDirty_hits::writebacks       267222                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total          267222                       # number of WritebackDirty hits
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-system.l2c.UpgradeReq_misses::cpu0.data          9039                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          2774                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             11813                       # number of UpgradeReq misses
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+system.l2c.WritebackDirty_hits::writebacks       263091                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total          263091                       # number of WritebackDirty hits
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 system.l2c.demand_miss_latency::cpu0.itb.walker       241000                       # number of demand (read+write) miss cycles
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 system.l2c.overall_miss_latency::cpu0.itb.walker       241000                       # number of overall miss cycles
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-system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.367721                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.163898                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.743039                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.080000                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.051282                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.176265                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.101121                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.597254                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.527675                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.120930                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.036585                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.367721                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.289701                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.743039                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.080000                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.051282                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.176265                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.470205                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.597254                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.546955                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.120930                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.036585                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.367721                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.289701                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.743039                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.080000                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.051282                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.176265                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.470205                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.597254                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.546955                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1049.120478                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1057.858688                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  1051.172437                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  2330.781011                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   833.724570                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  1339.979285                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 102845.878908                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 84468.891403                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 94902.376412                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 99788.461538                       # average ReadSharedReq miss latency
+system.l2c.overall_miss_latency::cpu0.inst   1645029500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data   2038864000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  14426700203                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker       699000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.itb.walker        83500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    247656000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data    796596000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher    907627854                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    20066398057                       # number of overall miss cycles
+system.l2c.WritebackDirty_accesses::writebacks       263091                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total       263091                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data        42016                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         5397                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           47413                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data         2742                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data         2257                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          4999                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data        15297                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data         9784                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total            25081                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          260                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           89                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.inst        71216                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data        67501                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       178698                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker           71                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           18                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.inst        24536                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data        12815                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher        11666                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total       366870                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker          260                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker           89                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst           71216                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data           82798                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.l2cache.prefetcher       178698                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker           71                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker           18                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst           24536                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data           22599                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher        11666                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total              391951                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker          260                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker           89                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst          71216                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data          82798                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       178698                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker           71                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker           18                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst          24536                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data          22599                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher        11666                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total             391951                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.014494                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.102835                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.024550                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.018235                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.059814                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.037007                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.739622                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.846586                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.781348                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.115385                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.033708                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.275177                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.139139                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.735778                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.112676                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.055556                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.117949                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.084588                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.557432                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.466089                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.115385                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.033708                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.275177                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.250079                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.735778                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.112676                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.055556                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.117949                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.414487                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.557432                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.486262                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.115385                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.033708                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.275177                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.250079                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.735778                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.112676                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.055556                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.117949                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.414487                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.557432                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.486262                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 14554.187192                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2906.306306                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  9000.429553                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data        15000                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1851.851852                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  5405.405405                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 103715.264274                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 84305.927804                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 95511.583406                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker        96700                       # average ReadSharedReq miss latency
 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 80333.333333                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 82871.007997                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 91305.090241                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 109848.935181                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 90833.333333                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker        93500                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 86631.821403                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 94758.558559                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 134674.112751                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 106528.329310                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 99788.461538                       # average overall miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 83942.924937                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 92145.389693                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 109723.766014                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker        87375                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker        83500                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 85575.673808                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90673.431734                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 139570.637244                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 106405.239698                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker        96700                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu0.itb.walker 80333.333333                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 82871.007997                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 97727.640913                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 109848.935181                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 90833.333333                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker        93500                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 86631.821403                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 85616.783920                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 134674.112751                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 105307.520086                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 99788.461538                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 83942.924937                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 98467.304163                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 109723.766014                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        87375                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker        83500                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 85575.673808                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 85042.809864                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 139570.637244                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 105285.129188                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker        96700                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.itb.walker 80333.333333                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 82871.007997                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 97727.640913                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 109848.935181                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 90833.333333                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker        93500                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 86631.821403                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 85616.783920                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 134674.112751                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 105307.520086                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.l2c.overall_avg_miss_latency::cpu0.inst 83942.924937                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 98467.304163                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 109723.766014                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        87375                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker        83500                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 85575.673808                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 85042.809864                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 139570.637244                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 105285.129188                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs               188                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        5                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs     37.600000                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.writebacks::writebacks              103831                       # number of writebacks
-system.l2c.writebacks::total                   103831                       # number of writebacks
-system.l2c.ReadSharedReq_mshr_hits::cpu0.inst           10                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.inst           16                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.data            1                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total           27                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst             10                       # number of demand (read+write) MSHR hits
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-system.l2c.ReadReq_mshr_uncacheable_latency::total   6355765000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   4005299000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      6171000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2150864000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   6354900500                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    192566500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5794675500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      6549000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    361974000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   6355765000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   4005299000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      6171000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   2150864000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   6354900500                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.217723                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.506574                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.251383                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.241583                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.574124                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.391763                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.746064                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.868028                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.794306                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.120930                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.036585                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.367534                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.163898                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.743039                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.080000                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.051282                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.175265                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.101029                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.597254                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.527594                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.120930                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.036585                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.367534                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.289701                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.743039                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.080000                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.051282                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.175265                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.470157                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.597254                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.546879                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.120930                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.036585                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.367534                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.289701                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.743039                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.080000                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.051282                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.175265                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.470157                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.597254                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.546879                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23764.907623                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22719.178082                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23519.343097                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 25797.856049                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24906.494523                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25207.923356                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 92845.835931                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74468.778507                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 84902.303213                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 89788.461538                       # average ReadSharedReq mshr miss latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.014494                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.102835                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.024550                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.018235                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.059814                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.037007                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.739622                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.846586                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.781348                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.115385                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.033708                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.275149                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.139139                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.735778                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.112676                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.055556                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.117868                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.084588                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.557432                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.466078                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.115385                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.033708                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.275149                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.250079                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.735778                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.112676                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.055556                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.117868                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.414487                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.557432                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.486252                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.115385                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.033708                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.275149                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.250079                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.735778                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.112676                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.055556                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.117868                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.414487                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.557432                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.486252                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23267.651888                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22047.747748                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22685.996564                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        26990                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23811.111111                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24670.270270                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 93715.264274                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74305.927804                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 85511.583406                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker        86700                       # average ReadSharedReq mshr miss latency
 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 72881.160118                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 81305.090241                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99848.908954                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 80833.333333                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker        83500                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76729.510335                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 84795.762849                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124673.871401                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 96534.502071                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 89788.461538                       # average overall mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 73944.858586                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 82145.336563                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99723.724266                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker        77375                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker        73500                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 75611.687414                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80673.431734                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 129570.407043                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 96406.532990                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        86700                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72881.160118                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 87727.616996                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99848.908954                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80833.333333                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        83500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76729.510335                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75619.911850                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124673.871401                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 95312.867617                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 89788.461538                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73944.858586                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 88467.280064                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99723.724266                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        77375                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        73500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75611.687414                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75042.809864                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 129570.407043                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 95286.265989                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        86700                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72881.160118                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 87727.616996                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99848.908954                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80833.333333                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        83500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76729.510335                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75619.911850                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124673.871401                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 95312.867617                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73944.858586                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 88467.280064                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99723.724266                       # average overall mshr miss latency
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+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        73500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75611.687414                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75042.809864                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 129570.407043                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 95286.265989                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64124.708625                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182383.088883                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64841.584158                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117600.389864                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167459.688043                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 196956.087726                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 61099.009901                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 148192.365991                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167436.910471                       # average ReadReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64124.708625                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96220.306195                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64841.584158                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65622.552574                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 92322.603605                       # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests        523570                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       298445                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 101739.966470                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 61099.009901                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81567.901703                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 92312.727880                       # average overall mshr uncacheable latency
+system.membus.snoop_filter.tot_requests        505464                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests       284514                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests          572                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadReq               37954                       # Transaction distribution
-system.membus.trans_dist::ReadResp             212485                       # Transaction distribution
-system.membus.trans_dist::WriteReq              30889                       # Transaction distribution
-system.membus.trans_dist::WriteResp             30889                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       140037                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            17084                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            74884                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          40573                       # Transaction distribution
+system.membus.trans_dist::ReadResp             209195                       # Transaction distribution
+system.membus.trans_dist::WriteReq              30887                       # Transaction distribution
+system.membus.trans_dist::WriteResp             30887                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       137421                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            16935                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            65286                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          38770                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             40212                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            20363                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        174532                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq            2                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             39566                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            19573                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        171242                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107914                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           36                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13624                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       661033                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       782607                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13620                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       638853                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       760423                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72949                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total        72949                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 855556                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 833372                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162794                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          288                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27248                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     19150328                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     19340658                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27240                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18721784                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     18912106                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2318144                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2318144                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                21658802                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           122046                       # Total snoops (count)
+system.membus.pkt_size::total                21230250                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           123250                       # Total snoops (count)
 system.membus.snoopTraffic                      36480                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            435271                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.011878                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.108336                       # Request fanout histogram
+system.membus.snoop_fanout::samples            419934                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.012350                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.110440                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  430101     98.81%     98.81% # Request fanout histogram
-system.membus.snoop_fanout::1                    5170      1.19%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  414748     98.77%     98.77% # Request fanout histogram
+system.membus.snoop_fanout::1                    5186      1.23%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              435271                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            81633500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              419934                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            81570000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               24500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            11523000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            11357000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          1022470046                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           987545766                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1120816043                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1099710840                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy            1359381                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy            1385881                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
 system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
 system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
 system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
 system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -3687,81 +3674,81 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
 system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests      1014149                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests       548985                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests       155175                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops          21000                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops        20112                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops          888                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825947406000                       # Cumulative time (in ticks) in various power states
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.snoop_filter.tot_requests      1051858                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests       557134                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests       188416                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops          28173                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops        27109                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops         1064                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826111083000                       # Cumulative time (in ticks) in various power states
 system.toL2Bus.trans_dist::ReadReq              37957                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            486750                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             30889                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            30889                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty       371053                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict          122899                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          109975                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         43571                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         153546                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq           35                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp           35                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq            50842                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp           50842                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq       448796                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq         4596                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1244094                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       315957                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               1560051                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     34491784                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      5674154                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               40165938                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          382861                       # Total snoops (count)
-system.toL2Bus.snoopTraffic                  15835212                       # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples           859470                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.375184                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.486300                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadResp            525508                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             30887                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            30887                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty       364306                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          131438                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          111511                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         43584                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         155095                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq           19                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp           19                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq            50612                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp           50612                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       487554                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq         4612                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1267106                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       367019                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               1634125                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     36291756                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      5905726                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               42197482                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          390713                       # Total snoops (count)
+system.toL2Bus.snoopTraffic                  15836620                       # Total snoop traffic (bytes)
+system.toL2Bus.snoop_fanout::samples           903686                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.404217                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.493133                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                 537899     62.58%     62.58% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 320683     37.31%     99.90% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                    888      0.10%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                 539465     59.70%     59.70% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 363157     40.19%     99.88% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                   1064      0.12%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total             859470                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy          886309294                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total             903686                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy          901600874                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
 system.toL2Bus.snoopLayer0.occupancy           356119                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         648979933                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy         679704118                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         232794950                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         260937433                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    1839                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                    1856                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2759                       # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce                    2757                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
index f6937a594..fdcb3cf4d 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
@@ -1,122 +1,122 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.832894                       # Number of seconds simulated
-sim_ticks                                2832894126500                       # Number of ticks simulated
-final_tick                               2832894126500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.827853                       # Number of seconds simulated
+sim_ticks                                2827853096000                       # Number of ticks simulated
+final_tick                               2827853096000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 136161                       # Simulator instruction rate (inst/s)
-host_op_rate                                   165152                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3410188815                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 579068                       # Number of bytes of host memory used
-host_seconds                                   830.71                       # Real time elapsed on the host
-sim_insts                                   113111333                       # Number of instructions simulated
-sim_ops                                     137193850                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  94322                       # Simulator instruction rate (inst/s)
+host_op_rate                                   114411                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2357194570                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 589152                       # Number of bytes of host memory used
+host_seconds                                  1199.67                       # Real time elapsed on the host
+sim_insts                                   113155640                       # Number of instructions simulated
+sim_ops                                     137255479                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.dtb.walker         1344                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker          448                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1321536                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9400296                       # Number of bytes read from this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.dtb.walker         1024                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker          384                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1322240                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9790440                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10724584                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1321536                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1321536                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8031104                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             11115048                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1322240                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1322240                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8407168                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8048628                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker           21                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            7                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              22896                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             147400                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           8424692                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker           16                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker            6                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              22907                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             153496                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                170339                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          125486                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                176440                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          131362                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               129867                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker            474                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker            158                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               466497                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3318266                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               135743                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker            362                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker            136                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               467577                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3462146                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              339                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3785734                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          466497                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             466497                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2834947                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data                6186                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2841133                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2834947                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           474                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker           158                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              466497                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3324452                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                 3930561                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          467577                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             467577                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2972986                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data                6197                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2979183                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2972986                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           362                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker           136                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              467577                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3468343                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             339                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6626867                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        170340                       # Number of read requests accepted
-system.physmem.writeReqs                       129867                       # Number of write requests accepted
-system.physmem.readBursts                      170340                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     129867                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10892352                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      9408                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8061056                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10724648                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8048628                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      147                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    3887                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bw_total::total                6909744                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        176441                       # Number of read requests accepted
+system.physmem.writeReqs                       135743                       # Number of write requests accepted
+system.physmem.readBursts                      176441                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     135743                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 11282432                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      9792                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8437824                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  11115112                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8424692                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      153                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    3886                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11036                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10507                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               10862                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               11068                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               13101                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10327                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               10639                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10985                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10460                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10167                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10435                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9511                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               9930                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10756                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10401                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10008                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8291                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7865                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8399                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8558                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7751                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7713                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7781                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8111                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7871                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7662                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7844                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7196                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7582                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8119                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7846                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7365                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               11743                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               11227                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               11041                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               10652                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               13485                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               11002                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               11432                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               11844                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10383                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10947                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10471                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9569                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10361                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              11110                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10361                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10660                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8764                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                8604                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8676                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8310                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                8074                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                8230                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8228                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8800                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7938                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                8472                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               8080                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7388                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               8035                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8487                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7854                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7901                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          17                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2832893894500                       # Total gap between requests
+system.physmem.numWrRetry                           4                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2827852861000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     542                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                    2996                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  166788                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  172889                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 125486                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    150867                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     16439                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      2150                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       721                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 131362                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    155219                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     17999                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      2225                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       829                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         6                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
@@ -160,164 +160,164 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1883                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2891                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6675                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6069                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     7147                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6554                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6489                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6585                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7283                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7048                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7591                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8460                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7511                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7926                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     8975                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7507                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7129                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7208                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1140                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      304                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      257                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      207                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      209                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      194                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      202                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      174                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      169                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      132                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      146                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      130                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      137                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      122                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      108                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      113                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      138                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       79                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      117                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       55                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       81                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       48                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       79                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       69                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       54                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       35                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       56                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        62108                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      305.167515                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     180.813202                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     324.494619                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          23016     37.06%     37.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        15104     24.32%     61.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6524     10.50%     71.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3665      5.90%     77.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2528      4.07%     81.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1637      2.64%     84.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1479      2.38%     86.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1102      1.77%     88.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7053     11.36%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          62108                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6142                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        27.706936                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      569.623530                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6141     99.98%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6142                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6142                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.507001                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.506831                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       14.607971                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5435     88.49%     88.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             129      2.10%     90.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              31      0.50%     91.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              49      0.80%     91.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              32      0.52%     92.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              17      0.28%     92.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              48      0.78%     93.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              14      0.23%     93.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             140      2.28%     95.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              11      0.18%     96.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               8      0.13%     96.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               8      0.13%     96.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67              65      1.06%     97.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               1      0.02%     97.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              21      0.34%     97.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              93      1.51%     99.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               3      0.05%     99.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.02%     99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.02%     99.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               1      0.02%     99.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             2      0.03%     99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             3      0.05%     99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.02%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            11      0.18%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.02%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.02%     99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.03%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             7      0.11%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             1      0.02%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.02%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             1      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             2      0.03%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-211             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6142                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2108320500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5299439250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    850965000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12387.82                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::15                     2095                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2964                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5951                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6509                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6942                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6801                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7294                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7733                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     8218                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     8271                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     9582                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     9943                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     8295                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     8200                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     8031                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7326                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7196                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7152                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      364                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      327                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      266                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      134                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      133                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      125                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      139                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      101                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      130                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      109                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      104                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      129                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                       98                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      150                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      136                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       91                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       90                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       92                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       70                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       70                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       83                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       59                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       64                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       79                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       57                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       31                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       26                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       28                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       32                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       12                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       10                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        64990                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      303.434251                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     179.571710                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     325.070143                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          24166     37.18%     37.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        15993     24.61%     61.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6821     10.50%     72.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3792      5.83%     78.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2758      4.24%     82.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1633      2.51%     84.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1086      1.67%     86.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1085      1.67%     88.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7656     11.78%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          64990                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6662                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        26.461423                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      559.657587                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6661     99.98%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::45056-47103            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6662                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6662                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        19.790003                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.288798                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       12.351415                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5875     88.19%     88.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              70      1.05%     89.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              75      1.13%     90.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              36      0.54%     90.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             259      3.89%     94.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              62      0.93%     95.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              25      0.38%     96.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              19      0.29%     96.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51               9      0.14%     96.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               7      0.11%     96.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               3      0.05%     96.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               4      0.06%     96.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             160      2.40%     99.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               6      0.09%     99.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               8      0.12%     99.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               2      0.03%     99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               6      0.09%     99.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.02%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               3      0.05%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.02%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.02%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111            10      0.15%     99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.02%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.02%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             8      0.12%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.02%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             1      0.02%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.02%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             1      0.02%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             2      0.03%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             2      0.03%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6662                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2116192000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5421592000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    881440000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12004.17                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31137.82                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           3.84                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.85                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        3.79                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.84                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  30754.17                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           3.99                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.98                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        3.93                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.98                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.42                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     139937                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     94101                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.22                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  74.70                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9436468.49                       # Average gap between requests
-system.physmem.pageHitRate                      79.02                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  243454680                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  132837375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 690495000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                417759120                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           185030401920                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            83647548450                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1626357251250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1896519747795                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.465335                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2705450093000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     94596320000                       # Time in different power states
+system.physmem.avgWrQLen                        23.03                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     145153                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     97985                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.34                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  74.31                       # Row buffer hit rate for writes
+system.physmem.avgGap                      9058288.90                       # Average gap between requests
+system.physmem.pageHitRate                      78.90                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  256087440                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  139730250                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 720922800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                438605280                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           184701363600                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            81077227785                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1625589296250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1892923233405                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.386141                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2704185411500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     94428100000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     32840757000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     29235954750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  226081800                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  123358125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 637002600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                398422800                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           185030401920                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            82216233135                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1627612791000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1896244291380                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.368099                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2707556632500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     94596320000                       # Time in different power states
+system.physmem_1.actEnergy                  235236960                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  128353500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 654115800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                415724400                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           184701363600                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            80292349755                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1626277785750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1892704929765                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.308944                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2705344853000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     94428100000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     30741160500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     28080129500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
 system.realview.nvmem.bytes_read::cpu.inst          112                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           112                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu.inst          112                       # Number of instructions bytes read from this memory
@@ -330,30 +330,30 @@ system.realview.nvmem.bw_inst_read::cpu.inst           40
 system.realview.nvmem.bw_inst_read::total           40                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.inst           40                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total              40                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups                46812529                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          23980713                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1174980                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             29461889                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                13525990                       # Number of BTB hits
+system.cpu.branchPred.lookups                46859222                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          23995015                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1174256                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             29489294                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                13535968                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             45.910125                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                11726513                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              34925                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups         7916092                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits            7770128                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses           145964                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted        60126                       # Number of mispredicted indirect branches.
+system.cpu.branchPred.BTBHitPct             45.901296                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                11745095                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              35189                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         7931554                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits            7786304                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses           145250                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted        60170                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -383,82 +383,83 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks                     72186                       # Table walker walks requested
-system.cpu.dtb.walker.walksShort                72186                       # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walksShortTerminationLevel::Level1        29334                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksShortTerminationLevel::Level2        23181                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore        19671                       # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples        52515                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean   467.713986                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev  2821.743931                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-8191        51203     97.50%     97.50% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::8192-16383          905      1.72%     99.22% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::16384-24575          322      0.61%     99.84% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::24576-32767           40      0.08%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::32768-40959           18      0.03%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::40960-49151           21      0.04%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::49152-57343            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::57344-65535            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.walks                     72426                       # Table walker walks requested
+system.cpu.dtb.walker.walksShort                72426                       # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1        29716                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2        23400                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore        19310                       # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples        53116                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean   407.485503                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev  2469.018740                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-8191        51917     97.74%     97.74% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::8192-16383          937      1.76%     99.51% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::16384-24575          190      0.36%     99.86% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::24576-32767           37      0.07%     99.93% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::32768-40959           15      0.03%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::40960-49151           16      0.03%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::49152-57343            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::57344-65535            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::65536-73727            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::81920-90111            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::90112-98303            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total        52515                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples        17658                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 12583.333333                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 10066.135653                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev  8522.119991                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-32767        17438     98.75%     98.75% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::32768-65535          214      1.21%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-163839            4      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::163840-196607            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-360447            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total        17658                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 131358619316                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean     0.629965                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev     0.490082                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0-1  131298865316     99.95%     99.95% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::2-3      40695500      0.03%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::4-5       8747000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::6-7       6751500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::8-9       1053500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::10-11       584000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::12-13      1412000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::14-15       501000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walkWaitTime::total        53116                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples        17396                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean  9637.387905                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean  7803.906851                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev  6813.601039                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-16383        15561     89.45%     89.45% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::16384-32767         1740     10.00%     99.45% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::32768-49151           86      0.49%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::49152-65535            2      0.01%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-81919            1      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::81920-98303            4      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::147456-163839            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::245760-262143            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total        17396                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 117727604724                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean     0.629848                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev     0.489627                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1  117677681224     99.96%     99.96% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3      34838500      0.03%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5       7318000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7       4585500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9        935500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::10-11       533500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::12-13      1306000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::14-15       397000      0.00%    100.00% # Table walker pending requests distribution
 system.cpu.dtb.walker.walksPending::16-17         9500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 131358619316                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K          6349     82.25%     82.25% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::1M          1370     17.75%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total         7719                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        72186                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walksPending::total 117727604724                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K          6471     81.85%     81.85% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::1M          1435     18.15%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total         7906                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        72426                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total        72186                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7719                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total        72426                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7906                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7719                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total        79905                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7906                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total        80332                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     25413003                       # DTB read hits
-system.cpu.dtb.read_misses                      62542                       # DTB read misses
-system.cpu.dtb.write_hits                    19866296                       # DTB write hits
-system.cpu.dtb.write_misses                      9644                       # DTB write misses
+system.cpu.dtb.read_hits                     25423365                       # DTB read hits
+system.cpu.dtb.read_misses                      62664                       # DTB read misses
+system.cpu.dtb.write_hits                    19868926                       # DTB write hits
+system.cpu.dtb.write_misses                      9762                       # DTB write misses
 system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     4253                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                       366                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   2075                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries                     4289                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                       358                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                   2236                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                      1321                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 25475545                       # DTB read accesses
-system.cpu.dtb.write_accesses                19875940                       # DTB write accesses
+system.cpu.dtb.perms_faults                      1258                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 25486029                       # DTB read accesses
+system.cpu.dtb.write_accesses                19878688                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          45279299                       # DTB hits
-system.cpu.dtb.misses                           72186                       # DTB misses
-system.cpu.dtb.accesses                      45351485                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.hits                          45292291                       # DTB hits
+system.cpu.dtb.misses                           72426                       # DTB misses
+system.cpu.dtb.accesses                      45364717                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -488,59 +489,58 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks                     12817                       # Table walker walks requested
-system.cpu.itb.walker.walksShort                12817                       # Table walker walks initiated with short descriptors
-system.cpu.itb.walker.walksShortTerminationLevel::Level1         3407                       # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksShortTerminationLevel::Level2         7692                       # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksSquashedBefore         1718                       # Table walks squashed before starting
-system.cpu.itb.walker.walkWaitTime::samples        11099                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::mean   742.229030                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::stdev  3116.397220                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0-4095        10521     94.79%     94.79% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::4096-8191          119      1.07%     95.86% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::8192-12287          227      2.05%     97.91% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::12288-16383          123      1.11%     99.02% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::16384-20479           47      0.42%     99.44% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::20480-24575           47      0.42%     99.86% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::24576-28671            3      0.03%     99.89% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::28672-32767            6      0.05%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::32768-36863            1      0.01%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::36864-40959            2      0.02%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::40960-45055            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::53248-57343            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::57344-61439            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total        11099                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples         5040                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 12026.488095                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean  9684.197840                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev  7608.176186                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-16383         4071     80.77%     80.77% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::16384-32767          955     18.95%     99.72% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::32768-49151           11      0.22%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::49152-65535            1      0.02%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-147455            2      0.04%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total         5040                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples  23984374916                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::mean     0.642154                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::stdev     0.479545                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0      8584682500     35.79%     35.79% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::1     15397812416     64.20%     99.99% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::2         1792000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::3           88000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total  23984374916                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K          2987     89.92%     89.92% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::1M           335     10.08%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total         3322                       # Table walker page sizes translated
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.walks                     12855                       # Table walker walks requested
+system.cpu.itb.walker.walksShort                12855                       # Table walker walks initiated with short descriptors
+system.cpu.itb.walker.walksShortTerminationLevel::Level1         3590                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksShortTerminationLevel::Level2         7693                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksSquashedBefore         1572                       # Table walks squashed before starting
+system.cpu.itb.walker.walkWaitTime::samples        11283                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean   605.778605                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev  2805.757421                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-8191        10907     96.67%     96.67% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::8192-16383          327      2.90%     99.57% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::16384-24575           40      0.35%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::24576-32767            5      0.04%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::40960-49151            1      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::57344-65535            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::65536-73727            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::81920-90111            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total        11283                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples         4887                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean  8961.019030                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean  7007.167188                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev  7172.888707                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-8191         3327     68.08%     68.08% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::8192-16383          829     16.96%     85.04% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::16384-24575          682     13.96%     99.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::24576-32767           38      0.78%     99.77% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::32768-40959            1      0.02%     99.80% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::40960-49151            7      0.14%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::49152-57343            1      0.02%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::81920-90111            2      0.04%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total         4887                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples  23237381212                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean     0.774797                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev     0.417824                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0      5234024500     22.52%     22.52% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1     18002578212     77.47%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::2          696500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::3           46500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::4           35500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total  23237381212                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K          2980     89.89%     89.89% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::1M           335     10.11%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total         3315                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst        12817                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total        12817                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst        12855                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total        12855                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3322                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total         3322                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total        16139                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                     65982481                       # ITB inst hits
-system.cpu.itb.inst_misses                      12817                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3315                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total         3315                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total        16170                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                     66060204                       # ITB inst hits
+system.cpu.itb.inst_misses                      12855                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -549,112 +549,113 @@ system.cpu.itb.flush_tlb                           64                       # Nu
 system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     3021                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     3013                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                      2147                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                      2175                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 65995298                       # ITB inst accesses
-system.cpu.itb.hits                          65982481                       # DTB hits
-system.cpu.itb.misses                           12817                       # DTB misses
-system.cpu.itb.accesses                      65995298                       # DTB accesses
-system.cpu.numPwrStateTransitions                6074                       # Number of power state transitions
-system.cpu.pwrStateClkGateDist::samples          3037                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::mean     886948130.312150                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::stdev    17421700028.084686                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::underflows         2966     97.66%     97.66% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1000-5e+10           65      2.14%     99.80% # Distribution of time spent in the clock gated state
+system.cpu.itb.inst_accesses                 66073059                       # ITB inst accesses
+system.cpu.itb.hits                          66060204                       # DTB hits
+system.cpu.itb.misses                           12855                       # DTB misses
+system.cpu.itb.accesses                      66073059                       # DTB accesses
+system.cpu.numPwrStateTransitions                6076                       # Number of power state transitions
+system.cpu.pwrStateClkGateDist::samples          3038                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean     887319797.866359                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev    17420812025.908409                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::underflows         2966     97.63%     97.63% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1000-5e+10           66      2.17%     99.80% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::1.5e+11-2e+11            1      0.03%     99.84% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::2e+11-2.5e+11            2      0.07%     99.90% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::2e+11-2.5e+11            1      0.03%     99.87% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::2.5e+11-3e+11            1      0.03%     99.90% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::4.5e+11-5e+11            3      0.10%    100.00% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::max_value 499972891000                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::total            3037                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateResidencyTicks::ON    139232654742                       # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::CLK_GATED 2693661471758                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                        278465363                       # number of cpu cycles simulated
+system.cpu.pwrStateClkGateDist::max_value 499973328096                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::total            3038                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateResidencyTicks::ON    132175550082                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 2695677545918                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                        264351157                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          104979858                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      184015649                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    46812529                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           33022631                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     161497089                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 6057652                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     189263                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                 8972                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        337056                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       558097                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          172                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  65981271                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               1027864                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    6246                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          270599333                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.829251                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.216918                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          105007140                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      184198118                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    46859222                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           33067367                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     149125653                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 6062128                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     177509                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                 8064                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        342285                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       500656                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          149                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  66059105                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1061874                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    6140                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          258192520                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.869926                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.232240                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                171686790     63.45%     63.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 29154260     10.77%     74.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 14034299      5.19%     79.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 55723984     20.59%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                159207105     61.66%     61.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 29153243     11.29%     72.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 14041371      5.44%     78.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 55790801     21.61%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            270599333                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.168109                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.660821                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 77964907                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             121895477                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  64303176                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               3866825                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                2568948                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3406986                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                467982                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              156982730                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               3511045                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                2568948                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 83721940                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                11815597                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       76560081                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  62413108                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              33519659                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              146432544                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts                918349                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents                465966                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  65322                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                  18586                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               30762818                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           150226924                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             676971311                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        163962292                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             10893                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             141750491                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  8476427                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            2839737                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        2644396                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13885386                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             26339908                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            21214343                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1703941                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2126584                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  143224778                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2118002                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 143047064                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            260478                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         8148926                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     14278560                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         121950                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     270599333                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.528631                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.865147                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            258192520                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.177261                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.696793                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 78121728                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             109293057                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  64347286                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               3858820                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                2571629                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3404933                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                467397                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              157054266                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               3508469                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                2571629                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 83876272                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                10707182                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       75777880                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  62454434                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              22805123                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              146493829                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts                914752                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents                447933                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  65579                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                  19295                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               20059867                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           150297562                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             677265731                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        164029738                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             11047                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             141819290                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                  8478266                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            2841903                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        2646616                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13881588                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             26350743                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            21216202                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1694356                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2155521                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  143287156                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2116266                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 143106706                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            261772                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         8147939                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     14286308                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         122067                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     258192520                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.554264                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.878016                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           182394036     67.40%     67.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            45259787     16.73%     84.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            31866202     11.78%     95.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            10262392      3.79%     99.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4              816883      0.30%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           169987358     65.84%     65.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            45210540     17.51%     83.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            31907168     12.36%     95.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            10268019      3.98%     99.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4              819402      0.32%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::5                  33      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
@@ -662,44 +663,44 @@ system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Nu
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       270599333                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       258192520                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 7342152     32.76%     32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     32      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                5622313     25.09%     57.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               9444091     42.14%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 7338606     32.76%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     32      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                5623411     25.10%     57.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               9440852     42.14%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              2337      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              95850690     67.01%     67.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               114288      0.08%     67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              95896760     67.01%     67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               115009      0.08%     67.09% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.09% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.09% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.09% # Type of FU issued
@@ -723,99 +724,99 @@ system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.09% # Ty
 system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.09% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.09% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc           8577      0.01%     67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             26130891     18.27%     85.36% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            20940281     14.64%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc           8592      0.01%     67.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.10% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             26141404     18.27%     85.37% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            20942604     14.63%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              143047064                       # Type of FU issued
-system.cpu.iq.rate                           0.513698                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    22408588                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.156652                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          579326888                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         153497201                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    139997351                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               35639                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              13116                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses        11369                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              165429916                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                   23399                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           323958                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              143106706                       # Type of FU issued
+system.cpu.iq.rate                           0.541351                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    22402901                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.156547                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          567034934                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         153556562                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    140052264                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               35671                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              13288                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses        11499                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              165483986                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                   23284                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           324130                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      1433781                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses          712                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        18665                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       622043                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1434023                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses          698                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        18538                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       619510                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        88844                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          6344                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        88631                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          6598                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                2568948                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 1241907                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                544667                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           145523405                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                2571629                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  994929                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                316385                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           145584227                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              26339908                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             21214343                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1094304                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  17849                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                508298                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          18665                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         277238                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       471000                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               748238                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             142148555                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              25736254                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            826428                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts              26350743                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             21216202                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1093451                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  17658                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                280514                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          18538                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         277676                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       470698                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               748374                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             142207045                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              25746206                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            827350                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        180625                       # number of nop insts executed
-system.cpu.iew.exec_refs                     46564673                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 26492434                       # Number of branches executed
-system.cpu.iew.exec_stores                   20828419                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.510471                       # Inst execution rate
-system.cpu.iew.wb_sent                      141779361                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     140008720                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  63240555                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  95712709                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       0.502787                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.660733                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts         7366290                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1996052                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            715102                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    267708008                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.513054                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.118068                       # Number of insts commited each cycle
+system.cpu.iew.exec_nop                        180805                       # number of nop insts executed
+system.cpu.iew.exec_refs                     46576895                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 26509940                       # Number of branches executed
+system.cpu.iew.exec_stores                   20830689                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.537948                       # Inst execution rate
+system.cpu.iew.wb_sent                      141837731                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     140063763                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  63261975                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  95760288                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       0.529840                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.660628                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts         7362260                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1994199                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            714821                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    255299551                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.538232                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.139550                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    194252968     72.56%     72.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     43305040     16.18%     88.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     15457612      5.77%     94.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      4371808      1.63%     96.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      6428406      2.40%     98.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1610065      0.60%     99.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       797962      0.30%     99.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       411830      0.15%     99.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      1072317      0.40%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    181839086     71.23%     71.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     43295063     16.96%     88.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     15470047      6.06%     94.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      4367483      1.71%     95.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      6400805      2.51%     98.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1643674      0.64%     99.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       799411      0.31%     99.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       417134      0.16%     99.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      1066848      0.42%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    267708008                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            113266238                       # Number of instructions committed
-system.cpu.commit.committedOps              137348755                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    255299551                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            113310545                       # Number of instructions committed
+system.cpu.commit.committedOps              137410384                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       45498427                       # Number of memory references committed
-system.cpu.commit.loads                      24906127                       # Number of loads committed
-system.cpu.commit.membars                      814995                       # Number of memory barriers committed
-system.cpu.commit.branches                   26026646                       # Number of branches committed
-system.cpu.commit.fp_insts                      11364                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 120175202                       # Number of committed integer instructions.
-system.cpu.commit.function_calls              4885014                       # Number of function calls committed.
+system.cpu.commit.refs                       45513412                       # Number of memory references committed
+system.cpu.commit.loads                      24916720                       # Number of loads committed
+system.cpu.commit.membars                      814165                       # Number of memory barriers committed
+system.cpu.commit.branches                   26044798                       # Number of branches committed
+system.cpu.commit.fp_insts                      11492                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                 120233477                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              4891928                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu         91728959     66.79%     66.79% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult          112792      0.08%     66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         91774855     66.79%     66.79% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult          113526      0.08%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::IntDiv                0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp              0      0.00%     66.87% # Class of committed instruction
@@ -839,693 +840,689 @@ system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     66.87% #
 system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc         8577      0.01%     66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead        24906127     18.13%     85.01% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite       20592300     14.99%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc         8591      0.01%     66.88% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     66.88% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.88% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.88% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        24916720     18.13%     85.01% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite       20596692     14.99%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         137348755                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               1072317                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    389160423                       # The number of ROB reads
-system.cpu.rob.rob_writes                   292308325                       # The number of ROB writes
-system.cpu.timesIdled                          890756                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         7866030                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   5387322891                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   113111333                       # Number of Instructions Simulated
-system.cpu.committedOps                     137193850                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               2.461870                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.461870                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.406195                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.406195                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                155535200                       # number of integer regfile reads
-system.cpu.int_regfile_writes                88495253                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      9528                       # number of floating regfile reads
+system.cpu.commit.op_class_0::total         137410384                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               1066848                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    376774257                       # The number of ROB reads
+system.cpu.rob.rob_writes                   292425270                       # The number of ROB writes
+system.cpu.timesIdled                          893722                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         6158637                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   5391355036                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   113155640                       # Number of Instructions Simulated
+system.cpu.committedOps                     137255479                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               2.336173                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.336173                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.428050                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.428050                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                155596461                       # number of integer regfile reads
+system.cpu.int_regfile_writes                88540193                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      9674                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                     2716                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 502191757                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 53133619                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               461629806                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                1521804                       # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements            838109                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.925913                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            40060330                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            838621                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             47.769290                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         441954500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.925913                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999855                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999855                       # Average percentage of cache occupancy
+system.cpu.cc_regfile_reads                 502394909                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 53149715                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               449419252                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                1520020                       # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements            839084                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.954165                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            40069527                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            839596                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             47.724771                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         270911500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.954165                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999910                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999910                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          130                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          358                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           24                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          124                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          362                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         179138470                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        179138470                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data     23266826                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        23266826                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     15542812                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       15542812                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       345885                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        345885                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       441505                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       441505                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       460387                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       460387                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      38809638                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         38809638                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     39155523                       # number of overall hits
-system.cpu.dcache.overall_hits::total        39155523                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       704207                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        704207                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      3608607                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      3608607                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       177503                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       177503                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        27219                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        27219                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses         179200286                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        179200286                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data     23273566                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23273566                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     15547100                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       15547100                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       345314                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        345314                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       441102                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       441102                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       459566                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       459566                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      38820666                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         38820666                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     39165980                       # number of overall hits
+system.cpu.dcache.overall_hits::total        39165980                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       709196                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        709196                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      3610101                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      3610101                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       177382                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       177382                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        26835                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        26835                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            5                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            5                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      4312814                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        4312814                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      4490317                       # number of overall misses
-system.cpu.dcache.overall_misses::total       4490317                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  11705123500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  11705123500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 232670418192                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 232670418192                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    376308000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    376308000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       275000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       275000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 244375541692                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 244375541692                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 244375541692                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 244375541692                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     23971033                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     23971033                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     19151419                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     19151419                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       523388                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       523388                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       468724                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       468724                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       460392                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       460392                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     43122452                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     43122452                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     43645840                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     43645840                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.029377                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.029377                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.188425                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.188425                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.339142                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.339142                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.058070                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.058070                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_misses::cpu.data      4319297                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        4319297                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      4496679                       # number of overall misses
+system.cpu.dcache.overall_misses::total       4496679                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  10317292500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  10317292500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 150336233192                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 150336233192                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    369753500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    369753500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       213000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       213000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 160653525692                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 160653525692                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 160653525692                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 160653525692                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     23982762                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     23982762                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     19157201                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     19157201                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       522696                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       522696                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       467937                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       467937                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       459571                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       459571                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     43139963                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     43139963                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     43662659                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     43662659                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.029571                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.029571                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.188446                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.188446                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.339360                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.339360                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.057347                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.057347                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000011                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000011                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.100013                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.100013                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.102881                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.102881                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16621.708532                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16621.708532                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64476.519109                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 64476.519109                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13825.195635                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13825.195635                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        55000                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total        55000                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 56662.666577                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 56662.666577                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 54422.781664                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 54422.781664                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       867732                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.100123                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.100123                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.102987                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.102987                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14547.871815                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14547.871815                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41643.220838                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 41643.220838                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13778.777716                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13778.777716                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        42600                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total        42600                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 37194.368827                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 37194.368827                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 35727.150124                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 35727.150124                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       590933                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              6871                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              7520                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs   126.289041                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    78.581516                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks       696134                       # number of writebacks
-system.cpu.dcache.writebacks::total            696134                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       290642                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       290642                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3308599                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      3308599                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        18782                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        18782                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      3599241                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      3599241                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      3599241                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      3599241                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       413565                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       413565                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       300008                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       300008                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       119442                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       119442                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8437                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total         8437                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       696178                       # number of writebacks
+system.cpu.dcache.writebacks::total            696178                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       295013                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       295013                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3309632                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      3309632                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        18459                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        18459                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      3604645                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      3604645                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      3604645                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      3604645                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       414183                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       414183                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       300469                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       300469                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       119358                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       119358                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8376                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total         8376                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            5                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            5                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       713573                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       713573                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       833015                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       833015                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31129                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.ReadReq_mshr_uncacheable::total        31129                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27585                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total        27585                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58714                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total        58714                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6383877500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   6383877500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19987260971                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  19987260971                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1693165000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1693165000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    126972500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    126972500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       270000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       270000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26371138471                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  26371138471                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28064303471                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  28064303471                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6276254500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6276254500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6276254500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   6276254500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017253                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017253                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015665                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015665                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.228209                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.228209                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.018000                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.018000                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data       714652                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       714652                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       834010                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       834010                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31127                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.ReadReq_mshr_uncacheable::total        31127                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27584                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58711                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total        58711                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5890415000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   5890415000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  13426039479                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  13426039479                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1622684000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1622684000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    130358500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    130358500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       208000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       208000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  19316454479                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  19316454479                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  20939138479                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  20939138479                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6279502000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6279502000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6279502000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   6279502000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017270                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017270                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015684                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015684                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.228351                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.228351                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017900                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017900                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000011                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000011                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016548                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.016548                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019086                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.019086                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15436.213171                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15436.213171                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66622.426639                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66622.426639                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14175.624990                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14175.624990                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15049.484414                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15049.484414                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        54000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        54000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36956.469024                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 36956.469024                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33690.033758                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 33690.033758                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201620.819814                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201620.819814                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106895.365671                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106895.365671                       # average overall mshr uncacheable latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements           1886431                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.154202                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            64000082                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1886943                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             33.917337                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       16319051500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.154202                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.998348                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.998348                       # Average percentage of cache occupancy
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016566                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.016566                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019101                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.019101                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14221.769121                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14221.769121                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44683.609554                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44683.609554                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13595.100454                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13595.100454                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15563.335721                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15563.335721                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        41600                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        41600                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27029.175709                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 27029.175709                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25106.579632                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 25106.579632                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201738.105182                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201738.105182                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106956.141098                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106956.141098                       # average overall mshr uncacheable latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements           1887810                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.341026                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            64075895                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1888322                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             33.932716                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       13715039500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.341026                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.998713                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.998713                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          127                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          171                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          211                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          125                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          164                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          221                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          67865267                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         67865267                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst     64000082                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        64000082                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      64000082                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         64000082                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     64000082                       # number of overall hits
-system.cpu.icache.overall_hits::total        64000082                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1978185                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1978185                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1978185                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1978185                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1978185                       # number of overall misses
-system.cpu.icache.overall_misses::total       1978185                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  28158737492                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  28158737492                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  28158737492                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  28158737492                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  28158737492                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  28158737492                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     65978267                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     65978267                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     65978267                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     65978267                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     65978267                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     65978267                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.029982                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.029982                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.029982                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.029982                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.029982                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.029982                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14234.633006                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14234.633006                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14234.633006                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14234.633006                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14234.633006                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14234.633006                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         5390                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          67944454                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         67944454                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst     64075895                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        64075895                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      64075895                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         64075895                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     64075895                       # number of overall hits
+system.cpu.icache.overall_hits::total        64075895                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1980206                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1980206                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1980206                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1980206                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1980206                       # number of overall misses
+system.cpu.icache.overall_misses::total       1980206                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  26984355494                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  26984355494                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  26984355494                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  26984355494                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  26984355494                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  26984355494                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     66056101                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     66056101                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     66056101                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     66056101                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     66056101                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     66056101                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.029978                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.029978                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.029978                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.029978                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.029978                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.029978                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13627.044607                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13627.044607                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13627.044607                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13627.044607                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13627.044607                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13627.044607                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         2643                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               176                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               125                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    30.625000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    21.144000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks      1886431                       # number of writebacks
-system.cpu.icache.writebacks::total           1886431                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        91184                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        91184                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        91184                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        91184                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        91184                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        91184                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1887001                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1887001                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1887001                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1887001                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1887001                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1887001                       # number of overall MSHR misses
+system.cpu.icache.writebacks::writebacks      1887810                       # number of writebacks
+system.cpu.icache.writebacks::total           1887810                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        91852                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        91852                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        91852                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        91852                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        91852                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        91852                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1888354                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1888354                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1888354                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1888354                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1888354                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1888354                       # number of overall MSHR misses
 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         3003                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.ReadReq_mshr_uncacheable::total         3003                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3003                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses::total         3003                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  25189687497                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  25189687497                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  25189687497                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  25189687497                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  25189687497                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  25189687497                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    377605500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    377605500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    377605500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total    377605500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.028600                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.028600                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.028600                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.028600                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.028600                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.028600                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13349.058902                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13349.058902                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13349.058902                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13349.058902                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13349.058902                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13349.058902                       # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 125742.757243                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 125742.757243                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 125742.757243                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 125742.757243                       # average overall mshr uncacheable latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements            97066                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65034.676246                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            5004762                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           162374                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            30.822435                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 49586.658386                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    11.610418                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     2.677884                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 10386.588269                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  5047.141288                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.756632                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000177                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000041                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.158487                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.077013                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.992350                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023           15                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65293                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4           15                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          144                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2842                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6720                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55568                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000229                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.996292                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         44286849                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        44286849                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        57782                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        12059                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total          69841                       # number of ReadReq hits
-system.cpu.l2cache.WritebackDirty_hits::writebacks       696134                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       696134                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks      1848502                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total      1848502                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           60                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           60                       # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            2                       # number of SCUpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::total            2                       # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       161598                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       161598                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1866971                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total      1866971                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       527952                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       527952                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker        57782                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker        12059                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst      1866971                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       689550                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2626362                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker        57782                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker        12059                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst      1866971                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       689550                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2626362                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           21                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            7                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total           28                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         2746                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         2746                       # number of UpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::total            3                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       135739                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       135739                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        19929                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        19929                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data        13357                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total        13357                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker           21                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker            7                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        19929                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       149096                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        169053                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker           21                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker            7                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        19929                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       149096                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       169053                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      2978500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       929000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total      3907500                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      2730500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total      2730500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       162000                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::total       162000                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  17623320500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  17623320500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2639049500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total   2639049500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1797637500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   1797637500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      2978500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       929000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   2639049500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  19420958000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  22063915000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      2978500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       929000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   2639049500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  19420958000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  22063915000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        57803                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        12066                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total        69869                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       696134                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       696134                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks      1848502                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total      1848502                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2806                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         2806                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  24226536497                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  24226536497                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  24226536497                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  24226536497                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  24226536497                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  24226536497                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    229048500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    229048500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    229048500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total    229048500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.028587                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.028587                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.028587                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.028587                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.028587                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.028587                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12829.446437                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12829.446437                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12829.446437                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12829.446437                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12829.446437                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12829.446437                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 76273.226773                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 76273.226773                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 76273.226773                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 76273.226773                       # average overall mshr uncacheable latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.replacements           103423                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65159.012032                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            5300281                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           168782                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            31.403118                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      93779484000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     9.961762                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     3.729813                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 10177.791609                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 54967.528848                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000152                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000057                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.155301                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.838738                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.994248                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023           14                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65345                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4           14                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          175                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5571                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        59599                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000214                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997086                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         43992446                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        43992446                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        54341                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        10212                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total          64553                       # number of ReadReq hits
+system.cpu.l2cache.WritebackDirty_hits::writebacks       696178                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total       696178                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks      1850381                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total      1850381                       # number of WritebackClean hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data         2757                       # number of UpgradeReq hits
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+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1868353                       # number of ReadCleanReq hits
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+system.cpu.l2cache.demand_hits::total         2619078                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker        54341                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker        10212                       # number of overall hits
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+system.cpu.l2cache.overall_hits::total        2619078                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           16                       # number of ReadReq misses
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+system.cpu.l2cache.ReadReq_misses::total           22                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data           11                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total           11                       # number of UpgradeReq misses
+system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
+system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       139010                       # number of ReadExReq misses
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+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        19937                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total        19937                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data        14436                       # number of ReadSharedReq misses
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+system.cpu.l2cache.demand_misses::cpu.dtb.walker           16                       # number of demand (read+write) misses
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+system.cpu.l2cache.demand_misses::cpu.inst        19937                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       153446                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        173405                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker           16                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.itb.walker            6                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst        19937                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       153446                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       173405                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      1497500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       502000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total      1999500                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       320500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total       320500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       167000                       # number of SCUpgradeReq miss cycles
+system.cpu.l2cache.SCUpgradeReq_miss_latency::total       167000                       # number of SCUpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  11275740500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  11275740500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1659086000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total   1659086000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1242944500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total   1242944500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      1497500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       502000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   1659086000                       # number of demand (read+write) miss cycles
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+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      1497500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       502000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   1659086000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  12518685000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  14179770500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        54357                       # number of ReadReq accesses(hits+misses)
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+system.cpu.l2cache.ReadReq_accesses::total        64575                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::writebacks       696178                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total       696178                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks      1850381                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total      1850381                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2768                       # number of UpgradeReq accesses(hits+misses)
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 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            5                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::total            5                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       297337                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       297337                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1886900                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total      1886900                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       541309                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total       541309                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker        57803                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker        12066                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst      1886900                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       838646                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2795415                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker        57803                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker        12066                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      1886900                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       838646                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2795415                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000363                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000580                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.000401                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.978617                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.978617                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.600000                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.600000                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.456516                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.456516                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.010562                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.010562                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.024675                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.024675                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000363                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000580                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.010562                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.177782                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.060475                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000363                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000580                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010562                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.177782                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.060475                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 141833.333333                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 132714.285714                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 139553.571429                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   994.355426                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   994.355426                       # average UpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        54000                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        54000                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 129832.402626                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 129832.402626                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132422.575142                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132422.575142                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134583.926031                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134583.926031                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 141833.333333                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 132714.285714                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132422.575142                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 130258.075334                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 130514.779389                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 141833.333333                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 132714.285714                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132422.575142                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 130258.075334                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 130514.779389                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       297834                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       297834                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1888290                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total      1888290                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       541784                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total       541784                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker        54357                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker        10218                       # number of demand (read+write) accesses
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+system.cpu.l2cache.overall_accesses::cpu.dtb.walker        54357                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker        10218                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst      1888290                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       839618                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2792483                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000294                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000587                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.000341                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.003974                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.003974                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.400000                       # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.400000                       # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.466737                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.466737                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.010558                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.010558                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.026645                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.026645                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000294                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000587                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.010558                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.182757                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.062097                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000294                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000587                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010558                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.182757                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.062097                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 93593.750000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 83666.666667                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 90886.363636                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 29136.363636                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 29136.363636                       # average UpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        83500                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        83500                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81114.599669                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81114.599669                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83216.431760                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83216.431760                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86100.339429                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86100.339429                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 93593.750000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 83666.666667                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83216.431760                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81583.651578                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 81772.558461                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 93593.750000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 83666.666667                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83216.431760                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81583.651578                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 81772.558461                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks        89296                       # number of writebacks
-system.cpu.l2cache.writebacks::total            89296                       # number of writebacks
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           26                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total           26                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.writebacks::writebacks        95172                       # number of writebacks
+system.cpu.l2cache.writebacks::total            95172                       # number of writebacks
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           23                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total           23                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          112                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::total          112                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           26                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           23                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.data          112                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total          138                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           26                       # number of overall MSHR hits
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 system.cpu.l2cache.overall_mshr_hits::cpu.data          112                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total          138                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           21                       # number of ReadReq MSHR misses
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-system.cpu.l2cache.ReadReq_mshr_misses::total           28                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2746                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         2746                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       135739                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       135739                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        19903                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        19903                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        13245                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total        13245                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           21                       # number of demand (read+write) MSHR misses
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-system.cpu.l2cache.demand_mshr_misses::cpu.inst        19903                       # number of demand (read+write) MSHR misses
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-system.cpu.l2cache.demand_mshr_misses::total       168915                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           21                       # number of overall MSHR misses
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-system.cpu.l2cache.overall_mshr_misses::cpu.inst        19903                       # number of overall MSHR misses
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+system.cpu.l2cache.UpgradeReq_mshr_misses::total           11                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       139010                       # number of ReadExReq MSHR misses
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+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        19914                       # number of ReadCleanReq MSHR misses
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 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         3003                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31129                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total        34132                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        27585                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total        27585                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31127                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::total        34130                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        27584                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         3003                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58714                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total        61717                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      2768500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       859000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total      3627500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    186762000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    186762000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       210500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       210500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  16265930500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  16265930500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2437107003                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2437107003                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1651792000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1651792000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      2768500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       859000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2437107003                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  17917722500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  20358457003                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      2768500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       859000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2437107003                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  17917722500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  20358457003                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    340067500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5887129500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6227197000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    340067500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5887129500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   6227197000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000363                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000580                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000401                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.978617                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.978617                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.600000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.600000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.456516                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.456516                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.010548                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.010548                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.024468                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.024468                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000363                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000580                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010548                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.177648                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.060426                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000363                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000580                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010548                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.177648                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.060426                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 131833.333333                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122714.285714                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 129553.571429                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68012.381646                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68012.381646                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70166.666667                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70166.666667                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119832.402626                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119832.402626                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122449.228910                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122449.228910                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124710.607777                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124710.607777                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 131833.333333                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122714.285714                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122449.228910                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120266.085620                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120524.861635                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 131833.333333                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122714.285714                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122449.228910                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120266.085620                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120524.861635                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113242.590743                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189120.418260                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182444.538849                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113242.590743                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100267.900330                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 100899.217396                       # average overall mshr uncacheable latency
-system.cpu.toL2Bus.snoop_filter.tot_requests      5483160                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2757544                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        45002                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops          381                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops          381                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58711                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total        61714                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      1337500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       442000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total      1779500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       210500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       210500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       147000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       147000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   9885640500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   9885640500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1458480000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1458480000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1091561500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1091561500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      1337500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       442000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1458480000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  10977202000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  12437461500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      1337500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       442000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1458480000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  10977202000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  12437461500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    191510500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5890404500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6081915000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    191510500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5890404500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   6081915000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000294                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000587                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000341                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.003974                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.003974                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.400000                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.400000                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.466737                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.466737                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.010546                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.010546                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.026439                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.026439                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000294                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000587                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010546                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.182624                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.062049                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000294                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000587                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010546                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.182624                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.062049                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 83593.750000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 73666.666667                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 80886.363636                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19136.363636                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19136.363636                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        73500                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        73500                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71114.599669                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71114.599669                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73238.927388                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73238.927388                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76205.075398                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76205.075398                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 83593.750000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 73666.666667                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73238.927388                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71590.136565                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71780.813182                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 83593.750000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 73666.666667                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73238.927388                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71590.136565                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71780.813182                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63773.060273                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189237.783917                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 178198.505713                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63773.060273                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100328.805505                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 98550.004861                       # average overall mshr uncacheable latency
+system.cpu.toL2Bus.snoop_filter.tot_requests      5488560                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2760615                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        44763                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops          238                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops          238                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadReq         128619                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2557060                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         27585                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        27585                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       821637                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean      1886431                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       149968                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2806                       # Transaction distribution
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadReq         129622                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2559974                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         27584                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        27584                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       791350                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      1887810                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       151157                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2768                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            5                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2811                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       297337                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       297337                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      1887001                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       541532                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5666337                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2638583                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        30857                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       133499                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8469276                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    241541168                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98417449                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        48264                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       231212                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          340238093                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      194794                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic               8145576                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples      3054607                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.024758                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.155386                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2773                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       297834                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       297834                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1888354                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       542004                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq         4368                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5670459                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2641503                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        29194                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       130873                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8472029                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    241718384                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98487773                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        40872                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       217428                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          340464457                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      139207                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic               6232532                       # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples      2995964                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.025358                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.157210                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            2978982     97.52%     97.52% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              75625      2.48%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2919992     97.46%     97.46% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              75972      2.54%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3054607                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     5400960498                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        2995964                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     5405204997                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       258877                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       383377                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    2834452098                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    2836467127                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1304519551                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1305988986                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      18799483                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      18982487                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      75755880                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      76565899                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq                30172                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               30172                       # Transaction distribution
+system.iobus.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.iobus.trans_dist::ReadReq                30182                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               30182                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
@@ -1548,9 +1545,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72894                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total        72894                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  178372                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72914                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total        72914                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  178392                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
@@ -1571,22 +1568,22 @@ system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321016                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      2321016                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2480141                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             43088500                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321096                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      2321096                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2480221                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             43094500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               100500                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               101000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               326000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               325500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                28000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                28500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy                14500                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy                92500                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy                91500                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer8.occupancy               651500                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy               649500                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy               20500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
@@ -1608,56 +1605,56 @@ system.iobus.reqLayer20.occupancy                9000                       # La
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer21.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6158500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6172500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            33063500                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            33854000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           187149991                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           187760330                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36718000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36738000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements                36413                       # number of replacements
-system.iocache.tags.tagsinuse                1.005857                       # Cycle average of tags in use
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.replacements                36423                       # number of replacements
+system.iocache.tags.tagsinuse                1.000676                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                36429                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                36439                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         256506730000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.005857                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.062866                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.062866                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         252706881000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.000676                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.062542                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.062542                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               328023                       # Number of tag accesses
-system.iocache.tags.data_accesses              328023                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.iocache.ReadReq_misses::realview.ide          223                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              223                       # number of ReadReq misses
+system.iocache.tags.tag_accesses               328113                       # Number of tag accesses
+system.iocache.tags.data_accesses              328113                       # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.iocache.ReadReq_misses::realview.ide          233                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              233                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide        36447                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             36447                       # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide        36447                       # number of overall misses
-system.iocache.overall_misses::total            36447                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     28156877                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     28156877                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4551348114                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4551348114                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide   4579504991                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   4579504991                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide   4579504991                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   4579504991                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ide          223                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            223                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::realview.ide        36457                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             36457                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide        36457                       # number of overall misses
+system.iocache.overall_misses::total            36457                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide     28964877                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     28964877                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4277512453                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4277512453                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide   4306477330                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   4306477330                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide   4306477330                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   4306477330                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ide          233                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            233                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide        36447                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           36447                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide        36447                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          36447                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::realview.ide        36457                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           36457                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide        36457                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          36457                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
@@ -1666,14 +1663,14 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 126264.022422                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 126264.022422                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125644.548200                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 125644.548200                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 125648.338437                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 125648.338437                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 125648.338437                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 125648.338437                       # average overall miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 124312.776824                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 124312.776824                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118085.039007                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118085.039007                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 118124.841046                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 118124.841046                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 118124.841046                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 118124.841046                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
@@ -1682,22 +1679,22 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.writebacks::writebacks           36190                       # number of writebacks
 system.iocache.writebacks::total                36190                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ide          223                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          223                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide          233                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          233                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide        36447                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        36447                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide        36447                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        36447                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     17006877                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     17006877                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2738747578                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2738747578                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   2755754455                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   2755754455                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   2755754455                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   2755754455                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::realview.ide        36457                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        36457                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide        36457                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        36457                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     17314877                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     17314877                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2464212681                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2464212681                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   2481527558                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   2481527558                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   2481527558                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   2481527558                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1706,84 +1703,90 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76264.022422                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 76264.022422                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75605.884993                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75605.884993                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 75609.911790                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 75609.911790                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 75609.911790                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 75609.911790                       # average overall mshr miss latency
-system.membus.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq               34132                       # Transaction distribution
-system.membus.trans_dist::ReadResp              67530                       # Transaction distribution
-system.membus.trans_dist::WriteReq              27585                       # Transaction distribution
-system.membus.trans_dist::WriteResp             27585                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       125486                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             7993                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4611                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74312.776824                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 74312.776824                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68027.072687                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68027.072687                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 68067.245193                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 68067.245193                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 68067.245193                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 68067.245193                       # average overall mshr miss latency
+system.membus.snoop_filter.tot_requests        349590                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests       144366                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests          482                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
+system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadReq               34130                       # Transaction distribution
+system.membus.trans_dist::ReadResp              68622                       # Transaction distribution
+system.membus.trans_dist::WriteReq              27584                       # Transaction distribution
+system.membus.trans_dist::WriteResp             27584                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       131362                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             8484                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              130                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            133874                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           133874                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         33399                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            138891                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           138891                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         34493                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           14                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2076                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       451368                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       558936                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72875                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        72875                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 631811                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2070                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       465445                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       573007                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72895                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        72895                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 645902                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          112                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4152                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16456092                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16619481                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4140                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17222620                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     17385997                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                18936601                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              487                       # Total snoops (count)
-system.membus.snoopTraffic                      31040                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            403324                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.pkt_size::total                19703117                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              497                       # Total snoops (count)
+system.membus.snoopTraffic                      31680                       # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples            271454                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.017933                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.132708                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  403324    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  266586     98.21%     98.21% # Request fanout histogram
+system.membus.snoop_fanout::1                    4868      1.79%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              403324                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            83656500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              271454                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            84464500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                9000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1736499                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1723499                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           876921354                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           908168519                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          979994750                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1012308500                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy            1182123                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy            1273123                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
 system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
 system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
 system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
 system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -1815,30 +1818,30 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
 system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500                       # Cumulative time (in ticks) in various power states
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000                       # Cumulative time (in ticks) in various power states
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     3037                       # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce                     3038                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
index 317b8f2e9..b158166a6 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
@@ -1,169 +1,169 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.823751                       # Number of seconds simulated
-sim_ticks                                2823750824500                       # Number of ticks simulated
-final_tick                               2823750824500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.823713                       # Number of seconds simulated
+sim_ticks                                2823712531500                       # Number of ticks simulated
+final_tick                               2823712531500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 215412                       # Simulator instruction rate (inst/s)
-host_op_rate                                   261296                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4949093514                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 585976                       # Number of bytes of host memory used
-host_seconds                                   570.56                       # Real time elapsed on the host
-sim_insts                                   122905142                       # Number of instructions simulated
-sim_ops                                     149084969                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 235362                       # Simulator instruction rate (inst/s)
+host_op_rate                                   285496                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5406413351                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 591960                       # Number of bytes of host memory used
+host_seconds                                   522.29                       # Real time elapsed on the host
+sim_insts                                   122926882                       # Number of instructions simulated
+sim_ops                                     149111695                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu0.dtb.walker          320                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           542180                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          3155236                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           537508                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          3136100                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.dtb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           122688                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           900352                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           121472                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           903168                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu2.dtb.walker         1792                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst           341632                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          1990912                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.dtb.walker         4736                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst           343232                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          1991872                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.dtb.walker         4544                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu3.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst           381248                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.data          3510400                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst           387072                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.data          3526656                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10952712                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       542180                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       122688                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst       341632                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst       381248                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1387748                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8236736                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             10954952                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       537508                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       121472                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst       343232                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst       387072                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1389284                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8237952                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8254260                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8255476                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu0.dtb.walker            5                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             16925                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             49820                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             16852                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             49521                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.dtb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              1917                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             14068                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              1898                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             14112                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu2.dtb.walker           28                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst              5338                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data             31108                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.dtb.walker           74                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst              5363                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data             31123                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.dtb.walker           71                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu3.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst              5957                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.data             54850                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst              6048                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.data             55104                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                180109                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          128699                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                180144                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          128718                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               133080                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               133099                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu0.dtb.walker           113                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            45                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              192007                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1117392                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              190355                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1110630                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.dtb.walker            23                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               43449                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              318850                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               43019                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              319851                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu2.dtb.walker           635                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst              120985                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data              705059                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.dtb.walker          1677                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst              121553                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data              705409                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.dtb.walker          1609                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu3.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst              135015                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data             1243169                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst              137079                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data             1248943                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              340                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3878781                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         192007                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          43449                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst         120985                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst         135015                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             491456                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2916949                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3879627                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         190355                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          43019                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst         121553                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst         137079                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             492006                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2917419                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data               6206                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2923155                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2916949                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2923625                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2917419                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.dtb.walker          113                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           45                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             192007                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1123598                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             190355                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1116836                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.dtb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              43449                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             318850                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              43019                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             319851                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu2.dtb.walker          635                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst             120985                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data             705059                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.dtb.walker         1677                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst             121553                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data             705409                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.dtb.walker         1609                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu3.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst             135015                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data            1243169                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst             137079                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data            1248943                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             340                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6801936                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        113342                       # Number of read requests accepted
-system.physmem.writeReqs                        68762                       # Number of write requests accepted
-system.physmem.readBursts                      113342                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      68762                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  7247168                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6720                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4399872                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   7253888                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                4400768                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      105                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total                6803252                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        113749                       # Number of read requests accepted
+system.physmem.writeReqs                        69024                       # Number of write requests accepted
+system.physmem.readBursts                      113749                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      69024                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  7272896                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      7040                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4416768                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   7279936                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                4417536                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      110                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                7506                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                6787                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                7407                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                7543                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                7335                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                7022                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                7619                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                7707                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                6869                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                7531                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               6987                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               6354                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               6401                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               7189                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               6831                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               6149                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                4366                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                3966                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                4487                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                4689                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                4379                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                4312                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                4615                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                4485                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                4160                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                4849                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               4371                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               3905                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               3814                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               4615                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               4128                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               3607                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                7641                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                6876                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                7409                       # Per bank write bursts
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+system.physmem.perBankRdBursts::5                7030                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                7627                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                7716                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                6884                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                7545                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               7008                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               6374                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               6408                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               7193                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               6835                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               6286                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                4484                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                4020                       # Per bank write bursts
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+system.physmem.perBankWrBursts::4                4310                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                4320                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                4621                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                4483                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                4167                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                4860                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               4381                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               3929                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               3827                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               4631                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               4137                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               3740                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           2                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2822178697500                       # Total gap between requests
+system.physmem.numWrRetry                           1                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2822140482500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  113342                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  113749                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  68762                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     85611                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     24487                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      2575                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       560                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  69024                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     85840                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     24773                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      2446                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       577                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -191,176 +191,172 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                        70                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                        68                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                        73                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                        67                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::2                        65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                        66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                        64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                        63                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                        63                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                        65                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                        66                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                        66                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                        64                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::7                        63                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                        62                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                        61                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::9                        62                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::10                       62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                       62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                       62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                       62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                       61                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1135                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1473                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     3008                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     3566                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     3765                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     3730                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     3916                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4140                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4230                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4336                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4518                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     4815                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4157                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4283                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4363                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     3849                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     3792                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     3696                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       99                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      109                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       77                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       44                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       30                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                       40                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       46                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                       40                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                       43                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                       45                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                       46                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                       46                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       46                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       26                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       30                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       29                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       30                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       13                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       23                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                       61                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                       60                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                       60                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                       60                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1111                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1427                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     2991                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::52                       29                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::55                       18                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::56                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       20                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        7                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        39262                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      296.647547                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     172.649192                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     326.383393                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          15575     39.67%     39.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         9414     23.98%     63.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         3760      9.58%     73.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2064      5.26%     78.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1515      3.86%     82.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1018      2.59%     84.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          639      1.63%     86.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          658      1.68%     88.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         4619     11.76%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          39262                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          3618                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        31.293256                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      632.321482                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           3616     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::57                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       13                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        3                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        39259                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      297.757559                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     173.671784                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     326.464821                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          15432     39.31%     39.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         9477     24.14%     63.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         3788      9.65%     73.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2095      5.34%     78.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1555      3.96%     82.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1004      2.56%     84.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          603      1.54%     86.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          654      1.67%     88.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         4651     11.85%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          39259                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          3667                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        30.985274                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      628.070623                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           3665     99.95%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-4095            1      0.03%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::36864-38911            1      0.03%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            3618                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          3618                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        19.001658                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.828073                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       10.498575                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                 5      0.14%      0.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                 2      0.06%      0.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11                2      0.06%      0.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15               2      0.06%      0.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            3234     89.39%     89.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              43      1.19%     90.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              55      1.52%     92.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              37      1.02%     93.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              88      2.43%     95.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              33      0.91%     96.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              11      0.30%     97.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              11      0.30%     97.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51               5      0.14%     97.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               7      0.19%     97.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               2      0.06%     97.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               5      0.14%     97.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67              54      1.49%     99.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               3      0.08%     99.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               1      0.03%     99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               4      0.11%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               2      0.06%     99.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               1      0.03%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.03%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             2      0.06%     99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.03%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             3      0.08%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.06%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             1      0.03%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             1      0.03%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            3618                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1331922750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                3455116500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    566185000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       11762.26                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            3667                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          3667                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        18.819744                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.710166                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        9.565148                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                 9      0.25%      0.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                 3      0.08%      0.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11                3      0.08%      0.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15               6      0.16%      0.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            3283     89.53%     90.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              35      0.95%     91.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              47      1.28%     92.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              39      1.06%     93.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              88      2.40%     95.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              43      1.17%     96.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43               6      0.16%     97.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              10      0.27%     97.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51               7      0.19%     97.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               5      0.14%     97.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               4      0.11%     97.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               3      0.08%     97.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              62      1.69%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               1      0.03%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               1      0.03%     99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               4      0.11%     99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               1      0.03%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.03%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             4      0.11%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             1      0.03%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             1      0.03%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            3667                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1342938250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                3473669500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    568195000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11817.58                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30512.26                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.57                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  30567.58                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.58                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           1.56                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.57                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.58                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        1.56                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        19.94                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      93386                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     49336                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.47                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  71.75                       # Row buffer hit rate for writes
-system.physmem.avgGap                     15497620.58                       # Average gap between requests
-system.physmem.pageHitRate                      78.42                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  157701600                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                   85878375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 459622800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                228737520                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           179710355760                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            72061196355                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1617839664000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1870543156410                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              667.633364                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2641056208250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     91876460000                       # Time in different power states
+system.physmem.avgWrQLen                        27.55                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      93703                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     49689                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.46                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  71.99                       # Row buffer hit rate for writes
+system.physmem.avgGap                     15440685.89                       # Average gap between requests
+system.physmem.pageHitRate                      78.50                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  158064480                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                   86055750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 461026800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                229003200                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           179708321520                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            72025489845                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1621445025000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1874112986595                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              667.488376                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2641083296250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     91875160000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     18550863000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     18501220250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  139119120                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                   75726750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 423618000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                216749520                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           179710355760                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            71208324450                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1622163329250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1873937222850                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              667.425184                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2642291372250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     91876460000                       # Time in different power states
+system.physmem_1.actEnergy                  138733560                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                   75508125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 425357400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                218194560                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           179708321520                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            71152837515                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1620392151000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1872111103680                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              667.495866                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2642358679500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     91875160000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     17320352000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     17221255250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
@@ -373,9 +369,9 @@ system.realview.nvmem.bw_inst_read::cpu0.inst            7
 system.realview.nvmem.bw_inst_read::total            7                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu0.inst            7                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total               7                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
@@ -383,7 +379,7 @@ system.cf0.dma_write_full_pages                   540                       # Nu
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -413,49 +409,49 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.cpu0.dtb.walker.walks                     4996                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort                4996                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walkWaitTime::samples         4996                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0           4996    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total         4996                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walksPending::samples  56881650376                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     1.265666                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0   -15111501624    -26.57%    -26.57% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1    71993152000    126.57%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total  56881650376                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         2808     68.21%     68.21% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         1309     31.79%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         4117                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         4996                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.walker.walks                     4966                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort                4966                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walkWaitTime::samples         4966                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0           4966    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total         4966                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walksPending::samples  56881367876                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     1.265672                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0   -15111782124    -26.57%    -26.57% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1    71993150000    126.57%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total  56881367876                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K         2795     68.22%     68.22% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1302     31.78%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         4097                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         4966                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         4996                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         4117                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         4966                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         4097                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         4117                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total         9113                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         4097                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total         9063                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    12099084                       # DTB read hits
-system.cpu0.dtb.read_misses                      4274                       # DTB read misses
-system.cpu0.dtb.write_hits                    9151888                       # DTB write hits
-system.cpu0.dtb.write_misses                      722                       # DTB write misses
+system.cpu0.dtb.read_hits                    12103158                       # DTB read hits
+system.cpu0.dtb.read_misses                      4250                       # DTB read misses
+system.cpu0.dtb.write_hits                    9145748                       # DTB write hits
+system.cpu0.dtb.write_misses                      716                       # DTB write misses
 system.cpu0.dtb.flush_tlb                         171                       # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva                     363                       # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva                     362                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    2772                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries                    2759                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   821                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                   823                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      173                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                12103358                       # DTB read accesses
-system.cpu0.dtb.write_accesses                9152610                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      174                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                12107408                       # DTB read accesses
+system.cpu0.dtb.write_accesses                9146464                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         21250972                       # DTB hits
-system.cpu0.dtb.misses                           4996                       # DTB misses
-system.cpu0.dtb.accesses                     21255968                       # DTB accesses
-system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.hits                         21248906                       # DTB hits
+system.cpu0.dtb.misses                           4966                       # DTB misses
+system.cpu0.dtb.accesses                     21253872                       # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -485,93 +481,93 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.cpu0.itb.walker.walks                     2442                       # Table walker walks requested
-system.cpu0.itb.walker.walksShort                2442                       # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walkWaitTime::samples         2442                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0           2442    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total         2442                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walksPending::samples  56881650376                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     1.265668                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0   -15111616124    -26.57%    -26.57% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1    71993266500    126.57%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total  56881650376                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K         1322     74.86%     74.86% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M          444     25.14%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total         1766                       # Table walker page sizes translated
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.cpu0.itb.walker.walks                     2431                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort                2431                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walkWaitTime::samples         2431                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0           2431    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total         2431                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walksPending::samples  56881367876                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     1.265674                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0   -15111901124    -26.57%    -26.57% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1    71993269000    126.57%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total  56881367876                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K         1314     74.83%     74.83% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          442     25.17%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         1756                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         2442                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total         2442                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         2431                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total         2431                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         1766                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total         1766                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total         4208                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    56923800                       # ITB inst hits
-system.cpu0.itb.inst_misses                      2442                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         1756                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         1756                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total         4187                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    56926912                       # ITB inst hits
+system.cpu0.itb.inst_misses                      2431                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                         171                       # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva                     363                       # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva                     362                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    1703                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    1695                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                56926242                       # ITB inst accesses
-system.cpu0.itb.hits                         56923800                       # DTB hits
-system.cpu0.itb.misses                           2442                       # DTB misses
-system.cpu0.itb.accesses                     56926242                       # DTB accesses
-system.cpu0.numPwrStateTransitions               2560                       # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples         1280                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean    2127325768.303125                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev   53245910996.367020                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::underflows         1265     98.83%     98.83% # Distribution of time spent in the clock gated state
+system.cpu0.itb.inst_accesses                56929343                       # ITB inst accesses
+system.cpu0.itb.hits                         56926912                       # DTB hits
+system.cpu0.itb.misses                           2431                       # DTB misses
+system.cpu0.itb.accesses                     56929343                       # DTB accesses
+system.cpu0.numPwrStateTransitions               2564                       # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples         1282                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean    2124006318.198128                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev   53204391855.203163                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows         1267     98.83%     98.83% # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::1000-5e+10           11      0.86%     99.69% # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11            1      0.08%     99.77% # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11            1      0.08%     99.84% # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11            1      0.08%     99.92% # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::overflows            1      0.08%    100.00% # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::max_value 1799911049001                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total           1280                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON   100773841072                       # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 2722976983428                       # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles                        68778258                       # number of cpu cycles simulated
+system.cpu0.pwrStateClkGateDist::max_value 1799910947501                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total           1282                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON   100736431570                       # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 2722976099930                       # Cumulative time (in ticks) in various power states
+system.cpu0.numCycles                        68779411                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    3086                       # number of quiesce instructions executed
-system.cpu0.committedInsts                   55461787                       # Number of instructions committed
-system.cpu0.committedOps                     67232154                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             59006752                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                  4424                       # Number of float alu accesses
-system.cpu0.num_func_calls                    5784619                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      7357566                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    59006752                       # number of integer instructions
-system.cpu0.num_fp_insts                         4424                       # number of float instructions
-system.cpu0.num_int_register_reads          108803726                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          41133474                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                3383                       # number of times the floating registers were read
+system.cpu0.kern.inst.quiesce                    3087                       # number of quiesce instructions executed
+system.cpu0.committedInsts                   55462034                       # Number of instructions committed
+system.cpu0.committedOps                     67230601                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             59006165                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                  4380                       # Number of float alu accesses
+system.cpu0.num_func_calls                    5788069                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      7355854                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    59006165                       # number of integer instructions
+system.cpu0.num_fp_insts                         4380                       # number of float instructions
+system.cpu0.num_int_register_reads          108801460                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          41139310                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads                3339                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes               1042                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           204599031                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           24717436                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     21838245                       # number of memory refs
-system.cpu0.num_load_insts                   12248234                       # Number of load instructions
-system.cpu0.num_store_insts                   9590011                       # Number of store instructions
-system.cpu0.num_idle_cycles              64958382.766609                       # Number of idle cycles
-system.cpu0.num_busy_cycles              3819875.233391                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.055539                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.944461                       # Percentage of idle cycles
-system.cpu0.Branches                         13458694                       # Number of branches fetched
+system.cpu0.num_cc_register_reads           204596465                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           24709161                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     21836532                       # number of memory refs
+system.cpu0.num_load_insts                   12252554                       # Number of load instructions
+system.cpu0.num_store_insts                   9583978                       # Number of store instructions
+system.cpu0.num_idle_cycles              64960338.337804                       # Number of idle cycles
+system.cpu0.num_busy_cycles              3819072.662196                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.055526                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.944474                       # Percentage of idle cycles
+system.cpu0.Branches                         13460127                       # Number of branches fetched
 system.cpu0.op_class::No_OpClass                 2178      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 46427379     67.95%     67.96% # Class of executed instruction
-system.cpu0.op_class::IntMult                   50783      0.07%     68.03% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 46428516     67.96%     67.96% # Class of executed instruction
+system.cpu0.op_class::IntMult                   50840      0.07%     68.03% # Class of executed instruction
 system.cpu0.op_class::IntDiv                        0      0.00%     68.03% # Class of executed instruction
 system.cpu0.op_class::FloatAdd                      0      0.00%     68.03% # Class of executed instruction
 system.cpu0.op_class::FloatCmp                      0      0.00%     68.03% # Class of executed instruction
@@ -595,550 +591,550 @@ system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.03% # Cl
 system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.03% # Class of executed instruction
 system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.03% # Class of executed instruction
 system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.03% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc              3883      0.01%     68.04% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc              3886      0.01%     68.04% # Class of executed instruction
 system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.04% # Class of executed instruction
 system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.04% # Class of executed instruction
 system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.04% # Class of executed instruction
-system.cpu0.op_class::MemRead                12248234     17.93%     85.96% # Class of executed instruction
-system.cpu0.op_class::MemWrite                9590011     14.04%    100.00% # Class of executed instruction
+system.cpu0.op_class::MemRead                12252554     17.93%     85.97% # Class of executed instruction
+system.cpu0.op_class::MemWrite                9583978     14.03%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  68322468                       # Class of executed instruction
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements           833257                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.996712                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           45925455                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           833769                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            55.081749                       # Average number of references to valid blocks.
+system.cpu0.op_class::total                  68321952                       # Class of executed instruction
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.tags.replacements           833218                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.996713                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           45933242                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           833730                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            55.093666                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         23053500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   482.041518                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data    11.532588                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data     4.805161                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu3.data    13.617445                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.941487                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.022525                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.009385                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu3.data     0.026597                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   481.881738                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data    11.691774                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data     4.820044                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu3.data    13.603157                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.941175                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.022835                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data     0.009414                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu3.data     0.026569                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0           60                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          363                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           89                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          362                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           88                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        193121109                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       193121109                       # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data     11466282                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      3602501                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data      4049569                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu3.data      6704947                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       25823299                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      8812878                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      2685246                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data      3139889                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu3.data      4160679                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      18798692                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       178656                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data        57007                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu2.data        67385                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu3.data        85895                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       388943                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       216992                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        74973                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        70646                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu3.data        88358                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       450969                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       218031                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data        76624                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu2.data        73525                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu3.data        92476                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       460656                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     20279160                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data      6287747                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data      7189458                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu3.data     10865626                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        44621991                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     20457816                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data      6344754                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data      7256843                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu3.data     10951521                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       45010934                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       170890                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data        52219                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data        77937                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu3.data       220468                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       521514                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       112466                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data        34991                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data       102606                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu3.data      1224598                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1474661                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data        53866                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data        19687                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu2.data        19003                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu3.data        42601                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       135157                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         3704                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         2351                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         3769                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu3.data         8092                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        17916                       # number of LoadLockedReq misses
+system.cpu0.dcache.tags.tag_accesses        193157378                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       193157378                       # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.ReadReq_hits::cpu0.data     11470530                       # number of ReadReq hits
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 system.cpu0.dcache.StoreCondReq_misses::cpu0.data            1                       # number of StoreCondReq misses
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-system.cpu0.dcache.StoreCondReq_misses::total           21                       # number of StoreCondReq misses
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-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data    840626000                       # number of ReadReq miss cycles
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-system.cpu0.dcache.ReadReq_miss_latency::total   5326839000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1278551500                       # number of WriteReq miss cycles
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-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     28781500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data     56444000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data    111171000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    196396500                       # number of LoadLockedReq miss cycles
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-system.cpu0.dcache.demand_miss_latency::cpu1.data   2119177500                       # number of demand (read+write) miss cycles
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-system.cpu0.dcache.demand_miss_latency::cpu3.data  64070765820                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  72332277317                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data   2119177500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data   6142333997                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu3.data  64070765820                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  72332277317                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     11637172                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      3654720                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data      4127506                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu3.data      6925415                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     26344813                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      8925344                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      2720237                       # number of WriteReq accesses(hits+misses)
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-system.cpu0.dcache.WriteReq_accesses::cpu3.data      5385277                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     20273353                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       232522                       # number of SoftPFReq accesses(hits+misses)
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-system.cpu0.dcache.SoftPFReq_accesses::cpu2.data        86388                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu3.data       128496                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       524100                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       220696                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        77324                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        74415                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data        96450                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       468885                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       218032                       # number of StoreCondReq accesses(hits+misses)
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-system.cpu0.dcache.demand_accesses::cpu0.data     20562516                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data      6374957                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data      7370001                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu3.data     12310692                       # number of demand (read+write) accesses
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-system.cpu0.dcache.overall_accesses::cpu0.data     20795038                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data      6451651                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data      7456389                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu3.data     12439188                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     47142266                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.014685                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.014288                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.018882                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu3.data     0.031835                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.019796                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.012601                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.012863                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.031644                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu3.data     0.227397                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.072739                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.231660                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.256695                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.219973                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data     0.331536                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.257884                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.016783                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.030405                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.050648                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data     0.083898                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.038210                       # miss rate for LoadLockedReq accesses
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+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1269362500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   5008758996                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu3.data  61128343835                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  67406465331                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     28849500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data     56408000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data    111440000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    196697500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data       509500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total       509500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data   2108136000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data   6144501496                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu3.data  64486614335                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  72739251831                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data   2108136000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data   6144501496                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu3.data  64486614335                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  72739251831                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     11641391                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data      3657022                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data      4130976                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu3.data      6921671                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     26351060                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      8919356                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data      2718660                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data      3246157                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu3.data      5392136                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     20276309                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       232500                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        76400                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu2.data        86511                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu3.data       128522                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       523933                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       220513                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        77416                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        74224                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data        96748                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       468901                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       217843                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        76721                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        73321                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu3.data        92817                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       460702                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     20560747                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data      6375682                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data      7377133                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu3.data     12313807                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     46627369                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     20793247                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data      6452082                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data      7463644                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu3.data     12442329                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     47151302                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.014677                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.014251                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.018892                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu3.data     0.031742                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.019761                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.012590                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.012793                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.031819                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu3.data     0.227450                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.072834                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.232133                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.255223                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.221371                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data     0.330208                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.257781                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.016793                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.030317                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.050900                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data     0.083816                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.038253                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000005                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data     0.000216                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000046                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.013780                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.013680                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.024497                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu3.data     0.117383                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.042820                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.016216                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.016569                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.026762                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu3.data     0.119595                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.045211                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16098.086903                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14546.422110                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 15206.326995                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 10214.182170                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 36539.438713                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 48814.196996                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 49582.195398                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 45437.858814                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12242.237346                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14975.855665                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 13738.383589                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10962.073007                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data        22525                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21452.380952                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 24299.707602                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 34021.446398                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 44337.605217                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 36235.438935                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19824.480575                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30781.544090                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 43067.948553                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 33937.592696                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs       336311                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets        29493                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            12565                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets            679                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    26.765698                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    43.435935                       # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks       691735                       # number of writebacks
-system.cpu0.dcache.writebacks::total           691735                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data          104                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data         3034                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data       108026                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       111164                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        47325                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data      1128149                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1175474                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         1653                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         2318                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data         5313                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total         9284                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data          104                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data        50359                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu3.data      1236175                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1286638                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data          104                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data        50359                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu3.data      1236175                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1286638                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        52115                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data        74903                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data       112442                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       239460                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        34991                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        55281                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data        96449                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       186721                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        19358                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data        15598                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data        29608                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total        64564                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data          698                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         1451                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data         2779                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         4928                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data           20                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total           20                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data        87106                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data       130184                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu3.data       208891                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       426181                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       106464                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data       145782                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu3.data       238499                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       490745                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         3449                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         7107                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data         7761                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        18317                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         2842                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         5190                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data         6229                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        14261                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data         6291                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data        12297                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data        13990                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        32578                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data    786951500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   1017548500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data   1612818000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   3417318000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1243560500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   2630255500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data   4839784419                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   8713600419                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    249854500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data    223680000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data    457627500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total    931162000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data      9093000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     27428500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data     39926500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     76448000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data       430500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       430500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   2030512000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   3647804000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data   6452602419                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  12130918419                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   2280366500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   3871484000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data   6910229919                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  13062080419                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    605119000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data   1489074500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data   1668784000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3762977500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data    605119000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   1489074500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data   1668784000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3762977500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.014260                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.018147                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.016236                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.009089                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.012863                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.017049                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.017910                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.009210                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.252406                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.180557                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data     0.230420                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.123190                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.009027                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.019499                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data     0.028813                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.010510                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data     0.000216                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000043                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.013664                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.017664                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data     0.016968                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.009142                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.016502                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.019551                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data     0.019173                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.010410                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15100.287825                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13584.883115                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 14343.554899                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14270.934603                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35539.438713                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 47579.738066                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 50179.726270                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46666.418983                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12907.041017                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14340.300038                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15456.211159                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14422.309646                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13027.220630                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 18903.170227                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 14367.218424                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15512.987013                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data        21525                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        21525                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23310.816706                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 28020.371167                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 30889.805779                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28464.240356                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21419.132289                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26556.666804                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 28973.831836                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26616.838519                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 175447.665990                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 209522.231603                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 215021.775544                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 205436.343288                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 96188.046416                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 121092.502236                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 119284.060043                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115506.706980                       # average overall mshr uncacheable latency
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements          1969655                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.471697                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           93089501                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1970167                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            47.249548                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      12499304500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   436.731895                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst    12.926501                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst    25.039106                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu3.inst    36.774196                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.852992                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.025247                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.048905                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu3.inst     0.071825                       # Average percentage of cache occupancy
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data     0.000291                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000061                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.013772                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.013629                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.024580                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu3.data     0.117441                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.042840                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.016213                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.016490                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.026861                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu3.data     0.119639                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.045229                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16094.048007                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14553.151549                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 15285.292618                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 10241.080225                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 36496.909143                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 48492.666170                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 49842.098949                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 45643.443333                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12292.074989                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14930.651138                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 13742.754964                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10966.019959                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 18870.370370                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 18196.428571                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 24260.170086                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 33885.741444                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 44592.049720                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 36414.597944                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19814.053160                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30648.797123                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 43320.747109                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 34108.408945                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs       335851                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets        30410                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            12618                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets            677                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    26.616817                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    44.918759                       # average number of cycles each access was blocked
+system.cpu0.dcache.writebacks::writebacks       692039                       # number of writebacks
+system.cpu0.dcache.writebacks::total           692039                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data          103                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data         3007                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data       107263                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       110373                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        47662                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data      1129952                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1177614                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         1644                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         2326                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data         5317                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total         9287                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data          103                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data        50669                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu3.data      1237215                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1287987                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data          103                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data        50669                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu3.data      1237215                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1287987                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        52014                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data        75034                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data       112443                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       239491                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        34780                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        55627                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data        96488                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       186895                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        19172                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data        15769                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data        29454                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total        64395                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data          703                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         1452                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data         2792                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         4947                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data           27                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total           27                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data        86794                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data       130661                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu3.data       208931                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       426386                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       105966                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data       146430                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu3.data       238385                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       490781                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         3424                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         7112                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data         7739                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        18275                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         2828                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         5192                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data         6207                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        14227                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data         6252                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data        12304                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data        13946                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        32502                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data    785366000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   1020201000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data   1616061500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   3421628500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1234582500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   2622763500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data   4843611917                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   8700957917                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    247389500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data    224319000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data    453567500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total    925276000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data      9229000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     27290500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data     39997500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     76517000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data       482500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       482500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   2019948500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   3642964500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data   6459673417                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  12122586417                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   2267338000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   3867283500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data   6913240917                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  13047862417                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    601508000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data   1489621000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data   1663692500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3754821500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data    601508000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   1489621000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data   1663692500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3754821500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.014223                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.018164                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.016245                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.009088                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.012793                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.017136                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.017894                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.009217                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.250942                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.182277                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data     0.229175                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.122907                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.009081                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.019562                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data     0.028858                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.010550                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data     0.000291                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000059                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.013613                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.017712                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data     0.016967                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.009145                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.016424                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.019619                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data     0.019159                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.010409                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15099.127158                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13596.516246                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 14372.273063                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14287.085945                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35496.909143                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 47149.109246                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 50199.111983                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46555.327414                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12903.687670                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14225.315492                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15399.181775                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14368.755338                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13128.022760                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 18795.110193                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 14325.752149                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15467.353952                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 17870.370370                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 17870.370370                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23272.904809                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 27881.039484                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 30917.735602                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28431.014191                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21396.844271                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26410.458922                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 29000.318464                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26585.915952                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 175674.065421                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 209451.771654                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 214975.125985                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 205462.188782                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 96210.492642                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 121068.026658                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 119295.317654                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115525.859947                       # average overall mshr uncacheable latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.tags.replacements          1969505                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.471624                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           93098332                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1970017                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            47.257629                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      12499756500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   436.760332                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst    13.051317                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst    24.695920                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu3.inst    36.964055                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.853048                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.025491                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst     0.048234                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu3.inst     0.072195                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.998968                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          196                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          194                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::2          260                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         97072276                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        97072276                       # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst     56181878                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     17631013                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst      9969832                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu3.inst      9306778                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       93089501                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     56181878                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     17631013                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst      9969832                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu3.inst      9306778                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        93089501                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     56181878                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     17631013                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst      9969832                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu3.inst      9306778                       # number of overall hits
-system.cpu0.icache.overall_hits::total       93089501                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       743688                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       212939                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst       469858                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu3.inst       586089                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      2012574                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       743688                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       212939                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst       469858                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu3.inst       586089                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       2012574                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       743688                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       212939                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst       469858                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu3.inst       586089                       # number of overall misses
-system.cpu0.icache.overall_misses::total      2012574                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2915341500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   6506958500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu3.inst   7959529989                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  17381829989                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst   2915341500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst   6506958500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu3.inst   7959529989                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  17381829989                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst   2915341500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst   6506958500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu3.inst   7959529989                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  17381829989                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     56925566                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     17843952                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst     10439690                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu3.inst      9892867                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     95102075                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     56925566                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     17843952                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst     10439690                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu3.inst      9892867                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     95102075                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     56925566                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     17843952                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst     10439690                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu3.inst      9892867                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     95102075                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.013064                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.011933                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.045007                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu3.inst     0.059244                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.021162                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.013064                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.011933                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst     0.045007                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu3.inst     0.059244                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.021162                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.013064                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.011933                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst     0.045007                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu3.inst     0.059244                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.021162                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13690.970184                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13848.776652                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13580.753075                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  8636.616586                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13690.970184                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13848.776652                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13580.753075                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  8636.616586                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13690.970184                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13848.776652                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13580.753075                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  8636.616586                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         4059                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses         97080848                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        97080848                       # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.ReadReq_hits::cpu0.inst     56184409                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     17633594                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst      9977155                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu3.inst      9303174                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       93098332                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     56184409                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst     17633594                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst      9977155                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu3.inst      9303174                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        93098332                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     56184409                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst     17633594                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst      9977155                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu3.inst      9303174                       # number of overall hits
+system.cpu0.icache.overall_hits::total       93098332                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       744259                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       211927                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst       469274                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu3.inst       586995                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      2012455                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       744259                       # number of demand (read+write) misses
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+system.cpu0.icache.demand_misses::cpu3.inst       586995                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       2012455                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       744259                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       211927                       # number of overall misses
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+system.cpu0.icache.overall_misses::cpu3.inst       586995                       # number of overall misses
+system.cpu0.icache.overall_misses::total      2012455                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2897125000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   6498329500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu3.inst   7981353488                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  17376807988                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst   2897125000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst   6498329500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu3.inst   7981353488                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  17376807988                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst   2897125000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst   6498329500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu3.inst   7981353488                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  17376807988                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     56928668                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst     17845521                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst     10446429                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu3.inst      9890169                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     95110787                       # number of ReadReq accesses(hits+misses)
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+system.cpu0.icache.demand_accesses::cpu1.inst     17845521                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu2.inst     10446429                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu3.inst      9890169                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     95110787                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     56928668                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst     17845521                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst     10446429                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu3.inst      9890169                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     95110787                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.013074                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.011876                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.044922                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu3.inst     0.059351                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.021159                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.013074                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.011876                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst     0.044922                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu3.inst     0.059351                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.021159                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.013074                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.011876                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst     0.044922                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu3.inst     0.059351                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.021159                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13670.391220                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13847.623137                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13596.970141                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  8634.631824                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13670.391220                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13847.623137                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13596.970141                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  8634.631824                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13670.391220                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13847.623137                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13596.970141                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  8634.631824                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         4282                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              214                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              243                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    18.967290                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    17.621399                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks      1969655                       # number of writebacks
-system.cpu0.icache.writebacks::total          1969655                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst        42373                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        42373                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu3.inst        42373                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        42373                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu3.inst        42373                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        42373                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       212939                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       469858                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst       543716                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1226513                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       212939                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst       469858                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu3.inst       543716                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1226513                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       212939                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst       469858                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu3.inst       543716                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1226513                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   2702402500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   6037100500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst   7028496990                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  15767999990                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   2702402500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   6037100500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst   7028496990                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  15767999990                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   2702402500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   6037100500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst   7028496990                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  15767999990                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011933                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.045007                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.054960                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.012897                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.011933                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.045007                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst     0.054960                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.012897                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.011933                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.045007                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst     0.054960                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.012897                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12690.970184                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12848.776652                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12926.779771                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12855.958306                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12690.970184                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12848.776652                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12926.779771                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12855.958306                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12690.970184                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12848.776652                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12926.779771                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12855.958306                       # average overall mshr miss latency
-system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.writebacks::writebacks      1969505                       # number of writebacks
+system.cpu0.icache.writebacks::total          1969505                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst        42394                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        42394                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu3.inst        42394                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        42394                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu3.inst        42394                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        42394                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       211927                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       469274                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst       544601                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1225802                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       211927                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst       469274                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu3.inst       544601                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1225802                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       211927                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst       469274                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu3.inst       544601                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1225802                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   2685198000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   6029055500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst   7046769990                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  15761023490                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   2685198000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   6029055500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst   7046769990                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  15761023490                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   2685198000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   6029055500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst   7046769990                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  15761023490                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011876                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.044922                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.055065                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.012888                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.011876                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.044922                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst     0.055065                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.012888                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.011876                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.044922                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst     0.055065                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.012888                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12670.391220                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12847.623137                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12939.326204                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12857.723751                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12670.391220                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12847.623137                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12939.326204                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12857.723751                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12670.391220                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12847.623137                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12939.326204                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12857.723751                       # average overall mshr miss latency
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1168,63 +1164,61 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.cpu1.dtb.walker.walks                     2014                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort                2014                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1          554                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         1460                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples         2014                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0           2014    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total         2014                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples         1648                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 12287.621359                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 10419.476914                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev  6887.691629                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::2048-4095           15      0.91%      0.91% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::4096-6143          458     27.79%     28.70% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::6144-8191          116      7.04%     35.74% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::10240-12287          507     30.76%     66.50% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::12288-14335          107      6.49%     73.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::14336-16383           75      4.55%     77.55% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-18431           12      0.73%     78.28% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::22528-24575          336     20.39%     98.67% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::24576-26623           22      1.33%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total         1648                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.walker.walks                     2001                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort                2001                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1          565                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         1436                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples         2001                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0           2001    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total         2001                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples         1629                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 10353.898097                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean  9102.917994                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  5277.363913                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::2048-4095           15      0.92%      0.92% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::4096-6143          529     32.47%     33.39% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::6144-8191          134      8.23%     41.62% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::10240-12287          516     31.68%     73.30% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::12288-14335          268     16.45%     89.75% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::14336-16383           35      2.15%     91.90% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::22528-24575          132      8.10%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total         1629                       # Table walker service (enqueue to completion) latency
 system.cpu1.dtb.walker.walksPending::samples   1000016000                       # Table walker pending requests distribution
 system.cpu1.dtb.walker.walksPending::0     1000016000    100.00%    100.00% # Table walker pending requests distribution
 system.cpu1.dtb.walker.walksPending::total   1000016000                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K         1102     66.87%     66.87% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M          546     33.13%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         1648                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         2014                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkPageSizes::4K         1072     65.81%     65.81% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M          557     34.19%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         1629                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         2001                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         2014                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1648                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         2001                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1629                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1648                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total         3662                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1629                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total         3630                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     3812187                       # DTB read hits
-system.cpu1.dtb.read_misses                      1742                       # DTB read misses
-system.cpu1.dtb.write_hits                    2799792                       # DTB write hits
-system.cpu1.dtb.write_misses                      272                       # DTB write misses
-system.cpu1.dtb.flush_tlb                         153                       # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva                     180                       # Number of times TLB was flushed by MVA
+system.cpu1.dtb.read_hits                     3814262                       # DTB read hits
+system.cpu1.dtb.read_misses                      1730                       # DTB read misses
+system.cpu1.dtb.write_hits                    2798296                       # DTB write hits
+system.cpu1.dtb.write_misses                      271                       # DTB write misses
+system.cpu1.dtb.flush_tlb                         154                       # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva                     179                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    1235                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries                    1231                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   241                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   257                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                       89                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 3813929                       # DTB read accesses
-system.cpu1.dtb.write_accesses                2800064                       # DTB write accesses
+system.cpu1.dtb.perms_faults                       87                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                 3815992                       # DTB read accesses
+system.cpu1.dtb.write_accesses                2798567                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                          6611979                       # DTB hits
-system.cpu1.dtb.misses                           2014                       # DTB misses
-system.cpu1.dtb.accesses                      6613993                       # DTB accesses
-system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.hits                          6612558                       # DTB hits
+system.cpu1.dtb.misses                           2001                       # DTB misses
+system.cpu1.dtb.accesses                      6614559                       # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1254,148 +1248,147 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.cpu1.itb.walker.walks                     1033                       # Table walker walks requested
-system.cpu1.itb.walker.walksShort                1033                       # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1          201                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2          832                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples         1033                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0           1033    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total         1033                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples          763                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 12903.669725                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 10877.320310                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev  7130.133618                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::4096-6143          252     33.03%     33.03% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::10240-12287          198     25.95%     58.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::12288-14335           53      6.95%     65.92% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::14336-16383           68      8.91%     74.84% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-18431            1      0.13%     74.97% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::22528-24575          185     24.25%     99.21% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-26623            6      0.79%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total          763                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.cpu1.itb.walker.walks                     1010                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                1010                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1          203                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2          807                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples         1010                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0           1010    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total         1010                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples          742                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 10898.247978                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean  9294.148205                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  6181.528328                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-6143          309     41.64%     41.64% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::6144-8191            2      0.27%     41.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::10240-12287          197     26.55%     68.46% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-14335          117     15.77%     84.23% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::14336-16383           15      2.02%     86.25% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::22528-24575          102     13.75%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total          742                       # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walksPending::samples   1000000500                       # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::0     1000000500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::total   1000000500                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K          562     73.66%     73.66% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M          201     26.34%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total          763                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::4K          539     72.64%     72.64% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          203     27.36%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total          742                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         1033                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total         1033                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         1010                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total         1010                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst          763                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total          763                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total         1796                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    17843952                       # ITB inst hits
-system.cpu1.itb.inst_misses                      1033                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst          742                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total          742                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total         1752                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                    17845521                       # ITB inst hits
+system.cpu1.itb.inst_misses                      1010                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                         153                       # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva                     180                       # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb                         154                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva                     179                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                     730                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                     709                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                17844985                       # ITB inst accesses
-system.cpu1.itb.hits                         17843952                       # DTB hits
-system.cpu1.itb.misses                           1033                       # DTB misses
-system.cpu1.itb.accesses                     17844985                       # DTB accesses
-system.cpu1.numPwrStateTransitions                704                       # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples          352                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean    882103975.423295                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev   11685879500.755745                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::underflows          347     98.58%     98.58% # Distribution of time spent in the clock gated state
+system.cpu1.itb.inst_accesses                17846531                       # ITB inst accesses
+system.cpu1.itb.hits                         17845521                       # DTB hits
+system.cpu1.itb.misses                           1010                       # DTB misses
+system.cpu1.itb.accesses                     17846531                       # DTB accesses
+system.cpu1.numPwrStateTransitions                702                       # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples          351                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean    884610555.122507                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev   11702380509.763947                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows          346     98.58%     98.58% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::1000-5e+10            3      0.85%     99.43% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11            2      0.57%    100.00% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::max_value 156798535501                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total            352                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON   2513250225151                       # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 310500599349                       # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles                       143831015                       # number of cpu cycles simulated
+system.cpu1.pwrStateClkGateDist::max_value 156798063501                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total            351                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON   2513214226652                       # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 310498304848                       # Cumulative time (in ticks) in various power states
+system.cpu1.numCycles                       143755305                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu1.committedInsts                   17251961                       # Number of instructions committed
-system.cpu1.committedOps                     20817165                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             18580086                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                  1666                       # Number of float alu accesses
-system.cpu1.num_func_calls                    1994134                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      2173480                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    18580086                       # number of integer instructions
-system.cpu1.num_fp_insts                         1666                       # number of float instructions
-system.cpu1.num_int_register_reads           34430067                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          13026660                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                1213                       # number of times the floating registers were read
+system.cpu1.committedInsts                   17251469                       # Number of instructions committed
+system.cpu1.committedOps                     20813754                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             18573481                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                  1582                       # Number of float alu accesses
+system.cpu1.num_func_calls                    1994080                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      2178225                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    18573481                       # number of integer instructions
+system.cpu1.num_fp_insts                         1582                       # number of float instructions
+system.cpu1.num_int_register_reads           34424804                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          13020587                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads                1129                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                454                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            75796626                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes            7400275                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                      6814833                       # number of memory refs
-system.cpu1.num_load_insts                    3855659                       # Number of load instructions
-system.cpu1.num_store_insts                   2959174                       # Number of store instructions
-system.cpu1.num_idle_cycles              136834040.067403                       # Number of idle cycles
-system.cpu1.num_busy_cycles              6996974.932597                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.048647                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.951353                       # Percentage of idle cycles
-system.cpu1.Branches                          4280023                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                   48      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 14598901     68.12%     68.12% # Class of executed instruction
-system.cpu1.op_class::IntMult                   16055      0.07%     68.20% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     68.20% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     68.20% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     68.20% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     68.20% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     68.20% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     68.20% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     68.20% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     68.20% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     68.20% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     68.20% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     68.20% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     68.20% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     68.20% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     68.20% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     68.20% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     68.20% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     68.20% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     68.20% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     68.20% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     68.20% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     68.20% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     68.20% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     68.20% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc               990      0.00%     68.20% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     68.20% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     68.20% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     68.20% # Class of executed instruction
-system.cpu1.op_class::MemRead                 3855659     17.99%     86.19% # Class of executed instruction
-system.cpu1.op_class::MemWrite                2959174     13.81%    100.00% # Class of executed instruction
+system.cpu1.num_cc_register_reads            75792524                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes            7403118                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                      6816030                       # number of memory refs
+system.cpu1.num_load_insts                    3857938                       # Number of load instructions
+system.cpu1.num_store_insts                   2958092                       # Number of store instructions
+system.cpu1.num_idle_cycles              136763817.825679                       # Number of idle cycles
+system.cpu1.num_busy_cycles              6991487.174321                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.048635                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.951365                       # Percentage of idle cycles
+system.cpu1.Branches                          4283308                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                   49      0.00%      0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 14594706     68.11%     68.11% # Class of executed instruction
+system.cpu1.op_class::IntMult                   16119      0.08%     68.19% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     68.19% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     68.19% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     68.19% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     68.19% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     68.19% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     68.19% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     68.19% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     68.19% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     68.19% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     68.19% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     68.19% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     68.19% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     68.19% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     68.19% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     68.19% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     68.19% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     68.19% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     68.19% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     68.19% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     68.19% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     68.19% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     68.19% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     68.19% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc               983      0.00%     68.19% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     68.19% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     68.19% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     68.19% # Class of executed instruction
+system.cpu1.op_class::MemRead                 3857938     18.00%     86.20% # Class of executed instruction
+system.cpu1.op_class::MemWrite                2958092     13.80%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  21430827                       # Class of executed instruction
-system.cpu2.branchPred.lookups                5563915                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted          2829451                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect           493242                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups             3244476                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits                1661186                       # Number of BTB hits
+system.cpu1.op_class::total                  21427887                       # Class of executed instruction
+system.cpu2.branchPred.lookups                5563559                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted          2831152                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect           495188                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups             3274111                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits                1663178                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            51.200440                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                1571960                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect            328162                       # Number of incorrect RAS predictions.
-system.cpu2.branchPred.indirectLookups         674670                       # Number of indirect predictor lookups.
-system.cpu2.branchPred.indirectHits            641704                       # Number of indirect target hits.
-system.cpu2.branchPred.indirectMisses           32966                       # Number of indirect misses.
-system.cpu2.branchPredindirectMispredicted        22004                       # Number of mispredicted indirect branches.
-system.cpu2.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
+system.cpu2.branchPred.BTBHitPct            50.797850                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                1571133                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect            329841                       # Number of incorrect RAS predictions.
+system.cpu2.branchPred.indirectLookups         676012                       # Number of indirect predictor lookups.
+system.cpu2.branchPred.indirectHits            643238                       # Number of indirect target hits.
+system.cpu2.branchPred.indirectMisses           32774                       # Number of indirect misses.
+system.cpu2.branchPredindirectMispredicted        22078                       # Number of mispredicted indirect branches.
+system.cpu2.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
 system.cpu2.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1425,59 +1418,58 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu2.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu2.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu2.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu2.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.cpu2.dtb.walker.walks                    11911                       # Table walker walks requested
-system.cpu2.dtb.walker.walksShort               11911                       # Table walker walks initiated with short descriptors
-system.cpu2.dtb.walker.walksShortTerminationLevel::Level1         7385                       # Level at which table walker walks with short descriptors terminate
-system.cpu2.dtb.walker.walksShortTerminationLevel::Level2         4526                       # Level at which table walker walks with short descriptors terminate
-system.cpu2.dtb.walker.walkWaitTime::samples        11911                       # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::0          11911    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::total        11911                       # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkCompletionTime::samples         2027                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::mean 12784.410459                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::gmean 11026.371953                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::stdev  6894.594481                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::0-8191          547     26.99%     26.99% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::8192-16383         1059     52.24%     79.23% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::16384-24575          401     19.78%     99.01% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::24576-32767           18      0.89%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::81920-90111            2      0.10%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::total         2027                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.cpu2.dtb.walker.walks                    12042                       # Table walker walks requested
+system.cpu2.dtb.walker.walksShort               12042                       # Table walker walks initiated with short descriptors
+system.cpu2.dtb.walker.walksShortTerminationLevel::Level1         7406                       # Level at which table walker walks with short descriptors terminate
+system.cpu2.dtb.walker.walksShortTerminationLevel::Level2         4636                       # Level at which table walker walks with short descriptors terminate
+system.cpu2.dtb.walker.walkWaitTime::samples        12042                       # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::0          12042    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::total        12042                       # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkCompletionTime::samples         2043                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::mean 11062.897699                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::gmean  9694.627890                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::stdev  6045.581336                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::0-8191          687     33.63%     33.63% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::8192-16383         1153     56.44%     90.06% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::16384-24575          200      9.79%     99.85% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::81920-90111            3      0.15%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::total         2043                       # Table walker service (enqueue to completion) latency
 system.cpu2.dtb.walker.walksPending::samples   2000042500                       # Table walker pending requests distribution
 system.cpu2.dtb.walker.walksPending::0     2000042500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu2.dtb.walker.walksPending::total   2000042500                       # Table walker pending requests distribution
-system.cpu2.dtb.walker.walkPageSizes::4K         1245     61.42%     61.42% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::1M          782     38.58%    100.00% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::total         2027                       # Table walker page sizes translated
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data        11911                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkPageSizes::4K         1264     61.87%     61.87% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::1M          779     38.13%    100.00% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::total         2043                       # Table walker page sizes translated
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data        12042                       # Table walker requests started/completed, data/inst
 system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::total        11911                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data         2027                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::total        12042                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data         2043                       # Table walker requests started/completed, data/inst
 system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::total         2027                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin::total        13938                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::total         2043                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin::total        14085                       # Table walker requests started/completed, data/inst
 system.cpu2.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu2.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu2.dtb.read_hits                     4327855                       # DTB read hits
-system.cpu2.dtb.read_misses                     10705                       # DTB read misses
-system.cpu2.dtb.write_hits                    3342614                       # DTB write hits
-system.cpu2.dtb.write_misses                     1206                       # DTB write misses
-system.cpu2.dtb.flush_tlb                         153                       # Number of times complete TLB was flushed
-system.cpu2.dtb.flush_tlb_mva                     143                       # Number of times TLB was flushed by MVA
+system.cpu2.dtb.read_hits                     4331167                       # DTB read hits
+system.cpu2.dtb.read_misses                     10867                       # DTB read misses
+system.cpu2.dtb.write_hits                    3346265                       # DTB write hits
+system.cpu2.dtb.write_misses                     1175                       # DTB write misses
+system.cpu2.dtb.flush_tlb                         152                       # Number of times complete TLB was flushed
+system.cpu2.dtb.flush_tlb_mva                     151                       # Number of times TLB was flushed by MVA
 system.cpu2.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu2.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu2.dtb.flush_entries                    1399                       # Number of entries that have been flushed from TLB
-system.cpu2.dtb.align_faults                      245                       # Number of TLB faults due to alignment restrictions
-system.cpu2.dtb.prefetch_faults                   301                       # Number of TLB faults due to prefetch
+system.cpu2.dtb.flush_entries                    1411                       # Number of entries that have been flushed from TLB
+system.cpu2.dtb.align_faults                      255                       # Number of TLB faults due to alignment restrictions
+system.cpu2.dtb.prefetch_faults                   303                       # Number of TLB faults due to prefetch
 system.cpu2.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.dtb.perms_faults                      123                       # Number of TLB faults due to permissions restrictions
-system.cpu2.dtb.read_accesses                 4338560                       # DTB read accesses
-system.cpu2.dtb.write_accesses                3343820                       # DTB write accesses
+system.cpu2.dtb.perms_faults                      127                       # Number of TLB faults due to permissions restrictions
+system.cpu2.dtb.read_accesses                 4342034                       # DTB read accesses
+system.cpu2.dtb.write_accesses                3347440                       # DTB write accesses
 system.cpu2.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu2.dtb.hits                          7670469                       # DTB hits
-system.cpu2.dtb.misses                          11911                       # DTB misses
-system.cpu2.dtb.accesses                      7682380                       # DTB accesses
-system.cpu2.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
+system.cpu2.dtb.hits                          7677432                       # DTB hits
+system.cpu2.dtb.misses                          12042                       # DTB misses
+system.cpu2.dtb.accesses                      7689474                       # DTB accesses
+system.cpu2.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
 system.cpu2.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1507,66 +1499,66 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu2.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu2.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu2.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu2.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.cpu2.itb.walker.walks                     1348                       # Table walker walks requested
-system.cpu2.itb.walker.walksShort                1348                       # Table walker walks initiated with short descriptors
-system.cpu2.itb.walker.walksShortTerminationLevel::Level1          252                       # Level at which table walker walks with short descriptors terminate
-system.cpu2.itb.walker.walksShortTerminationLevel::Level2         1096                       # Level at which table walker walks with short descriptors terminate
-system.cpu2.itb.walker.walkWaitTime::samples         1348                       # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::0           1348    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::total         1348                       # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkCompletionTime::samples          848                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::mean 13074.292453                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::gmean 11434.302344                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::stdev  6448.856060                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::4096-6143          240     28.30%     28.30% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::6144-8191            2      0.24%     28.54% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::10240-12287          241     28.42%     56.96% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::12288-14335           61      7.19%     64.15% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::14336-16383          126     14.86%     79.01% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::22528-24575          176     20.75%     99.76% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::24576-26623            2      0.24%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::total          848                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.cpu2.itb.walker.walks                     1330                       # Table walker walks requested
+system.cpu2.itb.walker.walksShort                1330                       # Table walker walks initiated with short descriptors
+system.cpu2.itb.walker.walksShortTerminationLevel::Level1          245                       # Level at which table walker walks with short descriptors terminate
+system.cpu2.itb.walker.walksShortTerminationLevel::Level2         1085                       # Level at which table walker walks with short descriptors terminate
+system.cpu2.itb.walker.walkWaitTime::samples         1330                       # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::0           1330    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::total         1330                       # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkCompletionTime::samples          845                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::mean 11181.065089                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::gmean  9687.789458                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::stdev  6060.643085                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::4096-6143          346     40.95%     40.95% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::6144-8191            3      0.36%     41.30% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::10240-12287          226     26.75%     68.05% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::12288-14335           99     11.72%     79.76% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::14336-16383           48      5.68%     85.44% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::22528-24575          122     14.44%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::24576-26623            1      0.12%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::total          845                       # Table walker service (enqueue to completion) latency
 system.cpu2.itb.walker.walksPending::samples   2000028000                       # Table walker pending requests distribution
 system.cpu2.itb.walker.walksPending::0     2000028000    100.00%    100.00% # Table walker pending requests distribution
 system.cpu2.itb.walker.walksPending::total   2000028000                       # Table walker pending requests distribution
-system.cpu2.itb.walker.walkPageSizes::4K          600     70.75%     70.75% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::1M          248     29.25%    100.00% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::total          848                       # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::4K          603     71.36%     71.36% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::1M          242     28.64%    100.00% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::total          845                       # Table walker page sizes translated
 system.cpu2.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst         1348                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::total         1348                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst         1330                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::total         1330                       # Table walker requests started/completed, data/inst
 system.cpu2.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst          848                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::total          848                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin::total         2196                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.inst_hits                    10441487                       # ITB inst hits
-system.cpu2.itb.inst_misses                      1348                       # ITB inst misses
+system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst          845                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Completed::total          845                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin::total         2175                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.inst_hits                    10448237                       # ITB inst hits
+system.cpu2.itb.inst_misses                      1330                       # ITB inst misses
 system.cpu2.itb.read_hits                           0                       # DTB read hits
 system.cpu2.itb.read_misses                         0                       # DTB read misses
 system.cpu2.itb.write_hits                          0                       # DTB write hits
 system.cpu2.itb.write_misses                        0                       # DTB write misses
-system.cpu2.itb.flush_tlb                         153                       # Number of times complete TLB was flushed
-system.cpu2.itb.flush_tlb_mva                     143                       # Number of times TLB was flushed by MVA
+system.cpu2.itb.flush_tlb                         152                       # Number of times complete TLB was flushed
+system.cpu2.itb.flush_tlb_mva                     151                       # Number of times TLB was flushed by MVA
 system.cpu2.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu2.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu2.itb.flush_entries                     821                       # Number of entries that have been flushed from TLB
+system.cpu2.itb.flush_entries                     823                       # Number of entries that have been flushed from TLB
 system.cpu2.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu2.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu2.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.itb.perms_faults                     1710                       # Number of TLB faults due to permissions restrictions
+system.cpu2.itb.perms_faults                     1725                       # Number of TLB faults due to permissions restrictions
 system.cpu2.itb.read_accesses                       0                       # DTB read accesses
 system.cpu2.itb.write_accesses                      0                       # DTB write accesses
-system.cpu2.itb.inst_accesses                10442835                       # ITB inst accesses
-system.cpu2.itb.hits                         10441487                       # DTB hits
-system.cpu2.itb.misses                           1348                       # DTB misses
-system.cpu2.itb.accesses                     10442835                       # DTB accesses
-system.cpu2.numPwrStateTransitions               1074                       # Number of power state transitions
-system.cpu2.pwrStateClkGateDist::samples          537                       # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::mean    5095328839.376163                       # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::stdev   41281959005.190056                       # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::underflows          492     91.62%     91.62% # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::1000-5e+10           38      7.08%     98.70% # Distribution of time spent in the clock gated state
+system.cpu2.itb.inst_accesses                10449567                       # ITB inst accesses
+system.cpu2.itb.hits                         10448237                       # DTB hits
+system.cpu2.itb.misses                           1330                       # DTB misses
+system.cpu2.itb.accesses                     10449567                       # DTB accesses
+system.cpu2.numPwrStateTransitions               1076                       # Number of power state transitions
+system.cpu2.pwrStateClkGateDist::samples          538                       # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::mean    5085855532.985130                       # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::stdev   41244061935.633728                       # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::underflows          493     91.64%     91.64% # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::1000-5e+10           38      7.06%     98.70% # Distribution of time spent in the clock gated state
 system.cpu2.pwrStateClkGateDist::5e+10-1e+11            1      0.19%     98.88% # Distribution of time spent in the clock gated state
 system.cpu2.pwrStateClkGateDist::1.5e+11-2e+11            1      0.19%     99.07% # Distribution of time spent in the clock gated state
 system.cpu2.pwrStateClkGateDist::2e+11-2.5e+11            1      0.19%     99.26% # Distribution of time spent in the clock gated state
@@ -1574,73 +1566,73 @@ system.cpu2.pwrStateClkGateDist::2.5e+11-3e+11            1      0.19%     99.44
 system.cpu2.pwrStateClkGateDist::4.5e+11-5e+11            2      0.37%     99.81% # Distribution of time spent in the clock gated state
 system.cpu2.pwrStateClkGateDist::5e+11-5.5e+11            1      0.19%    100.00% # Distribution of time spent in the clock gated state
 system.cpu2.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::max_value 500052269001                       # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::total            537                       # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateResidencyTicks::ON    87559237755                       # Cumulative time (in ticks) in various power states
-system.cpu2.pwrStateResidencyTicks::CLK_GATED 2736191586745                       # Cumulative time (in ticks) in various power states
-system.cpu2.numCycles                       141974504                       # number of cpu cycles simulated
+system.cpu2.pwrStateClkGateDist::max_value 500051113501                       # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::total            538                       # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateResidencyTicks::ON    87522254754                       # Cumulative time (in ticks) in various power states
+system.cpu2.pwrStateResidencyTicks::CLK_GATED 2736190276746                       # Cumulative time (in ticks) in various power states
+system.cpu2.numCycles                       141975261                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.committedInsts                   19185413                       # Number of instructions committed
-system.cpu2.committedOps                     23254826                       # Number of ops (including micro ops) committed
-system.cpu2.discardedOps                      1388377                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu2.numFetchSuspends                      540                       # Number of times Execute suspended instruction fetching
-system.cpu2.quiesceCycles                       36744                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.cpi                              7.400128                       # CPI: cycles per instruction
-system.cpu2.ipc                              0.135133                       # IPC: instructions per cycle
-system.cpu2.op_class_0::No_OpClass                 50      0.00%      0.00% # Class of committed instruction
-system.cpu2.op_class_0::IntAlu               15529839     66.78%     66.78% # Class of committed instruction
-system.cpu2.op_class_0::IntMult                 18571      0.08%     66.86% # Class of committed instruction
-system.cpu2.op_class_0::IntDiv                      0      0.00%     66.86% # Class of committed instruction
-system.cpu2.op_class_0::FloatAdd                    0      0.00%     66.86% # Class of committed instruction
-system.cpu2.op_class_0::FloatCmp                    0      0.00%     66.86% # Class of committed instruction
-system.cpu2.op_class_0::FloatCvt                    0      0.00%     66.86% # Class of committed instruction
-system.cpu2.op_class_0::FloatMult                   0      0.00%     66.86% # Class of committed instruction
-system.cpu2.op_class_0::FloatDiv                    0      0.00%     66.86% # Class of committed instruction
-system.cpu2.op_class_0::FloatSqrt                   0      0.00%     66.86% # Class of committed instruction
-system.cpu2.op_class_0::SimdAdd                     0      0.00%     66.86% # Class of committed instruction
-system.cpu2.op_class_0::SimdAddAcc                  0      0.00%     66.86% # Class of committed instruction
-system.cpu2.op_class_0::SimdAlu                     0      0.00%     66.86% # Class of committed instruction
-system.cpu2.op_class_0::SimdCmp                     0      0.00%     66.86% # Class of committed instruction
-system.cpu2.op_class_0::SimdCvt                     0      0.00%     66.86% # Class of committed instruction
-system.cpu2.op_class_0::SimdMisc                    0      0.00%     66.86% # Class of committed instruction
-system.cpu2.op_class_0::SimdMult                    0      0.00%     66.86% # Class of committed instruction
-system.cpu2.op_class_0::SimdMultAcc                 0      0.00%     66.86% # Class of committed instruction
-system.cpu2.op_class_0::SimdShift                   0      0.00%     66.86% # Class of committed instruction
-system.cpu2.op_class_0::SimdShiftAcc                0      0.00%     66.86% # Class of committed instruction
-system.cpu2.op_class_0::SimdSqrt                    0      0.00%     66.86% # Class of committed instruction
-system.cpu2.op_class_0::SimdFloatAdd                0      0.00%     66.86% # Class of committed instruction
-system.cpu2.op_class_0::SimdFloatAlu                0      0.00%     66.86% # Class of committed instruction
-system.cpu2.op_class_0::SimdFloatCmp                0      0.00%     66.86% # Class of committed instruction
-system.cpu2.op_class_0::SimdFloatCvt                0      0.00%     66.86% # Class of committed instruction
-system.cpu2.op_class_0::SimdFloatDiv                0      0.00%     66.86% # Class of committed instruction
-system.cpu2.op_class_0::SimdFloatMisc            1326      0.01%     66.87% # Class of committed instruction
-system.cpu2.op_class_0::SimdFloatMult               0      0.00%     66.87% # Class of committed instruction
-system.cpu2.op_class_0::SimdFloatMultAcc            0      0.00%     66.87% # Class of committed instruction
-system.cpu2.op_class_0::SimdFloatSqrt               0      0.00%     66.87% # Class of committed instruction
-system.cpu2.op_class_0::MemRead               4244552     18.25%     85.12% # Class of committed instruction
-system.cpu2.op_class_0::MemWrite              3460488     14.88%    100.00% # Class of committed instruction
+system.cpu2.committedInsts                   19207075                       # Number of instructions committed
+system.cpu2.committedOps                     23282264                       # Number of ops (including micro ops) committed
+system.cpu2.discardedOps                      1390064                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu2.numFetchSuspends                      541                       # Number of times Execute suspended instruction fetching
+system.cpu2.quiesceCycles                       36123                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.cpi                              7.391821                       # CPI: cycles per instruction
+system.cpu2.ipc                              0.135285                       # IPC: instructions per cycle
+system.cpu2.op_class_0::No_OpClass                 48      0.00%      0.00% # Class of committed instruction
+system.cpu2.op_class_0::IntAlu               15551874     66.80%     66.80% # Class of committed instruction
+system.cpu2.op_class_0::IntMult                 18578      0.08%     66.88% # Class of committed instruction
+system.cpu2.op_class_0::IntDiv                      0      0.00%     66.88% # Class of committed instruction
+system.cpu2.op_class_0::FloatAdd                    0      0.00%     66.88% # Class of committed instruction
+system.cpu2.op_class_0::FloatCmp                    0      0.00%     66.88% # Class of committed instruction
+system.cpu2.op_class_0::FloatCvt                    0      0.00%     66.88% # Class of committed instruction
+system.cpu2.op_class_0::FloatMult                   0      0.00%     66.88% # Class of committed instruction
+system.cpu2.op_class_0::FloatDiv                    0      0.00%     66.88% # Class of committed instruction
+system.cpu2.op_class_0::FloatSqrt                   0      0.00%     66.88% # Class of committed instruction
+system.cpu2.op_class_0::SimdAdd                     0      0.00%     66.88% # Class of committed instruction
+system.cpu2.op_class_0::SimdAddAcc                  0      0.00%     66.88% # Class of committed instruction
+system.cpu2.op_class_0::SimdAlu                     0      0.00%     66.88% # Class of committed instruction
+system.cpu2.op_class_0::SimdCmp                     0      0.00%     66.88% # Class of committed instruction
+system.cpu2.op_class_0::SimdCvt                     0      0.00%     66.88% # Class of committed instruction
+system.cpu2.op_class_0::SimdMisc                    0      0.00%     66.88% # Class of committed instruction
+system.cpu2.op_class_0::SimdMult                    0      0.00%     66.88% # Class of committed instruction
+system.cpu2.op_class_0::SimdMultAcc                 0      0.00%     66.88% # Class of committed instruction
+system.cpu2.op_class_0::SimdShift                   0      0.00%     66.88% # Class of committed instruction
+system.cpu2.op_class_0::SimdShiftAcc                0      0.00%     66.88% # Class of committed instruction
+system.cpu2.op_class_0::SimdSqrt                    0      0.00%     66.88% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatAdd                0      0.00%     66.88% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatAlu                0      0.00%     66.88% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatCmp                0      0.00%     66.88% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatCvt                0      0.00%     66.88% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatDiv                0      0.00%     66.88% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatMisc            1338      0.01%     66.88% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatMult               0      0.00%     66.88% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatMultAcc            0      0.00%     66.88% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatSqrt               0      0.00%     66.88% # Class of committed instruction
+system.cpu2.op_class_0::MemRead               4246805     18.24%     85.12% # Class of committed instruction
+system.cpu2.op_class_0::MemWrite              3463621     14.88%    100.00% # Class of committed instruction
 system.cpu2.op_class_0::IprAccess                   0      0.00%    100.00% # Class of committed instruction
 system.cpu2.op_class_0::InstPrefetch                0      0.00%    100.00% # Class of committed instruction
-system.cpu2.op_class_0::total                23254826                       # Class of committed instruction
+system.cpu2.op_class_0::total                23282264                       # Class of committed instruction
 system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu2.tickCycles                       38692637                       # Number of cycles that the object actually ticked
-system.cpu2.idleCycles                      103281867                       # Total number of cycles that the object has spent stopped
-system.cpu3.branchPred.lookups               13574263                       # Number of BP lookups
-system.cpu3.branchPred.condPredicted          7472946                       # Number of conditional branches predicted
-system.cpu3.branchPred.condIncorrect           296816                       # Number of conditional branches incorrect
-system.cpu3.branchPred.BTBLookups             8409244                       # Number of BTB lookups
-system.cpu3.branchPred.BTBHits                4443267                       # Number of BTB hits
+system.cpu2.tickCycles                       38700481                       # Number of cycles that the object actually ticked
+system.cpu2.idleCycles                      103274780                       # Total number of cycles that the object has spent stopped
+system.cpu3.branchPred.lookups               13558463                       # Number of BP lookups
+system.cpu3.branchPred.condPredicted          7461726                       # Number of conditional branches predicted
+system.cpu3.branchPred.condIncorrect           297292                       # Number of conditional branches incorrect
+system.cpu3.branchPred.BTBLookups             8389979                       # Number of BTB lookups
+system.cpu3.branchPred.BTBHits                4437676                       # Number of BTB hits
 system.cpu3.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.branchPred.BTBHitPct            52.837889                       # BTB Hit Percentage
-system.cpu3.branchPred.usedRAS                3091382                       # Number of times the RAS was used to get a target.
-system.cpu3.branchPred.RASInCorrect             16244                       # Number of incorrect RAS predictions.
-system.cpu3.branchPred.indirectLookups        2018293                       # Number of indirect predictor lookups.
-system.cpu3.branchPred.indirectHits           1956673                       # Number of indirect target hits.
-system.cpu3.branchPred.indirectMisses           61620                       # Number of indirect misses.
-system.cpu3.branchPredindirectMispredicted        18086                       # Number of mispredicted indirect branches.
-system.cpu3.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
+system.cpu3.branchPred.BTBHitPct            52.892576                       # BTB Hit Percentage
+system.cpu3.branchPred.usedRAS                3087767                       # Number of times the RAS was used to get a target.
+system.cpu3.branchPred.RASInCorrect             16069                       # Number of incorrect RAS predictions.
+system.cpu3.branchPred.indirectLookups        2015433                       # Number of indirect predictor lookups.
+system.cpu3.branchPred.indirectHits           1953316                       # Number of indirect target hits.
+system.cpu3.branchPred.indirectMisses           62117                       # Number of indirect misses.
+system.cpu3.branchPredindirectMispredicted        18167                       # Number of mispredicted indirect branches.
+system.cpu3.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
 system.cpu3.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1670,92 +1662,93 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu3.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu3.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu3.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu3.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.cpu3.dtb.walker.walks                    34289                       # Table walker walks requested
-system.cpu3.dtb.walker.walksShort               34289                       # Table walker walks initiated with short descriptors
-system.cpu3.dtb.walker.walksShortTerminationLevel::Level1        10988                       # Level at which table walker walks with short descriptors terminate
-system.cpu3.dtb.walker.walksShortTerminationLevel::Level2         8074                       # Level at which table walker walks with short descriptors terminate
-system.cpu3.dtb.walker.walksSquashedBefore        15227                       # Table walks squashed before starting
-system.cpu3.dtb.walker.walkWaitTime::samples        19062                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::mean   480.983108                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::stdev  2977.429006                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::0-8191        18630     97.73%     97.73% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::8192-16383          285      1.50%     99.23% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::16384-24575           92      0.48%     99.71% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::24576-32767           31      0.16%     99.87% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::32768-40959            6      0.03%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::40960-49151           14      0.07%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::49152-57343            2      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::57344-65535            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::65536-73727            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::total        19062                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkCompletionTime::samples         6433                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::mean 11737.913882                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::gmean  9614.193609                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::stdev  7621.962559                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::0-8191         2432     37.81%     37.81% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::8192-16383         2842     44.18%     81.98% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::16384-24575          955     14.85%     96.83% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::24576-32767          108      1.68%     98.51% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::32768-40959           45      0.70%     99.21% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::40960-49151           39      0.61%     99.81% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::49152-57343            6      0.09%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::57344-65535            1      0.02%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::65536-73727            2      0.03%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::81920-90111            3      0.05%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::total         6433                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walksPending::samples  -8544248564                       # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::mean     0.589102                       # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::stdev     0.347038                       # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::0-1  -8589968064    100.54%    100.54% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::2-3     32103000     -0.38%    100.16% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::4-5      6761500     -0.08%    100.08% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::6-7      2522000     -0.03%    100.05% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::8-9      1641500     -0.02%    100.03% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::10-11       647000     -0.01%    100.02% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::12-13       437000     -0.01%    100.02% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::14-15       926500     -0.01%    100.01% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::16-17       267500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::18-19       118000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::20-21        41000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::22-23        32500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::24-25        26000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::26-27        29500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::28-29         9000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::30-31       157500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::total  -8544248564                       # Table walker pending requests distribution
-system.cpu3.dtb.walker.walkPageSizes::4K         1826     71.78%     71.78% # Table walker page sizes translated
-system.cpu3.dtb.walker.walkPageSizes::1M          718     28.22%    100.00% # Table walker page sizes translated
-system.cpu3.dtb.walker.walkPageSizes::total         2544                       # Table walker page sizes translated
-system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data        34289                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.cpu3.dtb.walker.walks                    34483                       # Table walker walks requested
+system.cpu3.dtb.walker.walksShort               34483                       # Table walker walks initiated with short descriptors
+system.cpu3.dtb.walker.walksShortTerminationLevel::Level1        10978                       # Level at which table walker walks with short descriptors terminate
+system.cpu3.dtb.walker.walksShortTerminationLevel::Level2         8165                       # Level at which table walker walks with short descriptors terminate
+system.cpu3.dtb.walker.walksSquashedBefore        15340                       # Table walks squashed before starting
+system.cpu3.dtb.walker.walkWaitTime::samples        19143                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::mean   456.015254                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::stdev  2830.743841                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::0-8191        18720     97.79%     97.79% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::8192-16383          307      1.60%     99.39% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::16384-24575           66      0.34%     99.74% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::24576-32767           32      0.17%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::32768-40959            6      0.03%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::40960-49151            8      0.04%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::49152-57343            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::65536-73727            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::73728-81919            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::81920-90111            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::total        19143                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkCompletionTime::samples         6521                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::mean 10311.301948                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::gmean  8555.831863                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::stdev  6751.449027                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::0-8191         2865     43.93%     43.93% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::8192-16383         2966     45.48%     89.42% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::16384-24575          551      8.45%     97.87% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::24576-32767           84      1.29%     99.16% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::32768-40959           31      0.48%     99.63% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::40960-49151           17      0.26%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::57344-65535            1      0.02%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::81920-90111            3      0.05%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::90112-98303            2      0.03%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::98304-106495            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::total         6521                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walksPending::samples  -8545598564                       # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::mean     0.743431                       # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::stdev     0.275134                       # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::0-1  -8589277064    100.51%    100.51% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::2-3     31465000     -0.37%    100.14% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::4-5      6055500     -0.07%    100.07% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::6-7      2113000     -0.02%    100.05% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::8-9      1651500     -0.02%    100.03% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::10-11       591000     -0.01%    100.02% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::12-13       384000     -0.00%    100.02% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::14-15       739000     -0.01%    100.01% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::16-17       231000     -0.00%    100.01% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::18-19       112500     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::20-21        46500     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::22-23        31000     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::24-25        29500     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::26-27        22000     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::28-29        12000     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::30-31       195000     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::total  -8545598564                       # Table walker pending requests distribution
+system.cpu3.dtb.walker.walkPageSizes::4K         1839     71.81%     71.81% # Table walker page sizes translated
+system.cpu3.dtb.walker.walkPageSizes::1M          722     28.19%    100.00% # Table walker page sizes translated
+system.cpu3.dtb.walker.walkPageSizes::total         2561                       # Table walker page sizes translated
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data        34483                       # Table walker requests started/completed, data/inst
 system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Requested::total        34289                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data         2544                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::total        34483                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data         2561                       # Table walker requests started/completed, data/inst
 system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Completed::total         2544                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin::total        36833                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Completed::total         2561                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin::total        37044                       # Table walker requests started/completed, data/inst
 system.cpu3.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu3.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu3.dtb.read_hits                     7476077                       # DTB read hits
-system.cpu3.dtb.read_misses                     28705                       # DTB read misses
-system.cpu3.dtb.write_hits                    5707301                       # DTB write hits
-system.cpu3.dtb.write_misses                     5584                       # DTB write misses
+system.cpu3.dtb.read_hits                     7471341                       # DTB read hits
+system.cpu3.dtb.read_misses                     28725                       # DTB read misses
+system.cpu3.dtb.write_hits                    5714088                       # DTB write hits
+system.cpu3.dtb.write_misses                     5758                       # DTB write misses
 system.cpu3.dtb.flush_tlb                         157                       # Number of times complete TLB was flushed
-system.cpu3.dtb.flush_tlb_mva                     231                       # Number of times TLB was flushed by MVA
+system.cpu3.dtb.flush_tlb_mva                     225                       # Number of times TLB was flushed by MVA
 system.cpu3.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu3.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu3.dtb.flush_entries                    1654                       # Number of entries that have been flushed from TLB
-system.cpu3.dtb.align_faults                      379                       # Number of TLB faults due to alignment restrictions
-system.cpu3.dtb.prefetch_faults                   711                       # Number of TLB faults due to prefetch
+system.cpu3.dtb.flush_entries                    1650                       # Number of entries that have been flushed from TLB
+system.cpu3.dtb.align_faults                      393                       # Number of TLB faults due to alignment restrictions
+system.cpu3.dtb.prefetch_faults                   706                       # Number of TLB faults due to prefetch
 system.cpu3.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu3.dtb.perms_faults                      337                       # Number of TLB faults due to permissions restrictions
-system.cpu3.dtb.read_accesses                 7504782                       # DTB read accesses
-system.cpu3.dtb.write_accesses                5712885                       # DTB write accesses
+system.cpu3.dtb.perms_faults                      319                       # Number of TLB faults due to permissions restrictions
+system.cpu3.dtb.read_accesses                 7500066                       # DTB read accesses
+system.cpu3.dtb.write_accesses                5719846                       # DTB write accesses
 system.cpu3.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu3.dtb.hits                         13183378                       # DTB hits
-system.cpu3.dtb.misses                          34289                       # DTB misses
-system.cpu3.dtb.accesses                     13217667                       # DTB accesses
-system.cpu3.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
+system.cpu3.dtb.hits                         13185429                       # DTB hits
+system.cpu3.dtb.misses                          34483                       # DTB misses
+system.cpu3.dtb.accesses                     13219912                       # DTB accesses
+system.cpu3.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
 system.cpu3.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1785,220 +1778,221 @@ system.cpu3.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu3.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu3.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu3.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu3.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.cpu3.itb.walker.walks                     4253                       # Table walker walks requested
-system.cpu3.itb.walker.walksShort                4253                       # Table walker walks initiated with short descriptors
-system.cpu3.itb.walker.walksShortTerminationLevel::Level1         1354                       # Level at which table walker walks with short descriptors terminate
+system.cpu3.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.cpu3.itb.walker.walks                     4240                       # Table walker walks requested
+system.cpu3.itb.walker.walksShort                4240                       # Table walker walks initiated with short descriptors
+system.cpu3.itb.walker.walksShortTerminationLevel::Level1         1366                       # Level at which table walker walks with short descriptors terminate
 system.cpu3.itb.walker.walksShortTerminationLevel::Level2         2463                       # Level at which table walker walks with short descriptors terminate
-system.cpu3.itb.walker.walksSquashedBefore          436                       # Table walks squashed before starting
-system.cpu3.itb.walker.walkWaitTime::samples         3817                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::mean  1262.509824                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::stdev  4945.350323                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::0-8191         3591     94.08%     94.08% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::8192-16383          162      4.24%     98.32% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::16384-24575           27      0.71%     99.03% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::24576-32767           17      0.45%     99.48% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::32768-40959            8      0.21%     99.69% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::40960-49151            6      0.16%     99.84% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::49152-57343            1      0.03%     99.87% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::57344-65535            4      0.10%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::73728-81919            1      0.03%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::total         3817                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkCompletionTime::samples         1618                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::mean 11355.377009                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::gmean  9318.464391                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::stdev  7299.331906                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::0-8191          704     43.51%     43.51% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::8192-16383          629     38.88%     82.39% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::16384-24575          254     15.70%     98.08% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::24576-32767           19      1.17%     99.26% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::32768-40959            8      0.49%     99.75% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::40960-49151            2      0.12%     99.88% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::49152-57343            1      0.06%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walksSquashedBefore          411                       # Table walks squashed before starting
+system.cpu3.itb.walker.walkWaitTime::samples         3829                       # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::mean  1196.395926                       # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::stdev  4662.983981                       # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::0-8191         3612     94.33%     94.33% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::8192-16383          152      3.97%     98.30% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::16384-24575           35      0.91%     99.22% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::24576-32767           19      0.50%     99.71% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::32768-40959            3      0.08%     99.79% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::40960-49151            2      0.05%     99.84% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::49152-57343            2      0.05%     99.90% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::57344-65535            1      0.03%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::65536-73727            2      0.05%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::81920-90111            1      0.03%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::total         3829                       # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkCompletionTime::samples         1597                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::mean 10150.594865                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::gmean  8236.395815                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::stdev  7276.129645                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::0-8191          852     53.35%     53.35% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::8192-16383          514     32.19%     85.54% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::16384-24575          201     12.59%     98.12% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::24576-32767           13      0.81%     98.94% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::32768-40959           11      0.69%     99.62% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::40960-49151            3      0.19%     99.81% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::49152-57343            2      0.13%     99.94% # Table walker service (enqueue to completion) latency
 system.cpu3.itb.walker.walkCompletionTime::81920-90111            1      0.06%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::total         1618                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walksPending::samples  -4448372768                       # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::mean     0.737414                       # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::stdev     0.439006                       # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::0    -1166371868     26.22%     26.22% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::1    -3283428900     73.81%    100.03% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::2        1175000     -0.03%    100.01% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::3         224000     -0.01%    100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::4          29000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::total  -4448372768                       # Table walker pending requests distribution
-system.cpu3.itb.walker.walkPageSizes::4K          844     71.40%     71.40% # Table walker page sizes translated
-system.cpu3.itb.walker.walkPageSizes::1M          338     28.60%    100.00% # Table walker page sizes translated
-system.cpu3.itb.walker.walkPageSizes::total         1182                       # Table walker page sizes translated
+system.cpu3.itb.walker.walkCompletionTime::total         1597                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walksPending::samples  -8763056564                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::mean     0.696085                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::stdev     0.459515                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::0    -2661759664     30.37%     30.37% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::1    -6102526900     69.64%    100.01% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::2        1039000     -0.01%    100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::3         149500     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::4          41500     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::total  -8763056564                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walkPageSizes::4K          846     71.33%     71.33% # Table walker page sizes translated
+system.cpu3.itb.walker.walkPageSizes::1M          340     28.67%    100.00% # Table walker page sizes translated
+system.cpu3.itb.walker.walkPageSizes::total         1186                       # Table walker page sizes translated
 system.cpu3.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst         4253                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Requested::total         4253                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst         4240                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Requested::total         4240                       # Table walker requests started/completed, data/inst
 system.cpu3.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst         1182                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Completed::total         1182                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin::total         5435                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.inst_hits                     9894210                       # ITB inst hits
-system.cpu3.itb.inst_misses                      4253                       # ITB inst misses
+system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst         1186                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Completed::total         1186                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin::total         5426                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.inst_hits                     9891489                       # ITB inst hits
+system.cpu3.itb.inst_misses                      4240                       # ITB inst misses
 system.cpu3.itb.read_hits                           0                       # DTB read hits
 system.cpu3.itb.read_misses                         0                       # DTB read misses
 system.cpu3.itb.write_hits                          0                       # DTB write hits
 system.cpu3.itb.write_misses                        0                       # DTB write misses
 system.cpu3.itb.flush_tlb                         157                       # Number of times complete TLB was flushed
-system.cpu3.itb.flush_tlb_mva                     231                       # Number of times TLB was flushed by MVA
+system.cpu3.itb.flush_tlb_mva                     225                       # Number of times TLB was flushed by MVA
 system.cpu3.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu3.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu3.itb.flush_entries                    1133                       # Number of entries that have been flushed from TLB
+system.cpu3.itb.flush_entries                    1134                       # Number of entries that have been flushed from TLB
 system.cpu3.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu3.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu3.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu3.itb.perms_faults                      703                       # Number of TLB faults due to permissions restrictions
+system.cpu3.itb.perms_faults                      708                       # Number of TLB faults due to permissions restrictions
 system.cpu3.itb.read_accesses                       0                       # DTB read accesses
 system.cpu3.itb.write_accesses                      0                       # DTB write accesses
-system.cpu3.itb.inst_accesses                 9898463                       # ITB inst accesses
-system.cpu3.itb.hits                          9894210                       # DTB hits
-system.cpu3.itb.misses                           4253                       # DTB misses
-system.cpu3.itb.accesses                      9898463                       # DTB accesses
-system.cpu3.numPwrStateTransitions               1744                       # Number of power state transitions
-system.cpu3.pwrStateClkGateDist::samples          872                       # Distribution of time spent in the clock gated state
-system.cpu3.pwrStateClkGateDist::mean    24195228.891055                       # Distribution of time spent in the clock gated state
-system.cpu3.pwrStateClkGateDist::stdev   644254106.585039                       # Distribution of time spent in the clock gated state
-system.cpu3.pwrStateClkGateDist::underflows          857     98.28%     98.28% # Distribution of time spent in the clock gated state
+system.cpu3.itb.inst_accesses                 9895729                       # ITB inst accesses
+system.cpu3.itb.hits                          9891489                       # DTB hits
+system.cpu3.itb.misses                           4240                       # DTB misses
+system.cpu3.itb.accesses                      9895729                       # DTB accesses
+system.cpu3.numPwrStateTransitions               1742                       # Number of power state transitions
+system.cpu3.pwrStateClkGateDist::samples          871                       # Distribution of time spent in the clock gated state
+system.cpu3.pwrStateClkGateDist::mean    24222914.443169                       # Distribution of time spent in the clock gated state
+system.cpu3.pwrStateClkGateDist::stdev   644616845.496373                       # Distribution of time spent in the clock gated state
+system.cpu3.pwrStateClkGateDist::underflows          856     98.28%     98.28% # Distribution of time spent in the clock gated state
 system.cpu3.pwrStateClkGateDist::1000-5e+10           15      1.72%    100.00% # Distribution of time spent in the clock gated state
 system.cpu3.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu3.pwrStateClkGateDist::max_value  18906661340                       # Distribution of time spent in the clock gated state
-system.cpu3.pwrStateClkGateDist::total            872                       # Distribution of time spent in the clock gated state
-system.cpu3.pwrStateResidencyTicks::ON   2802652584907                       # Cumulative time (in ticks) in various power states
-system.cpu3.pwrStateResidencyTicks::CLK_GATED  21098239593                       # Cumulative time (in ticks) in various power states
-system.cpu3.numCycles                        55802582                       # number of cpu cycles simulated
+system.cpu3.pwrStateClkGateDist::max_value  18906422924                       # Distribution of time spent in the clock gated state
+system.cpu3.pwrStateClkGateDist::total            871                       # Distribution of time spent in the clock gated state
+system.cpu3.pwrStateResidencyTicks::ON   2802614373020                       # Cumulative time (in ticks) in various power states
+system.cpu3.pwrStateResidencyTicks::CLK_GATED  21098158480                       # Cumulative time (in ticks) in various power states
+system.cpu3.numCycles                        55804206                       # number of cpu cycles simulated
 system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.fetch.icacheStallCycles          20935031                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts                      53976458                       # Number of instructions fetch has processed
-system.cpu3.fetch.Branches                   13574263                       # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches           9491322                       # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles                     32368112                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles                1569845                       # Number of cycles fetch has spent squashing
-system.cpu3.fetch.TlbCycles                     63704                       # Number of cycles fetch has spent waiting for tlb
-system.cpu3.fetch.MiscStallCycles                1342                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu3.fetch.PendingDrainCycles              208                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu3.fetch.PendingTrapStallCycles       113598                       # Number of stall cycles due to pending traps
-system.cpu3.fetch.PendingQuiesceStallCycles        71390                       # Number of stall cycles due to pending quiesce instructions
-system.cpu3.fetch.IcacheWaitRetryStallCycles          235                       # Number of stall cycles due to full MSHR
-system.cpu3.fetch.CacheLines                  9892868                       # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes               204224                       # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.ItlbSquashes                   2239                       # Number of outstanding ITLB misses that were squashed
-system.cpu3.fetch.rateDist::samples          54338522                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean             1.198008                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev            2.332788                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.icacheStallCycles          20943122                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts                      53945813                       # Number of instructions fetch has processed
+system.cpu3.fetch.Branches                   13558463                       # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches           9478759                       # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles                     32366624                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles                1570295                       # Number of cycles fetch has spent squashing
+system.cpu3.fetch.TlbCycles                     59981                       # Number of cycles fetch has spent waiting for tlb
+system.cpu3.fetch.MiscStallCycles                 769                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu3.fetch.PendingDrainCycles              238                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu3.fetch.PendingTrapStallCycles       103755                       # Number of stall cycles due to pending traps
+system.cpu3.fetch.PendingQuiesceStallCycles        71551                       # Number of stall cycles due to pending quiesce instructions
+system.cpu3.fetch.IcacheWaitRetryStallCycles          320                       # Number of stall cycles due to full MSHR
+system.cpu3.fetch.CacheLines                  9890169                       # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes               205274                       # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.ItlbSquashes                   2246                       # Number of outstanding ITLB misses that were squashed
+system.cpu3.fetch.rateDist::samples          54331487                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean             1.197628                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev            2.332891                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0                39853023     73.34%     73.34% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1                 1853402      3.41%     76.75% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2                 1194631      2.20%     78.95% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3                 3690685      6.79%     85.74% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4                  942938      1.74%     87.48% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5                  608116      1.12%     88.60% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6                 2975810      5.48%     94.07% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7                  643271      1.18%     95.26% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8                 2576646      4.74%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0                39855672     73.36%     73.36% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1                 1851434      3.41%     76.76% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2                 1194487      2.20%     78.96% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3                 3686492      6.79%     85.75% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4                  943670      1.74%     87.48% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5                  608106      1.12%     88.60% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6                 2967627      5.46%     94.07% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7                  643917      1.19%     95.25% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8                 2580082      4.75%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total            54338522                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate                 0.243255                       # Number of branch fetches per cycle
-system.cpu3.fetch.rate                       0.967275                       # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles                14662616                       # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles             29996417                       # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles                  7962115                       # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles              1015455                       # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles                701676                       # Number of cycles decode is squashing
-system.cpu3.decode.BranchResolved             1056216                       # Number of times decode resolved a branch
-system.cpu3.decode.BranchMispred                84320                       # Number of times decode detected a branch misprediction
-system.cpu3.decode.DecodedInsts              46882791                       # Number of instructions handled by decode
-system.cpu3.decode.SquashedInsts               277439                       # Number of squashed instructions handled by decode
-system.cpu3.rename.SquashCycles                701676                       # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles                15188976                       # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles                3032843                       # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles      21357872                       # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles                  8442903                       # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles              5613994                       # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts              45010257                       # Number of instructions processed by rename
-system.cpu3.rename.ROBFullEvents                  711                       # Number of times rename has blocked due to ROB full
-system.cpu3.rename.IQFullEvents               1193798                       # Number of times rename has blocked due to IQ full
-system.cpu3.rename.LQFullEvents                109598                       # Number of times rename has blocked due to LQ full
-system.cpu3.rename.SQFullEvents               3924436                       # Number of times rename has blocked due to SQ full
-system.cpu3.rename.RenamedOperands           46943427                       # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups            206658226                       # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups        50584429                       # Number of integer rename lookups
-system.cpu3.rename.fp_rename_lookups             3918                       # Number of floating rename lookups
-system.cpu3.rename.CommittedMaps             39299455                       # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps                 7643972                       # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts            719812                       # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts        667882                       # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts                  5739952                       # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads             7978184                       # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores            6284983                       # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads          1159177                       # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores         1675680                       # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded                  43355264                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded             518308                       # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued                 41274077                       # Number of instructions issued
-system.cpu3.iq.iqSquashedInstsIssued            55092                       # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined        6092748                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined     14109869                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved         54644                       # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples     54338522                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean        0.759573                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev       1.457624                       # Number of insts issued each cycle
+system.cpu3.fetch.rateDist::total            54331487                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate                 0.242965                       # Number of branch fetches per cycle
+system.cpu3.fetch.rate                       0.966698                       # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles                14668908                       # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles             29986640                       # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles                  7957627                       # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles              1016633                       # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles                701473                       # Number of cycles decode is squashing
+system.cpu3.decode.BranchResolved             1058313                       # Number of times decode resolved a branch
+system.cpu3.decode.BranchMispred                84773                       # Number of times decode detected a branch misprediction
+system.cpu3.decode.DecodedInsts              46874682                       # Number of instructions handled by decode
+system.cpu3.decode.SquashedInsts               279635                       # Number of squashed instructions handled by decode
+system.cpu3.rename.SquashCycles                701473                       # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles                15195365                       # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles                3032088                       # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles      21321904                       # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles                  8439674                       # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles              5640768                       # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts              45002197                       # Number of instructions processed by rename
+system.cpu3.rename.ROBFullEvents                  690                       # Number of times rename has blocked due to ROB full
+system.cpu3.rename.IQFullEvents               1195883                       # Number of times rename has blocked due to IQ full
+system.cpu3.rename.LQFullEvents                108366                       # Number of times rename has blocked due to LQ full
+system.cpu3.rename.SQFullEvents               3949949                       # Number of times rename has blocked due to SQ full
+system.cpu3.rename.RenamedOperands           46926978                       # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups            206658489                       # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups        50587166                       # Number of integer rename lookups
+system.cpu3.rename.fp_rename_lookups             3902                       # Number of floating rename lookups
+system.cpu3.rename.CommittedMaps             39299186                       # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps                 7627792                       # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts            720809                       # count of serializing insts renamed
+system.cpu3.rename.tempSerializingInsts        668593                       # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts                  5741274                       # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads             7971579                       # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores            6293429                       # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads          1156869                       # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores         1562249                       # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded                  43347954                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded             520206                       # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued                 41277545                       # Number of instructions issued
+system.cpu3.iq.iqSquashedInstsIssued            55280                       # Number of squashed instructions issued
+system.cpu3.iq.iqSquashedInstsExamined        6083084                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined     14076683                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedNonSpecRemoved         54734                       # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.issued_per_cycle::samples     54331487                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean        0.759735                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev       1.457545                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0           38089201     70.10%     70.10% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1            5343903      9.83%     79.93% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2            4107112      7.56%     87.49% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3            3342238      6.15%     93.64% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4            1372760      2.53%     96.17% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5             822455      1.51%     97.68% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6             871489      1.60%     99.28% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::7             257925      0.47%     99.76% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::8             131439      0.24%    100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0           38079008     70.09%     70.09% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1            5345699      9.84%     79.93% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2            4107348      7.56%     87.49% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3            3341746      6.15%     93.64% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4            1375872      2.53%     96.17% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5             821998      1.51%     97.68% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6             871189      1.60%     99.28% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7             257716      0.47%     99.76% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::8             130911      0.24%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total       54338522                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total       54331487                       # Number of insts issued each cycle
 system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu                  64295     10.27%     10.27% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult                     1      0.00%     10.27% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv                      0      0.00%     10.27% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd                    0      0.00%     10.27% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp                    0      0.00%     10.27% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt                    0      0.00%     10.27% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult                   0      0.00%     10.27% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv                    0      0.00%     10.27% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%     10.27% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd                     0      0.00%     10.27% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%     10.27% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu                     0      0.00%     10.27% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp                     0      0.00%     10.27% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt                     0      0.00%     10.27% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc                    0      0.00%     10.27% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult                    0      0.00%     10.27% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%     10.27% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift                   0      0.00%     10.27% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%     10.27% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%     10.27% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%     10.27% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%     10.27% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%     10.27% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%     10.27% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%     10.27% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%     10.27% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%     10.27% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%     10.27% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%     10.27% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead                288567     46.11%     56.39% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite               272927     43.61%    100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu                  64496     10.30%     10.30% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult                     0      0.00%     10.30% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv                      0      0.00%     10.30% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd                    0      0.00%     10.30% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp                    0      0.00%     10.30% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt                    0      0.00%     10.30% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult                   0      0.00%     10.30% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv                    0      0.00%     10.30% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%     10.30% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd                     0      0.00%     10.30% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%     10.30% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu                     0      0.00%     10.30% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp                     0      0.00%     10.30% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt                     0      0.00%     10.30% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc                    0      0.00%     10.30% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult                    0      0.00%     10.30% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%     10.30% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift                   0      0.00%     10.30% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%     10.30% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%     10.30% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%     10.30% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%     10.30% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%     10.30% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%     10.30% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%     10.30% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%     10.30% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%     10.30% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%     10.30% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%     10.30% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead                288888     46.14%     56.45% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite               272662     43.55%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu3.iq.FU_type_0::No_OpClass               61      0.00%      0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu             27558257     66.77%     66.77% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult               31168      0.08%     66.84% # Type of FU issued
+system.cpu3.iq.FU_type_0::No_OpClass               62      0.00%      0.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu             27558666     66.76%     66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntMult               30979      0.08%     66.84% # Type of FU issued
 system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     66.84% # Type of FU issued
 system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     66.84% # Type of FU issued
 system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     66.84% # Type of FU issued
@@ -2022,99 +2016,99 @@ system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.84% # Ty
 system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.84% # Type of FU issued
 system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.84% # Type of FU issued
 system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.84% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc          2328      0.01%     66.85% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc          2332      0.01%     66.85% # Type of FU issued
 system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     66.85% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMultAcc            4      0.00%     66.85% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc            5      0.00%     66.85% # Type of FU issued
 system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.85% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead             7689945     18.63%     85.48% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite            5992314     14.52%    100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead             7685963     18.62%     85.47% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite            5999538     14.53%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total              41274077                       # Type of FU issued
-system.cpu3.iq.rate                          0.739645                       # Inst issue rate
-system.cpu3.iq.fu_busy_cnt                     625790                       # FU busy when requested
-system.cpu3.iq.fu_busy_rate                  0.015162                       # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads         137559378                       # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes         49989246                       # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses     40120759                       # Number of integer instruction queue wakeup accesses
-system.cpu3.iq.fp_inst_queue_reads               8180                       # Number of floating instruction queue reads
-system.cpu3.iq.fp_inst_queue_writes              4843                       # Number of floating instruction queue writes
-system.cpu3.iq.fp_inst_queue_wakeup_accesses         3492                       # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses              41895381                       # Number of integer alu accesses
-system.cpu3.iq.fp_alu_accesses                   4425                       # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads          174238                       # Number of loads that had data forwarded from stores
+system.cpu3.iq.FU_type_0::total              41277545                       # Type of FU issued
+system.cpu3.iq.rate                          0.739685                       # Inst issue rate
+system.cpu3.iq.fu_busy_cnt                     626046                       # FU busy when requested
+system.cpu3.iq.fu_busy_rate                  0.015167                       # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads         137559508                       # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes         49974445                       # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses     40123728                       # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.fp_inst_queue_reads               8395                       # Number of floating instruction queue reads
+system.cpu3.iq.fp_inst_queue_writes              4805                       # Number of floating instruction queue writes
+system.cpu3.iq.fp_inst_queue_wakeup_accesses         3602                       # Number of floating instruction queue wakeup accesses
+system.cpu3.iq.int_alu_accesses              41898968                       # Number of integer alu accesses
+system.cpu3.iq.fp_alu_accesses                   4561                       # Number of floating point alu accesses
+system.cpu3.iew.lsq.thread0.forwLoads          173439                       # Number of loads that had data forwarded from stores
 system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads      1195264                       # Number of loads squashed
-system.cpu3.iew.lsq.thread0.ignoredResponses         1195                       # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation        28361                       # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores       579365                       # Number of stores squashed
+system.cpu3.iew.lsq.thread0.squashedLoads      1192109                       # Number of loads squashed
+system.cpu3.iew.lsq.thread0.ignoredResponses         1191                       # Number of memory responses ignored because the instruction is squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation        28578                       # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores       580828                       # Number of stores squashed
 system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu3.iew.lsq.thread0.rescheduledLoads       104459                       # Number of loads that were rescheduled
-system.cpu3.iew.lsq.thread0.cacheBlocked        43794                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu3.iew.lsq.thread0.rescheduledLoads       104405                       # Number of loads that were rescheduled
+system.cpu3.iew.lsq.thread0.cacheBlocked        43387                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles                701676                       # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles                2636383                       # Number of cycles IEW is blocking
-system.cpu3.iew.iewUnblockCycles               282446                       # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts           43936154                       # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts            66826                       # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts              7978184                       # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts             6284983                       # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts            267113                       # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents                 25993                       # Number of times the IQ has become full, causing a stall
-system.cpu3.iew.iewLSQFullEvents               250282                       # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents         28361                       # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect        127792                       # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect       130048                       # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts              257840                       # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts             40954158                       # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts              7560730                       # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts           285711                       # Number of squashed instructions skipped in execute
+system.cpu3.iew.iewSquashCycles                701473                       # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles                2634873                       # Number of cycles IEW is blocking
+system.cpu3.iew.iewUnblockCycles               283425                       # Number of cycles IEW is unblocking
+system.cpu3.iew.iewDispatchedInsts           43928502                       # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts            66531                       # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts              7971579                       # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts             6293429                       # Number of dispatched store instructions
+system.cpu3.iew.iewDispNonSpecInsts            268536                       # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewIQFullEvents                 25934                       # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewLSQFullEvents               251471                       # Number of times the LSQ has become full, causing a stall
+system.cpu3.iew.memOrderViolationEvents         28578                       # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect        127058                       # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect       130735                       # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts              257793                       # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts             40956248                       # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts              7556430                       # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts           286903                       # Number of squashed instructions skipped in execute
 system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu3.iew.exec_nop                        62582                       # number of nop insts executed
-system.cpu3.iew.exec_refs                    13496719                       # number of memory reference insts executed
-system.cpu3.iew.exec_branches                 7548230                       # Number of branches executed
-system.cpu3.iew.exec_stores                   5935989                       # Number of stores executed
-system.cpu3.iew.exec_rate                    0.733912                       # Inst execution rate
-system.cpu3.iew.wb_sent                      40661575                       # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count                     40124251                       # cumulative count of insts written-back
-system.cpu3.iew.wb_producers                 21126058                       # num instructions producing a value
-system.cpu3.iew.wb_consumers                 37308798                       # num instructions consuming a value
-system.cpu3.iew.wb_rate                      0.719039                       # insts written-back per cycle
-system.cpu3.iew.wb_fanout                    0.566249                       # average fanout of values written-back
-system.cpu3.commit.commitSquashedInsts        6107928                       # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls         463664                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.branchMispredicts           213549                       # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples     53039462                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean     0.713065                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev     1.610172                       # Number of insts commited each cycle
+system.cpu3.iew.exec_nop                        60342                       # number of nop insts executed
+system.cpu3.iew.exec_refs                    13498971                       # number of memory reference insts executed
+system.cpu3.iew.exec_branches                 7544495                       # Number of branches executed
+system.cpu3.iew.exec_stores                   5942541                       # Number of stores executed
+system.cpu3.iew.exec_rate                    0.733928                       # Inst execution rate
+system.cpu3.iew.wb_sent                      40664526                       # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count                     40127330                       # cumulative count of insts written-back
+system.cpu3.iew.wb_producers                 21123316                       # num instructions producing a value
+system.cpu3.iew.wb_consumers                 37320445                       # num instructions consuming a value
+system.cpu3.iew.wb_rate                      0.719074                       # insts written-back per cycle
+system.cpu3.iew.wb_fanout                    0.565999                       # average fanout of values written-back
+system.cpu3.commit.commitSquashedInsts        6097313                       # The number of squashed insts skipped by commit
+system.cpu3.commit.commitNonSpecStalls         465472                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.branchMispredicts           213597                       # The number of times a branch was mispredicted
+system.cpu3.commit.committed_per_cycle::samples     53033650                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean     0.713199                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev     1.610019                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0     38622110     72.82%     72.82% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1      6314877     11.91%     84.72% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2      3213776      6.06%     90.78% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3      1409463      2.66%     93.44% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4       790260      1.49%     94.93% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5       551904      1.04%     95.97% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6       961415      1.81%     97.78% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7       244563      0.46%     98.24% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::8       931094      1.76%    100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0     38610990     72.80%     72.80% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1      6319361     11.92%     84.72% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2      3213493      6.06%     90.78% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3      1410131      2.66%     93.44% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4       792140      1.49%     94.93% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5       553402      1.04%     95.98% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6       958153      1.81%     97.78% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7       245496      0.46%     98.25% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::8       930484      1.75%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total     53039462                       # Number of insts commited each cycle
-system.cpu3.commit.committedInsts            31045718                       # Number of instructions committed
-system.cpu3.commit.committedOps              37820561                       # Number of ops (including micro ops) committed
+system.cpu3.commit.committed_per_cycle::total     53033650                       # Number of insts commited each cycle
+system.cpu3.commit.committedInsts            31044800                       # Number of instructions committed
+system.cpu3.commit.committedOps              37823572                       # Number of ops (including micro ops) committed
 system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu3.commit.refs                      12488538                       # Number of memory references committed
-system.cpu3.commit.loads                      6782920                       # Number of loads committed
-system.cpu3.commit.membars                     181312                       # Number of memory barriers committed
-system.cpu3.commit.branches                   7134012                       # Number of branches committed
-system.cpu3.commit.fp_insts                      3283                       # Number of committed floating point instructions.
-system.cpu3.commit.int_insts                 32975843                       # Number of committed integer instructions.
-system.cpu3.commit.function_calls             1245781                       # Number of function calls committed.
+system.cpu3.commit.refs                      12492071                       # Number of memory references committed
+system.cpu3.commit.loads                      6779470                       # Number of loads committed
+system.cpu3.commit.membars                     181779                       # Number of memory barriers committed
+system.cpu3.commit.branches                   7130164                       # Number of branches committed
+system.cpu3.commit.fp_insts                      3347                       # Number of committed floating point instructions.
+system.cpu3.commit.int_insts                 32983556                       # Number of committed integer instructions.
+system.cpu3.commit.function_calls             1245135                       # Number of function calls committed.
 system.cpu3.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntAlu        25299473     66.89%     66.89% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntMult          30222      0.08%     66.97% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntAlu        25299125     66.89%     66.89% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntMult          30044      0.08%     66.97% # Class of committed instruction
 system.cpu3.commit.op_class_0::IntDiv               0      0.00%     66.97% # Class of committed instruction
 system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     66.97% # Class of committed instruction
 system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     66.97% # Class of committed instruction
@@ -2138,36 +2132,36 @@ system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     66.97% #
 system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     66.97% # Class of committed instruction
 system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     66.97% # Class of committed instruction
 system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     66.97% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMisc         2328      0.01%     66.98% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     66.98% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.98% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.98% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemRead        6782920     17.93%     84.91% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemWrite       5705618     15.09%    100.00% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMisc         2332      0.01%     66.97% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     66.97% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.97% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.97% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemRead        6779470     17.92%     84.90% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemWrite       5712601     15.10%    100.00% # Class of committed instruction
 system.cpu3.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu3.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::total         37820561                       # Class of committed instruction
-system.cpu3.commit.bw_lim_events               931094                       # number cycles where commit BW limit reached
-system.cpu3.rob.rob_reads                    90431014                       # The number of ROB reads
-system.cpu3.rob.rob_writes                   89155949                       # The number of ROB writes
-system.cpu3.timesIdled                         227288                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles                        1464060                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu3.quiesceCycles                  5161848397                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts                   31005981                       # Number of Instructions Simulated
-system.cpu3.committedOps                     37780824                       # Number of Ops (including micro ops) Simulated
-system.cpu3.cpi                              1.799736                       # CPI: Cycles Per Instruction
-system.cpu3.cpi_total                        1.799736                       # CPI: Total CPI of All Threads
-system.cpu3.ipc                              0.555637                       # IPC: Instructions Per Cycle
-system.cpu3.ipc_total                        0.555637                       # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads                44884059                       # number of integer regfile reads
-system.cpu3.int_regfile_writes               25155589                       # number of integer regfile writes
-system.cpu3.fp_regfile_reads                    14375                       # number of floating regfile reads
-system.cpu3.fp_regfile_writes                   12072                       # number of floating regfile writes
-system.cpu3.cc_regfile_reads                144434496                       # number of cc regfile reads
-system.cpu3.cc_regfile_writes                15958517                       # number of cc regfile writes
-system.cpu3.misc_regfile_reads               98379107                       # number of misc regfile reads
-system.cpu3.misc_regfile_writes                343145                       # number of misc regfile writes
-system.iobus.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
+system.cpu3.commit.op_class_0::total         37823572                       # Class of committed instruction
+system.cpu3.commit.bw_lim_events               930484                       # number cycles where commit BW limit reached
+system.cpu3.rob.rob_reads                    90425378                       # The number of ROB reads
+system.cpu3.rob.rob_writes                   89139493                       # The number of ROB writes
+system.cpu3.timesIdled                         227716                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.idleCycles                        1472719                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.quiesceCycles                  5161848513                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu3.committedInsts                   31006304                       # Number of Instructions Simulated
+system.cpu3.committedOps                     37785076                       # Number of Ops (including micro ops) Simulated
+system.cpu3.cpi                              1.799770                       # CPI: Cycles Per Instruction
+system.cpu3.cpi_total                        1.799770                       # CPI: Total CPI of All Threads
+system.cpu3.ipc                              0.555627                       # IPC: Instructions Per Cycle
+system.cpu3.ipc_total                        0.555627                       # IPC: Total IPC of All Threads
+system.cpu3.int_regfile_reads                44890181                       # number of integer regfile reads
+system.cpu3.int_regfile_writes               25156907                       # number of integer regfile writes
+system.cpu3.fp_regfile_reads                    14457                       # number of floating regfile reads
+system.cpu3.fp_regfile_writes                   12074                       # number of floating regfile writes
+system.cpu3.cc_regfile_reads                144431120                       # number of cc regfile reads
+system.cpu3.cc_regfile_writes                15956854                       # number of cc regfile writes
+system.cpu3.misc_regfile_reads               98347677                       # number of misc regfile reads
+system.cpu3.misc_regfile_writes                344757                       # number of misc regfile writes
+system.iobus.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
 system.iobus.trans_dist::ReadReq                30152                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30152                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59010                       # Transaction distribution
@@ -2218,15 +2212,15 @@ system.iobus.pkt_size_system.bridge.master::total       159093
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2320992                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2320992                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2480085                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             29851500                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy             29764500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy               102000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               228500                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               229000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                19500                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                20500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy                 4000                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy                 4500                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy                1000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
@@ -2236,32 +2230,32 @@ system.iobus.reqLayer19.occupancy                3000                       # La
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             4026500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             3967500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            23286500                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            23290000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            72958030                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy            72552043                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            50254000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            50146000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            14338000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            14254000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
 system.iocache.tags.replacements                36410                       # number of replacements
-system.iocache.tags.tagsinuse                1.002565                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.002362                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36426                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         248718527509                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.002565                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.062660                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.062660                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         248718607009                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.002362                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.062648                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.062648                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
 system.iocache.tags.tag_accesses               327996                       # Number of tag accesses
 system.iocache.tags.data_accesses              327996                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
+system.iocache.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
 system.iocache.ReadReq_misses::realview.ide          220                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              220                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
@@ -2270,14 +2264,14 @@ system.iocache.demand_misses::realview.ide        36444                       #
 system.iocache.demand_misses::total             36444                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide        36444                       # number of overall misses
 system.iocache.overall_misses::total            36444                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     16295912                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     16295912                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   1689414118                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   1689414118                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide   1705710030                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1705710030                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide   1705710030                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1705710030                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     16061914                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     16061914                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   1680216129                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   1680216129                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide   1696278043                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1696278043                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide   1696278043                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1696278043                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          220                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            220                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
@@ -2294,14 +2288,14 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 74072.327273                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 74072.327273                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 46637.978081                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 46637.978081                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 46803.589891                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 46803.589891                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 46803.589891                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 46803.589891                       # average overall miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 73008.700000                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 73008.700000                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 46384.058331                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 46384.058331                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 46544.782214                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 46544.782214                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 46544.782214                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 46544.782214                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
@@ -2310,744 +2304,744 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.writebacks::writebacks           36190                       # number of writebacks
 system.iocache.writebacks::total                36190                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ide          137                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          137                       # number of ReadReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::realview.ide        14064                       # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total        14064                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide        14201                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        14201                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide        14201                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        14201                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide      9445912                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total      9445912                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide    985358547                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total    985358547                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide    994804459                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total    994804459                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide    994804459                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total    994804459                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::realview.ide     0.622727                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total     0.622727                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.388251                       # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total     0.388251                       # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::realview.ide     0.389666                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     0.389666                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::realview.ide     0.389666                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     0.389666                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68948.262774                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 68948.262774                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70062.467790                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70062.467790                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 70051.718823                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 70051.718823                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 70051.718823                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 70051.718823                       # average overall mshr miss latency
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements                   100866                       # number of replacements
-system.l2c.tags.tagsinuse                65104.734410                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    5134220                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   166034                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    30.922703                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle              79359149000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   49022.002356                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker     2.902695                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.002960                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4655.957926                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     1835.969861                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.000002                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      774.839390                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      858.475569                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker    20.852845                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst     2233.809872                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data      830.848364                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.dtb.walker    56.245543                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.itb.walker     0.001828                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst     2978.546484                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data     1834.278716                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.748016                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000044                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.071044                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.028015                       # Average percentage of cache occupancy
+system.iocache.ReadReq_mshr_misses::realview.ide          135                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          135                       # number of ReadReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::realview.ide        13984                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total        13984                       # number of WriteLineReq MSHR misses
+system.iocache.demand_mshr_misses::realview.ide        14119                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        14119                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide        14119                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        14119                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide      9311914                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total      9311914                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide    980165529                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total    980165529                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide    989477443                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total    989477443                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide    989477443                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total    989477443                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::realview.ide     0.613636                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total     0.613636                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.386042                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total     0.386042                       # mshr miss rate for WriteLineReq accesses
+system.iocache.demand_mshr_miss_rate::realview.ide     0.387416                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     0.387416                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::realview.ide     0.387416                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     0.387416                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68977.140741                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 68977.140741                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70091.928561                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70091.928561                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 70081.269424                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 70081.269424                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 70081.269424                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 70081.269424                       # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.l2c.tags.replacements                   100900                       # number of replacements
+system.l2c.tags.tagsinuse                65188.817028                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    5432391                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   166232                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    32.679574                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle              76153677500                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks       0.990870                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker     3.930107                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     1.003315                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     4645.223340                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data    20148.450289                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.003029                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      771.166553                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     6124.303836                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.dtb.walker    20.124161                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst     2252.228504                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data    10091.945751                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.dtb.walker    55.278842                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.itb.walker     0.002282                       # Average occupied blocks per requestor
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 system.l2c.tags.occ_percent::cpu3.itb.walker     0.000000                       # Average percentage of cache occupancy
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 system.l2c.SCUpgradeReq_hits::cpu0.data             1                       # number of SCUpgradeReq hits
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-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.989496                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data     0.979821                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3.data     0.959264                       # miss rate for UpgradeReq accesses
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-system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.011376                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.010967                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.010726                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.022477                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.033462                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.023763                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.030554                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.026349                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.001168                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.000928                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.010634                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.147357                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000635                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.009003                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.134807                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.dtb.walker     0.002180                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.011376                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.214542                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.dtb.walker     0.003562                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.itb.walker     0.000266                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst       0.010967                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.data       0.230653                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.060556                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.001168                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.000928                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.010634                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.147357                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000635                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.009003                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.134807                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.dtb.walker     0.002180                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.011376                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.214542                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.dtb.walker     0.003562                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.itb.walker     0.000266                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst      0.010967                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.data      0.230653                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.060556                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        97500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 84714.285714                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 92479.729730                       # average ReadReq miss latency
+system.l2c.SCUpgradeReq_accesses::cpu3.data           27                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total            28                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       111183                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        34298                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data        55188                       # number of ReadExReq accesses(hits+misses)
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+system.l2c.ReadExReq_accesses::total           296396                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu0.inst       744255                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu1.inst       211924                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu2.inst       469268                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu3.inst       544472                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::total       1969919                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data       228535                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data        71889                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu2.data        92254                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu3.data       144684                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total       537362                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker         3247                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         1704                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          744255                       # number of demand (read+write) accesses
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+system.l2c.demand_accesses::cpu1.inst          211924                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          106187                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.dtb.walker        12282                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.itb.walker          909                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst          469268                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data          147442                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.dtb.walker        19885                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.itb.walker         3416                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.inst          544472                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.data          240411                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2847010                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker         3247                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         1704                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         744255                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         339718                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::cpu1.itb.walker          661                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         211924                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::cpu2.dtb.walker        12282                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.itb.walker          909                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst         469268                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::cpu3.dtb.walker        19885                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.itb.walker         3416                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::total            2847010                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.001540                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.001174                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000814                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.002280                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.dtb.walker     0.003571                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.itb.walker     0.000293                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.002492                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.004492                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.004149                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data     0.006818                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu3.data     0.001305                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.003927                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu3.data     0.074074                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.071429                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.395546                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.342848                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data     0.525766                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu3.data     0.530989                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.457439                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.010527                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.008956                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.011443                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.011117                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.010740                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.022338                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.033552                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.023945                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.030805                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.026394                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.001540                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.001174                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.010527                       # miss rate for demand accesses
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+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000814                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.008956                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.133453                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.dtb.walker     0.002280                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst       0.011443                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data       0.211778                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.dtb.walker     0.003571                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.itb.walker     0.000293                       # miss rate for demand accesses
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+system.l2c.demand_miss_rate::total           0.060074                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.001540                       # miss rate for overall accesses
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+system.l2c.overall_miss_rate::cpu3.dtb.walker     0.003571                       # miss rate for overall accesses
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+system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 93859.154930                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu3.itb.walker        84000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 84657.657658                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data    62.632696                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data   395.881007                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu3.data   320.547945                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   158.958485                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu3.data        40625                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total        40625                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 78565.346369                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 77280.427884                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3.data 82222.062251                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 53929.809927                       # average ReadExReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 83408.711528                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 83133.769878                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 83354.914291                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 52110.850795                       # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 84053.002070                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 83044.393593                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 88864.293785                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 54919.809322                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        97500                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 83408.711528                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 79486.823808                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 84714.285714                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 83133.769878                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 77680.347390                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 92479.729730                       # average overall miss latency
+system.l2c.ReadReq_avg_miss_latency::total 85509.259259                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data        29500                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 28833.333333                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu3.data        29500                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 15909.090909                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu3.data        81250                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total        81250                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 79958.202228                       # average ReadExReq miss latency
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+system.l2c.ReadExReq_avg_miss_latency::cpu3.data 82863.230376                       # average ReadExReq miss latency
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+system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 81495.521602                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 82598.510242                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 83517.759623                       # average ReadCleanReq miss latency
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+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 83942.786070                       # average ReadSharedReq miss latency
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+system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 88577.630693                       # average ReadSharedReq miss latency
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 system.l2c.demand_avg_miss_latency::cpu3.itb.walker        84000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.inst 83354.914291                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 84714.285714                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 83133.769878                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 77680.347390                       # average overall miss latency
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 system.l2c.overall_avg_miss_latency::cpu3.itb.walker        84000                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::total 54387.198147                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
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 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.writebacks::writebacks               92509                       # number of writebacks
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+system.l2c.demand_mshr_miss_latency::total   8156075999                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker        73500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    135698500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   1000988500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      2123500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst    389778500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data   2125974000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker      5954000                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu3.itb.walker        74000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.inst    437012499                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.data   4033283000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   8139960499                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    561987500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data   1400221000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data   1571751000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   3533959500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    561987500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data   1400221000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu3.data   1571751000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   3533959500                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000635                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.002180                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker     0.003562                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3.itb.walker     0.000266                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.002191                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.989496                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.979821                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data     0.959264                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.584582                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data     0.200000                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.190476                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.346719                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.534448                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu3.data     0.533498                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.311499                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.009003                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.011367                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.010958                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.006708                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.033462                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.023567                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.030243                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.016676                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000635                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.009003                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.134807                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.002180                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.011367                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.214420                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker     0.003562                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.itb.walker     0.000266                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.inst     0.010958                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.data     0.230466                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.040194                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000635                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.009003                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.134807                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.002180                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.011367                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.214420                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker     0.003562                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.itb.walker     0.000266                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.inst     0.010958                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.data     0.230466                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.040194                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        87500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 74714.285714                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 82479.729730                       # average ReadReq mshr miss latency
+system.l2c.overall_mshr_miss_latency::cpu3.inst    444784999                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.data   4050626500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   8156075999                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    558689000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data   1400703000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data   1566927500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   3526319500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    558689000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data   1400703000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu3.data   1566927500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   3526319500                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000814                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.002280                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker     0.003571                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3.itb.walker     0.000293                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.002331                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.004149                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.006818                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data     0.001305                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.002142                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data     0.074074                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.071429                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.342848                       # mshr miss rate for ReadExReq accesses
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+system.l2c.ReadExReq_mshr_miss_rate::cpu3.data     0.530989                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.309063                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.008956                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.011435                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.011108                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.006758                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.033552                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.023728                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.030487                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.016771                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000814                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.008956                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.133453                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.002280                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.011435                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.211643                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker     0.003571                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.itb.walker     0.000293                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.inst     0.011108                       # mshr miss rate for demand accesses
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+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000814                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.008956                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.133453                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.002280                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.011435                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.211643                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker     0.003571                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.itb.walker     0.000293                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.inst     0.011108                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.data     0.229777                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.040053                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        73500                       # average ReadReq mshr miss latency
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+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 83859.154930                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker        74000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 80355.769231                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18969.214437                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 19030.892449                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 18987.671233                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18993.894994                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data        45125                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        45125                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 68565.346369                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 67280.427884                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 72222.062251                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 70179.447604                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 73408.711528                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73170.660925                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 73361.171563                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73291.070677                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74053.002070                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 73203.507153                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 79058.105023                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 76293.740237                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        87500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73408.711528                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69486.823808                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 74714.285714                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73170.660925                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 67688.234733                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 82479.729730                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 81435.643564                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        19500                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 18833.333333                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data        19500                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19166.666667                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data        71250                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        71250                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69958.202228                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 67825.044803                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 72863.230376                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 70894.470826                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71495.521602                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 72638.557585                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 73542.493221                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72886.267954                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 73942.786070                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 72161.946094                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 78664.361823                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 75821.238349                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        73500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71495.521602                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70636.405335                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 75839.285714                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 72638.557585                       # average overall mshr miss latency
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+system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 83859.154930                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker        74000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 73361.171563                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 72762.226913                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 71025.605108                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        87500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73408.711528                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69486.823808                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 74714.285714                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73170.660925                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 67688.234733                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 82479.729730                       # average overall mshr miss latency
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+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 73326.451368                       # average overall mshr miss latency
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+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        73500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71495.521602                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70636.405335                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 75839.285714                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72638.557585                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 68129.274155                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 83859.154930                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker        74000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 73361.171563                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 72762.226913                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 71025.605108                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162942.157147                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 197019.980301                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 202519.134132                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 192933.313315                       # average ReadReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 89331.982197                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 113866.878100                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 112348.177269                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 108476.870894                       # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests        349065                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       146440                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 73542.493221                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 73326.451368                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 71525.703753                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163168.516355                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 196949.240720                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 202471.572555                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 192958.659371                       # average ReadReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 89361.644274                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 113841.271131                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 112356.768966                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 108495.461818                       # average overall mshr uncacheable latency
+system.membus.snoop_filter.tot_requests        344722                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests       142063                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests          474                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadReq               40114                       # Transaction distribution
-system.membus.trans_dist::ReadResp              75665                       # Transaction distribution
+system.membus.trans_dist::ReadResp              75706                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27565                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27565                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       128699                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             8576                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4535                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              4                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            1836                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            135474                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           135474                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         35551                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       128718                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             8591                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              126                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp              40                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            135468                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           135468                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         35592                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
-system.membus.trans_dist::InvalidateResp        22160                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp        22240                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105436                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2006                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       476553                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       584005                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        95097                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        95097                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 679102                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       470452                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       577904                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        95179                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        95179                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 673083                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159093                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4012                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     16895100                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     17058225                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2321472                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2321472                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                19379697                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              340                       # Total snoops (count)
-system.membus.snoopTraffic                      21632                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            342782                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.015424                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.123231                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     16898684                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     17061809                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2321600                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2321600                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                19383409                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              336                       # Total snoops (count)
+system.membus.snoopTraffic                      21376                       # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples            338143                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.015650                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.124118                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  337495     98.46%     98.46% # Request fanout histogram
-system.membus.snoop_fanout::1                    5287      1.54%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  332851     98.43%     98.43% # Request fanout histogram
+system.membus.snoop_fanout::1                    5292      1.57%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              342782                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            57572000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              338143                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            57431500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy              694499                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy              684999                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           502472051                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           500677543                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          647767750                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          649758250                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy             729588                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy             720586                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
 system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
 system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
 system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
 system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -3079,85 +3073,85 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
 system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests      5637070                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      2833088                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests        44773                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops            304                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops          304                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.snoop_filter.tot_requests      5637023                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      2833220                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests        44733                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops            306                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops          306                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2823750824500                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadReq             110855                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2618591                       # Transaction distribution
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2823712531500                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.trans_dist::ReadReq             111093                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2618641                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             27565                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            27565                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty       746435                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean      1969655                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict          146584                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            2802                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq            21                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           2823                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           296389                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          296389                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq       1970201                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq       537545                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq         4503                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5927985                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2623938                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        25305                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        99572                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               8676800                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    252179448                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     97825081                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        41104                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       175440                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              350221073                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          122763                       # Total snoops (count)
-system.toL2Bus.snoopTraffic                   6010036                       # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples          4133801                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.021872                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.146266                       # Request fanout histogram
+system.toL2Bus.trans_dist::WritebackDirty       747081                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean      1969505                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          146278                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            2801                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq            28                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp           2829                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           296396                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          296396                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq       1970061                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       537497                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq         4488                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5927533                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2623831                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        24350                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        98043                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               8673757                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    252159480                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     97841913                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        37624                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       168032                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              350207049                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          125784                       # Total snoops (count)
+system.toL2Bus.snoopTraffic                   6024500                       # Total snoop traffic (bytes)
+system.toL2Bus.snoop_fanout::samples          4134386                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.021942                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.146494                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                4043386     97.81%     97.81% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                  90415      2.19%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                4043670     97.81%     97.81% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                  90716      2.19%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            4133801                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         3409727455                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            4134386                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         3408827455                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           234412                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           230414                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        1840405228                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        1839308788                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         767451664                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         767442228                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          10602473                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          10535976                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          47179732                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          47560224                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu3.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu3.kern.inst.quiesce                       0                       # number of quiesce instructions executed
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
index 0ff6fe40b..21f94071a 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
@@ -1,140 +1,140 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.804565                       # Number of seconds simulated
-sim_ticks                                2804565276000                       # Number of ticks simulated
-final_tick                               2804565276000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.804492                       # Number of seconds simulated
+sim_ticks                                2804492191000                       # Number of ticks simulated
+final_tick                               2804492191000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 107399                       # Simulator instruction rate (inst/s)
-host_op_rate                                   130353                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2576386262                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 586748                       # Number of bytes of host memory used
-host_seconds                                  1088.57                       # Real time elapsed on the host
-sim_insts                                   116911386                       # Number of instructions simulated
-sim_ops                                     141898031                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 104736                       # Simulator instruction rate (inst/s)
+host_op_rate                                   127120                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2512420654                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 592468                       # Number of bytes of host memory used
+host_seconds                                  1116.25                       # Real time elapsed on the host
+sim_insts                                   116911529                       # Number of instructions simulated
+sim_ops                                     141898255                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu0.dtb.walker         4032                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           684608                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          5013536                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker         4544                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           686976                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          4780808                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           689856                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          4962016                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker         4288                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           685888                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          4855432                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11175528                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       684608                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       686976                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1371584                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8423424                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             11202536                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       689856                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       685888                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1375744                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8427008                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17516                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             8                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8440948                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8444532                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu0.dtb.walker           63                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             10697                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             78855                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker           71                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             10734                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             74702                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             10779                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             78050                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker           67                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             10717                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             75868                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                175138                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          131616                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                175560                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          131672                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4379                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                2                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               135997                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               136053                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu0.dtb.walker          1438                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              244105                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1787634                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          1620                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              244949                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             1704652                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              245982                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1769310                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          1529                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              244568                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             1731305                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              342                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3984763                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         244105                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         244949                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             489054                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3003469                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3994497                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         245982                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         244568                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             490550                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3004825                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data               6246                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  3                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3009717                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3003469                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                3011073                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3004825                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.dtb.walker         1438                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             244105                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1793879                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         1620                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             244949                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            1704655                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             245982                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1775556                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         1529                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             244568                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            1731308                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             342                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6994480                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        175139                       # Number of read requests accepted
-system.physmem.writeReqs                       135997                       # Number of write requests accepted
-system.physmem.readBursts                      175139                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     135997                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 11199488                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      9408                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8453504                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  11175592                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8440948                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      147                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total                7005571                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        175561                       # Number of read requests accepted
+system.physmem.writeReqs                       136053                       # Number of write requests accepted
+system.physmem.readBursts                      175561                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     136053                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 11226560                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      9344                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8456704                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  11202600                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8444532                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      146                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    3888                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11119                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               11081                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               11640                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               11194                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               11361                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               11364                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               11912                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               11778                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10214                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10385                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10562                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9757                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10332                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              11401                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10617                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10275                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8313                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8440                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                9041                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8539                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                8335                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                8538                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8956                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8814                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7742                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7782                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7931                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7392                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7874                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8749                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8038                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7602                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               11215                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               11147                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               11273                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               10737                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               11860                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               11441                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               12346                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               11875                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10047                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10348                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10556                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9541                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10610                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              11371                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10552                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10496                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8375                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                8461                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8703                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8182                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                8713                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                8565                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                9253                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8873                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7587                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7750                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7865                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7197                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               8117                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8726                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7969                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7800                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           9                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2804565097500                       # Total gap between requests
+system.physmem.numWrRetry                          11                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2804492012500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     542                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  174583                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  175005                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 131616                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    103547                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     61287                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      8418                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      1715                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        14                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 131672                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    103754                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     61549                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      8374                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      1717                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        10                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
@@ -164,180 +164,182 @@ system.physmem.rdQLenPdf::30                        0                       # Wh
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
 system.physmem.wrQLenPdf::0                       104                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::1                        99                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                        93                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                        93                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                        92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                        90                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                        88                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                        97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                        92                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                        91                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                        88                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                        89                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::7                        87                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::8                        85                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                        86                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                       86                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                       85                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                       83                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                       82                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                       80                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2019                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2967                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4607                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6324                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6955                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6781                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7195                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7653                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8228                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     8265                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     9381                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     9792                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     8195                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     8293                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     8483                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7349                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7216                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6949                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      347                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      338                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      305                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      201                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      152                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      246                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      140                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      170                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      169                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      173                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      124                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      145                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      130                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      114                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      101                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       94                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       95                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       89                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       98                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       78                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       78                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       74                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       79                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       60                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       70                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       51                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       45                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       33                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       25                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        64824                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      303.173639                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     178.438923                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     326.896368                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          24325     37.52%     37.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        16003     24.69%     62.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6580     10.15%     72.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3580      5.52%     77.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2814      4.34%     82.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1563      2.41%     84.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1120      1.73%     86.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1064      1.64%     88.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7775     11.99%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          64824                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6666                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        26.249925                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      478.560077                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6664     99.97%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::6144-8191            1      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::36864-38911            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6666                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6666                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        19.814881                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.232650                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       12.394597                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                11      0.17%      0.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                 7      0.11%      0.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11                4      0.06%      0.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15              12      0.18%      0.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5751     86.27%     86.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             132      1.98%     88.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              86      1.29%     90.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              46      0.69%     90.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             272      4.08%     94.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              61      0.92%     95.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              24      0.36%     96.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              14      0.21%     96.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              13      0.20%     96.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               8      0.12%     96.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               6      0.09%     96.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               6      0.09%     96.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             155      2.33%     99.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               5      0.08%     99.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               1      0.02%     99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               3      0.05%     99.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               9      0.14%     99.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.02%     99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               2      0.03%     99.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               3      0.05%     99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             6      0.09%     99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.02%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             8      0.12%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            11      0.17%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.02%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.02%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             2      0.03%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             1      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             1      0.02%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6666                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2635898000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5916998000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    874960000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       15062.96                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::9                        85                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                       83                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                       82                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::42                      202                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::50                      137                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::53                       87                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::57                       67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       56                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       36                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::61                       46                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       37                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        64611                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      304.641624                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     179.481113                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     327.031220                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          24202     37.46%     37.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        15601     24.15%     61.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6722     10.40%     72.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3765      5.83%     77.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2815      4.36%     82.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1576      2.44%     84.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1095      1.69%     86.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1044      1.62%     87.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7791     12.06%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          64611                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6681                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        26.254154                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      478.043046                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6679     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::6144-8191            1      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::36864-38911            1      0.01%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6681                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6681                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        19.777878                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.220598                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       12.301236                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                12      0.18%      0.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                 6      0.09%      0.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11                6      0.09%      0.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15               5      0.07%      0.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5747     86.02%     86.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             151      2.26%     88.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              95      1.42%     90.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              50      0.75%     90.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             278      4.16%     95.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              50      0.75%     95.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              23      0.34%     96.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              15      0.22%     96.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              16      0.24%     96.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               5      0.07%     96.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               1      0.01%     96.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               9      0.13%     96.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             158      2.36%     99.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               6      0.09%     99.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               1      0.01%     99.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               3      0.04%     99.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               4      0.06%     99.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               4      0.06%     99.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               1      0.01%     99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               1      0.01%     99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               1      0.01%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             3      0.04%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             8      0.12%     99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.01%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            10      0.15%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             1      0.01%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             3      0.04%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             1      0.01%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             1      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             2      0.03%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             1      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6681                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2656456250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5945487500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    877075000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       15143.84                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  33812.96                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           3.99                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.01                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        3.98                       # Average system read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  33893.84                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           4.00                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.02                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        3.99                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        3.01                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.64                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        11.88                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     144615                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     97638                       # Number of row buffer hits during writes
+system.physmem.avgWrQLen                        11.27                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     144956                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     97983                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   82.64                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.91                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9013952.41                       # Average gap between requests
-system.physmem.pageHitRate                      78.88                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  258899760                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  141264750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 713294400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                446964480                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           183180260640                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            77917696695                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1614387610500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1877045991225                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.283406                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2685583279000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     93650440000                       # Time in different power states
+system.physmem.writeRowHitRate                  74.14                       # Row buffer hit rate for writes
+system.physmem.avgGap                      8999890.93                       # Average gap between requests
+system.physmem.pageHitRate                      78.98                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  256646880                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  140035500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 716765400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                447930000                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           183175683600                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            77871232575                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1614386322750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1876994616705                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.281811                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2685576144250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     93648100000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     25331546500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     25267936250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  231169680                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  126134250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 651635400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                408952800                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           183180260640                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            76668612660                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1615483298250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1876750063680                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.177890                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2687409308250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     93650440000                       # Time in different power states
+system.physmem_1.actEnergy                  231812280                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  126484875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 651463800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                408311280                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           183175683600                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            76860878220                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1615272598500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1876727232555                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.186470                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2687058026250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     93648100000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     23501044250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     23784590000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
 system.realview.nvmem.bytes_read::cpu0.inst          768                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           768                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu0.inst          768                       # Number of instructions bytes read from this memory
@@ -350,30 +352,30 @@ system.realview.nvmem.bw_inst_read::cpu0.inst          274
 system.realview.nvmem.bw_inst_read::total          274                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu0.inst          274                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total             274                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups               26568186                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         13757380                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           498035                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            15521852                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits                8027077                       # Number of BTB hits
+system.cpu0.branchPred.lookups               26597024                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         13781156                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           500525                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            15548162                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits                8034631                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            51.714686                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                6610878                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             28698                       # Number of incorrect RAS predictions.
-system.cpu0.branchPred.indirectLookups        4514253                       # Number of indirect predictor lookups.
-system.cpu0.branchPred.indirectHits           4401271                       # Number of indirect target hits.
-system.cpu0.branchPred.indirectMisses          112982                       # Number of indirect misses.
-system.cpu0.branchPredindirectMispredicted        32075                       # Number of mispredicted indirect branches.
+system.cpu0.branchPred.BTBHitPct            51.675761                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                6612410                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             28559                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.indirectLookups        4512781                       # Number of indirect predictor lookups.
+system.cpu0.branchPred.indirectHits           4401242                       # Number of indirect target hits.
+system.cpu0.branchPred.indirectMisses          111539                       # Number of indirect misses.
+system.cpu0.branchPredindirectMispredicted        32310                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -403,95 +405,95 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dtb.walker.walks                    58842                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort               58842                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        17810                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        14845                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore        26187                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples        32655                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean   632.200276                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev  3881.293866                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-16383        32316     98.96%     98.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::16384-32767          258      0.79%     99.75% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::32768-49151           49      0.15%     99.90% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::49152-65535           18      0.06%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::65536-81919           10      0.03%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::81920-98303            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::98304-114687            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::114688-131071            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::147456-163839            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total        32655                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples        12803                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 12389.596188                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 10179.754175                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev  7970.003099                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-8191         4327     33.80%     33.80% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::8192-16383         5843     45.64%     79.43% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::16384-24575         2208     17.25%     96.68% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::24576-32767          213      1.66%     98.34% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-40959          113      0.88%     99.23% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::40960-49151           69      0.54%     99.77% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::49152-57343           10      0.08%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::57344-65535            2      0.02%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-73727            2      0.02%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.walker.walks                    58420                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort               58420                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        17812                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        14989                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore        25619                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples        32801                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean   529.800921                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev  3188.709692                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-8191        31978     97.49%     97.49% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::8192-16383          569      1.73%     99.23% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::16384-24575          144      0.44%     99.66% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::24576-32767           64      0.20%     99.86% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::32768-40959           17      0.05%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::40960-49151           11      0.03%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::49152-57343            8      0.02%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::57344-65535            3      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::65536-73727            7      0.02%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total        32801                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples        12297                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 10850.939253                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean  9044.162625                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev  7100.469115                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-8191         4812     39.13%     39.13% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::8192-16383         6113     49.71%     88.84% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::16384-24575         1067      8.68%     97.52% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::24576-32767          142      1.15%     98.67% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-40959           98      0.80%     99.47% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::40960-49151           40      0.33%     99.80% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::49152-57343            6      0.05%     99.85% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::57344-65535            3      0.02%     99.87% # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walkCompletionTime::73728-81919            1      0.01%     99.88% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::81920-90111            7      0.05%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::90112-98303            4      0.03%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::98304-106495            4      0.03%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total        12803                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples  80889831836                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     0.654695                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev     0.499418                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-1  80811540336     99.90%     99.90% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::2-3     53922000      0.07%     99.97% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-5     11918500      0.01%     99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::6-7      4370000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-9      2811000      0.00%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::10-11      1565500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-13       964000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::14-15      1576000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-17       313500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::18-19       197500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::20-21       119500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::22-23        36500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::24-25       186500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::26-27        25500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::28-29        24000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::30-31       261500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total  80889831836                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         3539     69.42%     69.42% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         1559     30.58%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         5098                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        58842                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkCompletionTime::81920-90111            7      0.06%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::90112-98303            3      0.02%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::98304-106495            4      0.03%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::106496-114687            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total        12297                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples  80893915836                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.682843                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.485602                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-1  80818881836     99.91%     99.91% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::2-3     52303000      0.06%     99.97% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-5     11277500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::6-7      4307500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-9      2702500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::10-11      1677000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-13       813500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::14-15      1083500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-17       273500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::18-19       145500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::20-21       137500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::22-23        22500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::24-25       149000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::26-27        15000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::28-29         8000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::30-31       118500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total  80893915836                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K         3573     69.87%     69.87% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1541     30.13%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         5114                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        58420                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        58842                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         5098                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        58420                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         5114                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         5098                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total        63940                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         5114                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        63534                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    13766353                       # DTB read hits
-system.cpu0.dtb.read_misses                     49364                       # DTB read misses
-system.cpu0.dtb.write_hits                   10259633                       # DTB write hits
-system.cpu0.dtb.write_misses                     9478                       # DTB write misses
-system.cpu0.dtb.flush_tlb                         182                       # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva                     441                       # Number of times TLB was flushed by MVA
+system.cpu0.dtb.read_hits                    13811519                       # DTB read hits
+system.cpu0.dtb.read_misses                     49680                       # DTB read misses
+system.cpu0.dtb.write_hits                   10255920                       # DTB write hits
+system.cpu0.dtb.write_misses                     8740                       # DTB write misses
+system.cpu0.dtb.flush_tlb                         180                       # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva                     442                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3387                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      892                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  1297                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                    3407                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      831                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  1345                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      658                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                13815717                       # DTB read accesses
-system.cpu0.dtb.write_accesses               10269111                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      681                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                13861199                       # DTB read accesses
+system.cpu0.dtb.write_accesses               10264660                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         24025986                       # DTB hits
-system.cpu0.dtb.misses                          58842                       # DTB misses
-system.cpu0.dtb.accesses                     24084828                       # DTB accesses
-system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.hits                         24067439                       # DTB hits
+system.cpu0.dtb.misses                          58420                       # DTB misses
+system.cpu0.dtb.accesses                     24125859                       # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -521,817 +523,813 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.cpu0.itb.walker.walks                     7885                       # Table walker walks requested
-system.cpu0.itb.walker.walksShort                7885                       # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walksShortTerminationLevel::Level1         2420                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2         4556                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore          909                       # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples         6976                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean  1209.934060                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev  4914.790808                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-8191         6588     94.44%     94.44% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::8192-16383          240      3.44%     97.88% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::16384-24575           86      1.23%     99.11% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::24576-32767           32      0.46%     99.57% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-40959           14      0.20%     99.77% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::40960-49151            8      0.11%     99.89% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::49152-57343            3      0.04%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::57344-65535            1      0.01%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::65536-73727            1      0.01%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::73728-81919            1      0.01%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::81920-90111            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.cpu0.itb.walker.walks                     7709                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort                7709                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1         2350                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2         4518                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore          841                       # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples         6868                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean  1028.028538                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev  4446.105505                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-8191         6539     95.21%     95.21% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::8192-16383          228      3.32%     98.53% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::16384-24575           54      0.79%     99.32% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::24576-32767           25      0.36%     99.68% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-40959            8      0.12%     99.80% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::40960-49151            8      0.12%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::57344-65535            3      0.04%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::73728-81919            2      0.03%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu0.itb.walker.walkWaitTime::98304-106495            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total         6976                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples         3232                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 11727.877475                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean  9548.081517                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev  7530.941401                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-8191         1404     43.44%     43.44% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::8192-16383         1169     36.17%     79.61% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-24575          601     18.60%     98.21% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::24576-32767           35      1.08%     99.29% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-40959           11      0.34%     99.63% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::40960-49151            7      0.22%     99.85% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::49152-57343            3      0.09%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::57344-65535            1      0.03%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkWaitTime::total         6868                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples         3155                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 10383.835182                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean  8379.659125                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev  7218.357480                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-8191         1697     53.79%     53.79% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::8192-16383          897     28.43%     82.22% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-24575          526     16.67%     98.89% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::24576-32767           22      0.70%     99.59% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-40959            6      0.19%     99.78% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::40960-49151            4      0.13%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::49152-57343            2      0.06%     99.97% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::81920-90111            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total         3232                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples  33645212080                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     0.830268                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev     0.375687                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0     5713730428     16.98%     16.98% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1    27928860152     83.01%     99.99% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2        2282500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3         253000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::4          59500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::5          26500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total  33645212080                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K         1739     74.86%     74.86% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M          584     25.14%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total         2323                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkCompletionTime::total         3155                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples  33631218080                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     0.664997                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev     0.472178                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0    11268855428     33.51%     33.51% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1    22360574652     66.49%     99.99% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2        1449000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3         215000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::4          92500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::5          31500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total  33631218080                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K         1735     74.98%     74.98% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          579     25.02%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         2314                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         7885                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total         7885                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         7709                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total         7709                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2323                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2323                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total        10208                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    19916742                       # ITB inst hits
-system.cpu0.itb.inst_misses                      7885                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2314                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2314                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total        10023                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    19932883                       # ITB inst hits
+system.cpu0.itb.inst_misses                      7709                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                         182                       # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva                     441                       # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb                         180                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva                     442                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2222                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    2198                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     1235                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     1360                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                19924627                       # ITB inst accesses
-system.cpu0.itb.hits                         19916742                       # DTB hits
-system.cpu0.itb.misses                           7885                       # DTB misses
-system.cpu0.itb.accesses                     19924627                       # DTB accesses
-system.cpu0.numPwrStateTransitions               3162                       # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples         1581                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean    934903714.786211                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev   18749967267.112076                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::underflows         1545     97.72%     97.72% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10           33      2.09%     99.81% # Distribution of time spent in the clock gated state
+system.cpu0.itb.inst_accesses                19940592                       # ITB inst accesses
+system.cpu0.itb.hits                         19932883                       # DTB hits
+system.cpu0.itb.misses                           7709                       # DTB misses
+system.cpu0.itb.accesses                     19940592                       # DTB accesses
+system.cpu0.numPwrStateTransitions               3142                       # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples         1571                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean    940850098.166136                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev   18809432155.510696                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows         1535     97.71%     97.71% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10           33      2.10%     99.81% # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11            1      0.06%     99.87% # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11            2      0.13%    100.00% # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::max_value 499976755656                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total           1581                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON   1326482502923                       # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 1478082773077                       # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles                       106412241                       # number of cpu cycles simulated
+system.cpu0.pwrStateClkGateDist::max_value 499976941836                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total           1571                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON   1326416686781                       # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 1478075504219                       # Cumulative time (in ticks) in various power states
+system.cpu0.numCycles                       106432025                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          39807667                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     102389396                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                   26568186                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          19039226                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                     62026637                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                3110102                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                    107465                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles                3850                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingDrainCycles              421                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu0.fetch.PendingTrapStallCycles       155531                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       127911                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles          368                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                 19914927                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               350256                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                   3998                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         103784864                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             1.186876                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.290419                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          39943206                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     102521046                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                   26597024                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          19048283                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                     61908935                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                3115038                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                    100477                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles                4639                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles              343                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles       145025                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       124692                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles          417                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                 19931005                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               352594                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                   3944                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         103785216                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             1.188198                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.291827                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                75488274     72.74%     72.74% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                 3815041      3.68%     76.41% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                 2353974      2.27%     78.68% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                 7979190      7.69%     86.37% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                 1587719      1.53%     87.90% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                  994623      0.96%     88.86% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                 6057014      5.84%     94.69% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                 1019102      0.98%     95.67% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                 4489927      4.33%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                75467525     72.72%     72.72% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                 3816070      3.68%     76.39% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                 2355731      2.27%     78.66% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                 7980688      7.69%     86.35% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                 1585704      1.53%     87.88% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                  994797      0.96%     88.84% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                 6063354      5.84%     94.68% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                 1019951      0.98%     95.66% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                 4501396      4.34%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           103784864                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.249672                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.962196                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                27473759                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles             58173812                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                 15291505                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles              1432841                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               1412652                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved             1823499                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred               144249                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts              84520525                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts               475248                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               1412652                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                28280194                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles                6736942                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      43934801                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                 15910349                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles              7509629                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts              80887884                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents                 3905                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents               1038108                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                267593                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents               5492226                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands           83297539                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            373007231                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups        90195870                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups             6961                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             70398676                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                12898863                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts           1526830                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts       1432825                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                  8315442                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads            14569662                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           11312381                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1968850                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         2730392                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                  77926980                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            1058477                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                 74778360                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued            90763                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined       10627433                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     23204178                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        112737                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    103784864                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.720513                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.414461                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           103785216                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.249897                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.963254                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                27593672                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles             58026004                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                 15320051                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles              1430610                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               1414570                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved             1827863                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred               144800                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts              84662278                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts               478152                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               1414570                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                28401012                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles                6705964                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      43841646                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                 15935208                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles              7486513                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts              81019638                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents                 3792                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents               1047421                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                274733                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents               5461326                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands           83455149                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            373514562                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups        90323598                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups             7046                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             70490289                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                12964860                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts           1525331                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts       1431631                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                  8308638                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads            14616199                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           11309054                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1973588                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         2673938                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                  78051120                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1056498                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                 74882378                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued            90977                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined       10675596                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     23316802                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        112757                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    103785216                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.721513                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.414764                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0           73826337     71.13%     71.13% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1           10059193      9.69%     80.83% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2            7635969      7.36%     88.18% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            6342907      6.11%     94.30% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            2283033      2.20%     96.50% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5            1456613      1.40%     97.90% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6            1481922      1.43%     99.33% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7             479341      0.46%     99.79% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8             219549      0.21%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0           73772912     71.08%     71.08% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1           10078271      9.71%     80.79% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2            7660438      7.38%     88.17% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            6348835      6.12%     94.29% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            2285768      2.20%     96.49% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5            1455335      1.40%     97.90% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6            1487712      1.43%     99.33% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7             476853      0.46%     99.79% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8             219092      0.21%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      103784864                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      103785216                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                  96825      8.81%      8.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     1      0.00%      8.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%      8.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      8.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      8.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      8.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%      8.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      8.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      8.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      8.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      8.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      8.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      8.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      8.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      8.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%      8.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      8.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%      8.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      8.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      8.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      8.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      8.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      8.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      8.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      8.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      8.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      8.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      8.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      8.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                525523     47.82%     56.63% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite               476662     43.37%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                  97071      8.87%      8.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     1      0.00%      8.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%      8.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      8.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      8.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      8.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%      8.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      8.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      8.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      8.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      8.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      8.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      8.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      8.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      8.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%      8.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      8.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%      8.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      8.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      8.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      8.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      8.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      8.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      8.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      8.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      8.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      8.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      8.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      8.87% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                526414     48.10%     56.97% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite               471010     43.03%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass             2194      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             49752146     66.53%     66.54% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               57180      0.08%     66.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     66.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     66.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     66.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     66.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     66.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     66.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     66.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     66.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     66.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     66.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     66.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     66.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     66.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     66.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     66.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     66.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     66.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              1      0.00%     66.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc          4372      0.01%     66.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            1      0.00%     66.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead            14148422     18.92%     85.54% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           10814044     14.46%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass             2186      0.00%      0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             49813565     66.52%     66.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               57268      0.08%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              1      0.00%     66.60% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc          4356      0.01%     66.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            2      0.00%     66.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead            14194612     18.96%     85.56% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           10810388     14.44%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total              74778360                       # Type of FU issued
-system.cpu0.iq.rate                          0.702723                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                    1099011                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.014697                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         254516336                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes         89657321                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     72555337                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads              15022                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes              8945                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses         6550                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses              75867097                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                   8080                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          352646                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total              74882378                       # Type of FU issued
+system.cpu0.iq.rate                          0.703570                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                    1094496                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.014616                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         254720610                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes         89827638                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     72651171                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads              14835                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes              9007                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses         6569                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses              75966729                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                   7959                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          355417                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      2054023                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         2148                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      2067343                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         2157                       # Number of memory responses ignored because the instruction is squashed
 system.cpu0.iew.lsq.thread0.memOrderViolation        54598                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores      1028244                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedStores      1028774                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads       203435                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked        82087                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads       204196                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked        85944                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               1412652                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                5873643                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles               655367                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts           79110277                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts           106917                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts             14569662                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            11312381                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts            551702                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 44436                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents               599579                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.iewSquashCycles               1414570                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                5871401                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles               626694                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts           79236238                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts           107112                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts             14616199                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            11309054                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts            550325                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 44645                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents               570692                       # Number of times the LSQ has become full, causing a stall
 system.cpu0.iew.memOrderViolationEvents         54598                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        206066                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       219140                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              425206                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             74227613                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts             13928296                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           492013                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.predictedTakenIncorrect        206831                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       220981                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              427812                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             74329730                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts             13972872                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           494338                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       124820                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    24646290                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                14030699                       # Number of branches executed
-system.cpu0.iew.exec_stores                  10717994                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.697548                       # Inst execution rate
-system.cpu0.iew.wb_sent                      73714298                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     72561887                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 37730883                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 65693607                       # num instructions consuming a value
-system.cpu0.iew.wb_rate                      0.681894                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.574346                       # average fanout of values written-back
-system.cpu0.commit.commitSquashedInsts       10582820                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls         945740                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           355599                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    101354368                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.675249                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.564531                       # Number of insts commited each cycle
+system.cpu0.iew.exec_nop                       128620                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    24687619                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                14050828                       # Number of branches executed
+system.cpu0.iew.exec_stores                  10714747                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.698377                       # Inst execution rate
+system.cpu0.iew.wb_sent                      73810336                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     72657740                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 37782988                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 65726436                       # num instructions consuming a value
+system.cpu0.iew.wb_rate                      0.682668                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.574852                       # average fanout of values written-back
+system.cpu0.commit.commitSquashedInsts       10630509                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls         943741                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           357539                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    101347140                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.676054                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.564689                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0     74626886     73.63%     73.63% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1     12088537     11.93%     85.56% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      6044710      5.96%     91.52% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      2569505      2.54%     94.06% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4      1279385      1.26%     95.32% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5       839259      0.83%     96.15% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      1807050      1.78%     97.93% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       395487      0.39%     98.32% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1703549      1.68%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0     74567913     73.58%     73.58% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1     12119278     11.96%     85.53% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      6061489      5.98%     91.52% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      2574374      2.54%     94.06% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      1279376      1.26%     95.32% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5       838406      0.83%     96.15% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      1806795      1.78%     97.93% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       395599      0.39%     98.32% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1703910      1.68%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    101354368                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            56197107                       # Number of instructions committed
-system.cpu0.commit.committedOps              68439408                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    101347140                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            56273825                       # Number of instructions committed
+system.cpu0.commit.committedOps              68516155                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      22799776                       # Number of memory references committed
-system.cpu0.commit.loads                     12515639                       # Number of loads committed
-system.cpu0.commit.membars                     380661                       # Number of memory barriers committed
-system.cpu0.commit.branches                  13306067                       # Number of branches committed
-system.cpu0.commit.fp_insts                      6109                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 59926267                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls             2612600                       # Number of function calls committed.
+system.cpu0.commit.refs                      22829136                       # Number of memory references committed
+system.cpu0.commit.loads                     12548856                       # Number of loads committed
+system.cpu0.commit.membars                     380096                       # Number of memory barriers committed
+system.cpu0.commit.branches                  13320608                       # Number of branches committed
+system.cpu0.commit.fp_insts                      6081                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                 59986977                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls             2613752                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu        45579664     66.60%     66.60% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult          55599      0.08%     66.68% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv               0      0.00%     66.68% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     66.68% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     66.68% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     66.68% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     66.68% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     66.68% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     66.68% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     66.68% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     66.68% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     66.68% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     66.68% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     66.68% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     66.68% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     66.68% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     66.68% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     66.68% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     66.68% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     66.68% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     66.68% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     66.68% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     66.68% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     66.68% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     66.68% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc         4369      0.01%     66.69% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     66.69% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.69% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.69% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       12515639     18.29%     84.97% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      10284137     15.03%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu        45626966     66.59%     66.59% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult          55700      0.08%     66.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv               0      0.00%     66.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     66.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     66.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     66.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     66.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     66.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     66.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     66.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     66.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     66.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     66.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     66.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     66.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     66.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     66.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     66.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     66.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     66.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     66.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     66.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     66.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     66.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     66.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc         4353      0.01%     66.68% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     66.68% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.68% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.68% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       12548856     18.32%     85.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      10280280     15.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total         68439408                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events              1703549                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                   166286675                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  160474100                       # The number of ROB writes
-system.cpu0.timesIdled                         401346                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                        2627377                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  2956165518                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   56115723                       # Number of Instructions Simulated
-system.cpu0.committedOps                     68358024                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.896300                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.896300                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.527343                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.527343                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                80796649                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               46187734                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                    17075                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                   13292                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                262559417                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes                27235047                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads              188679333                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                725405                       # number of misc regfile writes
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements           851456                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.984383                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           42342080                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           851968                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            49.699144                       # Average number of references to valid blocks.
+system.cpu0.commit.op_class_0::total         68516155                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events              1703910                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                   166404387                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  160730663                       # The number of ROB writes
+system.cpu0.timesIdled                         403591                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                        2646809                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  2956150979                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   56189692                       # Number of Instructions Simulated
+system.cpu0.committedOps                     68432022                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.894156                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.894156                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.527940                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.527940                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                80895945                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               46256017                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                    17128                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                   13236                       # number of floating regfile writes
+system.cpu0.cc_regfile_reads                262969083                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes                27284448                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads              188741772                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                723817                       # number of misc regfile writes
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.tags.replacements           851102                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.984391                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           42341917                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           851614                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            49.719611                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         92671500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   183.852002                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   328.132381                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.359086                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.640884                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.999969                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   184.368893                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   327.615499                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.360095                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.639874                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.999970                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0          189                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::1          301                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2           22                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        189174693                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       189174693                       # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data     12241825                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     12926435                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       25168260                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      7660735                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      8240746                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      15901481                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       177973                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data       185251                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       363224                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       210012                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       236500                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       446512                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       216376                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data       242998                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       459374                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     19902560                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data     21167181                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        41069741                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     20080533                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data     21352432                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       41432965                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       399594                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       432990                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       832584                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1948359                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data      1749519                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      3697878                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data        78958                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data       104644                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       183602                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13682                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        13994                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        27676                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data           42                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu1.data           43                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total           85                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      2347953                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data      2182509                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       4530462                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      2426911                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data      2287153                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      4714064                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5954800500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   6571091500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  12525892000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  86724909183                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  78793160939                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 165518070122                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    180271000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    207675500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    387946500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       854000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       810000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total      1664000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  92679709683                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data  85364252439                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 178043962122                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  92679709683                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data  85364252439                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 178043962122                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     12641419                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     13359425                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     26000844                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      9609094                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      9990265                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     19599359                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       256931                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       289895                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       546826                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       223694                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       250494                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       474188                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       216418                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       243041                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       459459                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     22250513                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data     23349690                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     45600203                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     22507444                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data     23639585                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     46147029                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.031610                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.032411                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.032021                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.202762                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.175122                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.188673                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.307312                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.360972                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.335759                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.061164                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.055866                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.058365                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000194                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000177                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000185                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.105524                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.093471                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.099352                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.107827                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.096751                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.102153                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14902.126909                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15176.081434                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 15044.598503                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44511.770769                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45037.042146                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 44760.284174                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13175.778395                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14840.324425                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14017.433878                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 20333.333333                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 18837.209302                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 19576.470588                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39472.557450                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 39112.898246                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 39299.294889                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 38188.342994                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 37323.367715                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 37768.677329                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs      1136536                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets       185396                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            52540                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets           2932                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    21.631823                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    63.231924                       # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks       702421                       # number of writebacks
-system.cpu0.dcache.writebacks::total           702421                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       189399                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       219838                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       409237                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1792246                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1606080                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      3398326                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         9509                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         9097                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18606                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1981645                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data      1825918                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      3807563                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1981645                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data      1825918                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      3807563                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       210195                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       213152                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       423347                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       156113                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       143439                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       299552                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        54836                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        68047                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       122883                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         4173                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         4897                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9070                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data           42                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data           43                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total           85                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       366308                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       356591                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       722899                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       421144                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       424638                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       845782                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16327                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        14800                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.tags.tag_accesses        189170266                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       189170266                       # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.ReadReq_hits::cpu0.data     12276993                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data     12891400                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       25168393                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      7660658                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data      8240277                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      15900935                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       178519                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data       185010                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       363529                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       209836                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       236717                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       446553                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       216124                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data       243253                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       459377                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     19937651                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data     21131677                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        41069328                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     20116170                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data     21316687                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       41432857                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       401226                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data       429872                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       831098                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1944439                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data      1754085                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      3698524                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data        79996                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data       103567                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       183563                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13679                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        13937                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        27616                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data           39                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu1.data           31                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total           70                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      2345665                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data      2183957                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       4529622                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      2425661                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data      2287524                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      4713185                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   6001869000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   6540022000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  12541891000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  85882896000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  79793795696                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 165676691696                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    178954000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    206024000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    384978000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       605500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       494000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total      1099500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  91884765000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data  86333817696                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 178218582696                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  91884765000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data  86333817696                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 178218582696                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     12678219                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data     13321272                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     25999491                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      9605097                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data      9994362                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     19599459                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       258515                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       288577                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       547092                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       223515                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       250654                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       474169                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       216163                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       243284                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       459447                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     22283316                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data     23315634                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     45598950                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     22541831                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data     23604211                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     46146042                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.031647                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.032270                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.031966                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.202438                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.175507                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.188705                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.309444                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.358889                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.335525                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.061199                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.055603                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.058241                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000180                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000127                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000152                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.105266                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.093669                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.099336                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.107607                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.096912                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.102136                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14958.823705                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15213.882272                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 15090.748624                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44168.470186                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45490.267402                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 44795.353956                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13082.389064                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14782.521346                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13940.396871                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15525.641026                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15935.483871                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15707.142857                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39172.160134                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 39530.914618                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 39345.133589                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37880.299432                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 37741.163676                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 37812.770493                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs      1147990                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets       183848                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            53098                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets           2861                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    21.620212                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    64.260049                       # average number of cycles each access was blocked
+system.cpu0.dcache.writebacks::writebacks       702238                       # number of writebacks
+system.cpu0.dcache.writebacks::total           702238                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       190024                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       217945                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       407969                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1788584                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1610518                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      3399102                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         9563                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         8886                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18449                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1978608                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data      1828463                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      3807071                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1978608                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data      1828463                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      3807071                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       211202                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       211927                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       423129                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       155855                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       143567                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       299422                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        55758                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        66999                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       122757                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         4116                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         5051                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9167                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data           39                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data           31                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total           70                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       367057                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       355494                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       722551                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       422815                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       422493                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       845308                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16331                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        14796                       # number of ReadReq MSHR uncacheable
 system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31127                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        15920                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        11664                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        15929                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        11655                       # number of WriteReq MSHR uncacheable
 system.cpu0.dcache.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        32247                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        26464                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        32260                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        26451                       # number of overall MSHR uncacheable misses
 system.cpu0.dcache.overall_mshr_uncacheable_misses::total        58711                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2991440000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   3075969500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6067409500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   7265470369                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   6699556943                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  13965027312                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    768840000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    969057000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1737897000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     54425000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     82975500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    137400500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       812000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       767000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      1579000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  10256910369                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   9775526443                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  20032436812                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  11025750369                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  10744583443                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  21770333812                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3299950500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3004338000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6304288500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3299950500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   3004338000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6304288500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016627                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.015955                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016282                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.016246                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014358                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015284                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.213427                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.234730                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.224720                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.018655                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.019549                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.019127                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000194                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000177                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000185                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016463                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.015272                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.015853                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.018711                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.017963                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.018328                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14231.737196                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14430.873274                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14332.000699                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46539.816473                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46706.662365                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46619.709807                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14020.716318                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14240.995194                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14142.696712                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13042.175893                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16944.149479                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15148.897464                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19333.333333                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 17837.209302                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18576.470588                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28000.781771                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27413.833897                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27711.252626                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26180.475963                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25302.924945                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25739.887834                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 202116.157285                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 202995.810811                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202534.407428                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 102333.565913                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 113525.468561                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 107378.319225                       # average overall mshr uncacheable latency
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements          1933722                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.561114                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           38706921                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1934234                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            20.011499                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       9780443500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   229.301603                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   282.259511                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.447855                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.551288                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999143                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   3008616500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   3065906000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6074522500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   7160903385                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   6753725936                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  13914629321                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    778587000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    955209000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1733796000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     53300000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     84160500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    137460500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       566500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       463000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      1029500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  10169519885                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   9819631936                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  19989151821                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10948106885                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  10774840936                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  21722947821                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3301571000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3002627500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6304198500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3301571000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   3002627500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6304198500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016659                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.015909                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016275                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.016226                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014365                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015277                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.215686                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.232170                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.224381                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.018415                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.020151                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.019333                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000180                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000127                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000152                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016472                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.015247                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.015846                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.018757                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.017899                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.018318                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14245.208379                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14466.802248                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14356.195156                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45945.932983                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47042.328223                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46471.633083                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13963.682342                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14257.063538                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14123.805567                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12949.465500                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16662.146110                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14995.145631                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14525.641026                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14935.483871                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14707.142857                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27705.560403                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27622.496965                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27664.693317                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25893.373899                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25503.004632                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25698.263616                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 202165.880840                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 202935.083806                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202531.516047                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 102342.560446                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 113516.596726                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 107376.786292                       # average overall mshr uncacheable latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.tags.replacements          1935798                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.566475                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           38706343                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1936310                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            19.989745                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle       9778864500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   232.011267                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   279.555207                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.453147                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.546006                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999153                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::0          132                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          227                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          151                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          225                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          153                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         42723428                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        42723428                       # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst     18879325                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     19827596                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       38706921                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     18879325                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     19827596                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        38706921                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     18879325                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     19827596                       # number of overall hits
-system.cpu0.icache.overall_hits::total       38706921                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      1034931                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst      1047206                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      2082137                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      1034931                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst      1047206                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       2082137                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      1034931                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst      1047206                       # number of overall misses
-system.cpu0.icache.overall_misses::total      2082137                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14029669987                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  14232269988                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  28261939975                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  14029669987                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst  14232269988                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  28261939975                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  14029669987                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst  14232269988                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  28261939975                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     19914256                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     20874802                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     40789058                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     19914256                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     20874802                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     40789058                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     19914256                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     20874802                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     40789058                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.051969                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.050166                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.051046                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.051969                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.050166                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.051046                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.051969                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.050166                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.051046                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13556.140445                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13590.707070                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13573.525649                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13556.140445                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13590.707070                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13573.525649                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13556.140445                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13590.707070                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13573.525649                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs        12122                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses         42727106                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        42727106                       # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.ReadReq_hits::cpu0.inst     18888703                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     19817640                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       38706343                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     18888703                       # number of demand (read+write) hits
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+system.cpu0.icache.demand_hits::total        38706343                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     18888703                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst     19817640                       # number of overall hits
+system.cpu0.icache.overall_hits::total       38706343                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      1041631                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst      1042707                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      2084338                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      1041631                       # number of demand (read+write) misses
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+system.cpu0.icache.demand_misses::total       2084338                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      1041631                       # number of overall misses
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+system.cpu0.icache.overall_misses::total      2084338                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14123286486                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  14169720487                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  28293006973                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  14123286486                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst  14169720487                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  28293006973                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  14123286486                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst  14169720487                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  28293006973                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     19930334                       # number of ReadReq accesses(hits+misses)
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+system.cpu0.icache.overall_accesses::total     40790681                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.052264                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.049985                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.051098                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.052264                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.049985                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.051098                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.052264                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.049985                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.051098                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13558.819281                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13589.359702                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13574.097374                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13558.819281                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13589.359702                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13574.097374                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13558.819281                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13589.359702                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13574.097374                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs        11799                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              623                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              615                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    19.457464                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    19.185366                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks      1933722                       # number of writebacks
-system.cpu0.icache.writebacks::total          1933722                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        71718                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        76048                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total       147766                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        71718                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu1.inst        76048                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total       147766                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        71718                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu1.inst        76048                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total       147766                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       963213                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       971158                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1934371                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       963213                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       971158                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1934371                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       963213                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       971158                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1934371                       # number of overall MSHR misses
+system.cpu0.icache.writebacks::writebacks      1935798                       # number of writebacks
+system.cpu0.icache.writebacks::total          1935798                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        72135                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        75777                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total       147912                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        72135                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu1.inst        75777                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total       147912                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        72135                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu1.inst        75777                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total       147912                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       969496                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       966930                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1936426                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       969496                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       966930                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1936426                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       969496                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       966930                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1936426                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst          667                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total          667                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst          667                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total          667                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12408483492                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  12567838491                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  24976321983                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12408483492                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  12567838491                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  24976321983                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12408483492                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  12567838491                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  24976321983                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12493413990                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  12512123492                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  25005537482                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12493413990                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  12512123492                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  25005537482                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12493413990                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  12512123492                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  25005537482                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst     53482500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total     53482500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst     53482500                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total     53482500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.048368                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.046523                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.047424                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.048368                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.046523                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.047424                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.048368                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.046523                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.047424                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12882.387896                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12941.085272                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12911.857127                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12882.387896                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12941.085272                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12911.857127                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12882.387896                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12941.085272                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12911.857127                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.048644                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.046353                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.047472                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.048644                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.046353                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.047472                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.048644                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.046353                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.047472                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12886.503905                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12940.050978                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12913.241963                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12886.503905                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12940.050978                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12913.241963                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12886.503905                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12940.050978                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12913.241963                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80183.658171                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 80183.658171                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80183.658171                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 80183.658171                       # average overall mshr uncacheable latency
-system.cpu1.branchPred.lookups               27798204                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         14470719                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           518667                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            17368333                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                8539564                       # Number of BTB hits
+system.cpu1.branchPred.lookups               27768467                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         14444745                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           516645                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            16732156                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                8530484                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            49.167436                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                6849209                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect             29775                       # Number of incorrect RAS predictions.
-system.cpu1.branchPred.indirectLookups        4616738                       # Number of indirect predictor lookups.
-system.cpu1.branchPred.indirectHits           4505967                       # Number of indirect target hits.
-system.cpu1.branchPred.indirectMisses          110771                       # Number of indirect misses.
-system.cpu1.branchPredindirectMispredicted        32761                       # Number of mispredicted indirect branches.
-system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
+system.cpu1.branchPred.BTBHitPct            50.982575                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                6847641                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect             29585                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.indirectLookups        4618056                       # Number of indirect predictor lookups.
+system.cpu1.branchPred.indirectHits           4506231                       # Number of indirect target hits.
+system.cpu1.branchPred.indirectMisses          111825                       # Number of indirect misses.
+system.cpu1.branchPredindirectMispredicted        32588                       # Number of mispredicted indirect branches.
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1361,91 +1359,91 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dtb.walker.walks                    58826                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort               58826                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        18872                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2        14273                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore        25681                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples        33145                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean   585.865138                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev  3677.608561                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-16383        32788     98.92%     98.92% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::16384-32767          287      0.87%     99.79% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::32768-49151           48      0.14%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::49152-65535           12      0.04%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::65536-81919            7      0.02%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::98304-114687            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::114688-131071            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::131072-147455            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total        33145                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples        13049                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 12961.567936                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 10723.007113                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev  7830.239554                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-8191         3942     30.21%     30.21% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::8192-16383         6071     46.52%     76.73% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-24575         2547     19.52%     96.25% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::24576-32767          256      1.96%     98.21% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-40959          106      0.81%     99.03% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::40960-49151          110      0.84%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::49152-57343            9      0.07%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::57344-65535            2      0.02%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-73727            2      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::81920-90111            4      0.03%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total        13049                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples  90145173428                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.714972                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.473357                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0-1  90067700428     99.91%     99.91% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::2-3     53747000      0.06%     99.97% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4-5     11656000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::6-7      4441500      0.00%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8-9      2654000      0.00%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::10-11      1196000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12-13       758000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::14-15      1848500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::16-17       266500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::18-19       153500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::20-21       119500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::22-23       164000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::24-25       321500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::26-27        35000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::28-29         7500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::30-31       104500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total  90145173428                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K         3714     69.38%     69.38% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M         1639     30.62%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         5353                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        58826                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.walker.walks                    59138                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort               59138                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        19056                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2        14153                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore        25929                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples        33209                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean   492.833268                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev  3043.837220                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-8191        32423     97.63%     97.63% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::8192-16383          540      1.63%     99.26% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::16384-24575          149      0.45%     99.71% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::24576-32767           52      0.16%     99.86% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::32768-40959           16      0.05%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::40960-49151           18      0.05%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::49152-57343            4      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::57344-65535            2      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::65536-73727            5      0.02%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total        33209                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples        12964                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 10951.828139                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean  9214.622989                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  6533.603209                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-8191         4889     37.71%     37.71% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::8192-16383         6655     51.33%     89.05% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-24575         1022      7.88%     96.93% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::24576-32767          238      1.84%     98.77% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-40959          117      0.90%     99.67% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::40960-49151           38      0.29%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::57344-65535            2      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-73727            1      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::81920-90111            2      0.02%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total        12964                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples  90072330428                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.721128                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.470247                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0-1  89999642928     99.92%     99.92% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::2-3     51122000      0.06%     99.98% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4-5     10756000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::6-7      3956500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8-9      2349000      0.00%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::10-11      1202000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12-13       700500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::14-15      1277500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::16-17       267000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::18-19       187000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::20-21       117000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::22-23       117500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::24-25       238000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::26-27        36000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::28-29        19500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::30-31       342000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total  90072330428                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K         3730     69.60%     69.60% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M         1629     30.40%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         5359                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        59138                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        58826                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         5353                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        59138                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         5359                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         5353                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total        64179                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         5359                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        64497                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    14560023                       # DTB read hits
-system.cpu1.dtb.read_misses                     50490                       # DTB read misses
-system.cpu1.dtb.write_hits                   10636581                       # DTB write hits
-system.cpu1.dtb.write_misses                     8336                       # DTB write misses
-system.cpu1.dtb.flush_tlb                         176                       # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva                     476                       # Number of times TLB was flushed by MVA
+system.cpu1.dtb.read_hits                    14518023                       # DTB read hits
+system.cpu1.dtb.read_misses                     50239                       # DTB read misses
+system.cpu1.dtb.write_hits                   10641437                       # DTB write hits
+system.cpu1.dtb.write_misses                     8899                       # DTB write misses
+system.cpu1.dtb.flush_tlb                         178                       # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva                     475                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    3352                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      784                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  1139                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries                    3373                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      787                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  1128                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      621                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                14610513                       # DTB read accesses
-system.cpu1.dtb.write_accesses               10644917                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      610                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                14568262                       # DTB read accesses
+system.cpu1.dtb.write_accesses               10650336                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         25196604                       # DTB hits
-system.cpu1.dtb.misses                          58826                       # DTB misses
-system.cpu1.dtb.accesses                     25255430                       # DTB accesses
-system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.hits                         25159460                       # DTB hits
+system.cpu1.dtb.misses                          59138                       # DTB misses
+system.cpu1.dtb.accesses                     25218598                       # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1475,338 +1473,344 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.cpu1.itb.walker.walks                     7718                       # Table walker walks requested
-system.cpu1.itb.walker.walksShort                7718                       # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1         2370                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2         4511                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore          837                       # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples         6881                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean  1585.234704                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev  6902.284757                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-16383         6686     97.17%     97.17% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::16384-32767          129      1.87%     99.04% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::32768-49151           34      0.49%     99.53% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::49152-65535           16      0.23%     99.77% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::65536-81919            8      0.12%     99.88% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::81920-98303            3      0.04%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::98304-114687            3      0.04%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::114688-131071            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::131072-147455            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total         6881                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples         3170                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 12167.034700                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean  9891.169611                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev  8057.359944                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-16383         2478     78.17%     78.17% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-32767          663     20.91%     99.09% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-49151           24      0.76%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::49152-65535            4      0.13%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::147456-163839            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total         3170                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples  34310573580                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean     0.816220                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev     0.387901                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0     6310834876     18.39%     18.39% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1    27996313204     81.60%     99.99% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2        2293000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::3         658500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::4         333500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::5          91000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::6          49500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total  34310573580                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K         1756     75.27%     75.27% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M          577     24.73%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total         2333                       # Table walker page sizes translated
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.cpu1.itb.walker.walks                     7663                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                7663                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1         2322                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2         4510                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore          831                       # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples         6832                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean   994.072014                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev  4194.954654                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-8191         6528     95.55%     95.55% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::8192-16383          212      3.10%     98.65% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::16384-24575           44      0.64%     99.30% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::24576-32767           27      0.40%     99.69% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::32768-40959            9      0.13%     99.82% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::40960-49151            4      0.06%     99.88% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::49152-57343            5      0.07%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::57344-65535            1      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::65536-73727            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::73728-81919            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total         6832                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples         3180                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 10355.188679                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean  8393.071987                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  7092.645451                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-4095           28      0.88%      0.88% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-8191         1663     52.30%     53.18% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-12287          542     17.04%     70.22% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-16383          404     12.70%     82.92% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-20479           34      1.07%     83.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::20480-24575          470     14.78%     98.77% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-28671           15      0.47%     99.25% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::28672-32767            7      0.22%     99.47% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-36863            6      0.19%     99.65% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::36864-40959            3      0.09%     99.75% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-45055            5      0.16%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::49152-53247            3      0.09%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total         3180                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples  25646768488                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean     0.764516                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev     0.424553                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0     6041654948     23.56%     23.56% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1    19603312040     76.44%     99.99% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2        1413500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::3         335000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::4          53000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total  25646768488                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K         1773     75.48%     75.48% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          576     24.52%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total         2349                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         7718                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total         7718                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         7663                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total         7663                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2333                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2333                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total        10051                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    20877340                       # ITB inst hits
-system.cpu1.itb.inst_misses                      7718                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2349                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2349                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total        10012                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                    20862819                       # ITB inst hits
+system.cpu1.itb.inst_misses                      7663                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                         176                       # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva                     476                       # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb                         178                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva                     475                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    2200                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    2217                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                     1355                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                     1301                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                20885058                       # ITB inst accesses
-system.cpu1.itb.hits                         20877340                       # DTB hits
-system.cpu1.itb.misses                           7718                       # DTB misses
-system.cpu1.itb.accesses                     20885058                       # DTB accesses
-system.cpu1.numPwrStateTransitions               2914                       # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples         1457                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean    836230234.840082                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev   15860875866.076208                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::underflows         1422     97.60%     97.60% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1000-5e+10           32      2.20%     99.79% # Distribution of time spent in the clock gated state
+system.cpu1.itb.inst_accesses                20870482                       # ITB inst accesses
+system.cpu1.itb.hits                         20862819                       # DTB hits
+system.cpu1.itb.misses                           7663                       # DTB misses
+system.cpu1.itb.accesses                     20870482                       # DTB accesses
+system.cpu1.numPwrStateTransitions               2936                       # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples         1468                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean    829956972.596730                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev   15801466276.187872                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows         1432     97.55%     97.55% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10           33      2.25%     99.80% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11            1      0.07%     99.86% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::2.5e+11-3e+11            1      0.07%     99.93% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11            1      0.07%    100.00% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::max_value 499953982692                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total           1457                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON   1586177823838                       # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 1218387452162                       # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles                       109746430                       # number of cpu cycles simulated
+system.cpu1.pwrStateClkGateDist::total           1468                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON   1586115355228                       # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 1218376835772                       # Cumulative time (in ticks) in various power states
+system.cpu1.numCycles                       109612747                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles          40895986                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                     108462285                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                   27798204                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches          19894740                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                     64228270                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                3210503                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                    105636                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles                7306                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingDrainCycles              364                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu1.fetch.PendingTrapStallCycles       136679                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       127439                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles          259                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                 20874803                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes               362169                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                   3960                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         107107154                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.215557                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.316339                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles          40790032                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                     108316651                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                   27768467                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches          19884356                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                     64224291                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                3206570                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                    101756                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles                7200                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles              365                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles       143510                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       122842                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles          226                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                 20860348                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes               361284                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                   3826                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         106993471                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.215539                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.315939                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                77373213     72.24%     72.24% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                 3963895      3.70%     75.94% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                 2490638      2.33%     78.27% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                 8243801      7.70%     85.96% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                 1611366      1.50%     87.47% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                 1186347      1.11%     88.57% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                 6289453      5.87%     94.45% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                 1183134      1.10%     95.55% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                 4765307      4.45%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                77281815     72.23%     72.23% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                 3963095      3.70%     75.93% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                 2488318      2.33%     78.26% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                 8243119      7.70%     85.96% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                 1612889      1.51%     87.47% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                 1184021      1.11%     88.58% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                 6282411      5.87%     94.45% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                 1182908      1.11%     95.56% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                 4754895      4.44%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           107107154                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.253295                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.988299                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                27921866                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles             60067662                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                 15890093                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles              1767595                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               1459620                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved             1999442                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred               147513                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              90274906                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts               488786                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               1459620                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                28874792                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                5214847                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles      47170555                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                 16697712                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles              7689265                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              86435062                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                 2196                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents               1738246                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                216044                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents               4936698                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands           89654559                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            397922384                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups        96312255                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups             6119                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps             76275352                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                13379191                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts           1604332                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts       1503289                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                 10206476                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads            15384658                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores           11766815                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads          2187303                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores         2806337                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  83309557                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded            1151208                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 79998202                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued            91456                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined       10920754                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     24595973                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        103002                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    107107154                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.746899                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.431011                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total           106993471                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.253332                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.988176                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                27827531                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles             60076040                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                 15861302                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles              1770624                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               1457723                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved             1995842                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred               147467                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              90138607                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts               489536                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               1457723                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                28780463                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                5201978                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles      47127740                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                 16672085                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles              7753197                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              86299553                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                 2624                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents               1735423                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                210199                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents               5005527                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands           89489706                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            397397955                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups        96183965                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups             6079                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps             76183985                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                13305705                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts           1606232                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts       1504962                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                 10217330                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads            15336831                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores           11768795                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads          2172366                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores         2803589                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  83184481                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded            1153102                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 79902588                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            90974                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined       10871346                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     24449389                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        102910                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    106993471                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.746799                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.430875                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           75017466     70.04%     70.04% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1           10766554     10.05%     80.09% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2            8172110      7.63%     87.72% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3            6817962      6.37%     94.09% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4            2501926      2.34%     96.42% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5            1553712      1.45%     97.87% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6            1535084      1.43%     99.31% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7             491946      0.46%     99.77% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8             250394      0.23%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           74936839     70.04%     70.04% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1           10763085     10.06%     80.10% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2            8157485      7.62%     87.72% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3            6811202      6.37%     94.09% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4            2499268      2.34%     96.42% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5            1551620      1.45%     97.87% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6            1531718      1.43%     99.31% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7             492585      0.46%     99.77% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8             249669      0.23%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      107107154                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      106993471                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                 114052      9.86%      9.86% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     7      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      9.87% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead                527984     45.67%     55.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite               514092     44.47%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                 113986      9.89%      9.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     7      0.00%      9.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%      9.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      9.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      9.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      9.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%      9.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      9.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      9.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      9.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      9.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      9.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      9.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      9.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      9.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%      9.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      9.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%      9.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      9.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      9.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      9.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      9.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      9.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      9.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      9.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      9.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      9.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      9.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead                526393     45.65%     55.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite               512676     44.46%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass              143      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu             53728973     67.16%     67.16% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               59111      0.07%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              3      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc          4201      0.01%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            2      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead            14948674     18.69%     85.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite           11257095     14.07%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass              151      0.00%      0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu             53671519     67.17%     67.17% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               59014      0.07%     67.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     67.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     67.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     67.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     67.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     67.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     67.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     67.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     67.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     67.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     67.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     67.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     67.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     67.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     67.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     67.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     67.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     67.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              3      0.00%     67.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc          4219      0.01%     67.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     67.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            2      0.00%     67.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead            14905160     18.65%     85.90% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite           11262520     14.10%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              79998202                       # Type of FU issued
-system.cpu1.iq.rate                          0.728937                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                    1156135                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.014452                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads         268337940                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         95424057                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     77696965                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads              13209                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes              7523                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses         5720                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              81147055                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                   7139                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads          351994                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total              79902588                       # Type of FU issued
+system.cpu1.iq.rate                          0.728953                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                    1153062                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.014431                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads         268029337                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         95251361                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     77606677                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads              13346                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes              7483                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses         5728                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses              81048267                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                   7232                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads          350880                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads      2099522                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses         2035                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation        51133                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores      1012143                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads      2084815                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses         2040                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation        50958                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores      1010162                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads       193136                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked       112329                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads       192812                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked       110845                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               1459620                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                4216196                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles               746434                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           84577573                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts           108382                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts             15384658                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts            11766815                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            582249                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                 44240                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents               689439                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents         51133                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect        222163                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       226496                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              448659                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             79436293                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts             14722883                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts           503246                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles               1457723                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                4213427                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles               739361                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           84450588                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts           107924                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts             15336831                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts            11768795                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            583687                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                 43916                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents               682784                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents         50958                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect        221001                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect       225315                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              446316                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             79342272                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts             14681206                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           501344                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       116808                       # number of nop insts executed
-system.cpu1.iew.exec_refs                    25882990                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                14805311                       # Number of branches executed
-system.cpu1.iew.exec_stores                  11160107                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.723817                       # Inst execution rate
-system.cpu1.iew.wb_sent                      78872387                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     77702685                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                 41015418                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                 71702227                       # num instructions consuming a value
-system.cpu1.iew.wb_rate                      0.708020                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.572024                       # average fanout of values written-back
-system.cpu1.commit.commitSquashedInsts       10950045                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls        1048206                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           372999                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    104597545                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.703779                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.594224                       # Number of insts commited each cycle
+system.cpu1.iew.exec_nop                       113005                       # number of nop insts executed
+system.cpu1.iew.exec_refs                    25846099                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                14786732                       # Number of branches executed
+system.cpu1.iew.exec_stores                  11164893                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.723842                       # Inst execution rate
+system.cpu1.iew.wb_sent                      78781509                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     77612405                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                 40957824                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                 71653116                       # num instructions consuming a value
+system.cpu1.iew.wb_rate                      0.708060                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.571613                       # average fanout of values written-back
+system.cpu1.commit.commitSquashedInsts       10899776                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls        1050192                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           371047                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    104491444                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.703761                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.593714                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     76066046     72.72%     72.72% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1     12690674     12.13%     84.86% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2      6559681      6.27%     91.13% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3      2745344      2.62%     93.75% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4      1426512      1.36%     95.12% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5       937004      0.90%     96.01% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6      1881396      1.80%     97.81% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7       439088      0.42%     98.23% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8      1851800      1.77%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     75982461     72.72%     72.72% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1     12681627     12.14%     84.85% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2      6552474      6.27%     91.12% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3      2740841      2.62%     93.75% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4      1432894      1.37%     95.12% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5       937550      0.90%     96.02% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6      1880638      1.80%     97.82% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       438919      0.42%     98.24% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8      1844040      1.76%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    104597545                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts            60869184                       # Number of instructions committed
-system.cpu1.commit.committedOps              73613528                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    104491444                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts            60792609                       # Number of instructions committed
+system.cpu1.commit.committedOps              73537005                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                      24039808                       # Number of memory references committed
-system.cpu1.commit.loads                     13285136                       # Number of loads committed
-system.cpu1.commit.membars                     433641                       # Number of memory barriers committed
-system.cpu1.commit.branches                  14069734                       # Number of branches committed
-system.cpu1.commit.fp_insts                      5319                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                 64506591                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls             2723384                       # Number of function calls committed.
+system.cpu1.commit.refs                      24010649                       # Number of memory references committed
+system.cpu1.commit.loads                     13252016                       # Number of loads committed
+system.cpu1.commit.membars                     434207                       # Number of memory barriers committed
+system.cpu1.commit.branches                  14055285                       # Number of branches committed
+system.cpu1.commit.fp_insts                      5347                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                 64446138                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls             2722289                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu        49512063     67.26%     67.26% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult          57459      0.08%     67.34% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu        49464791     67.27%     67.27% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult          57349      0.08%     67.34% # Class of committed instruction
 system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.34% # Class of committed instruction
 system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.34% # Class of committed instruction
 system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.34% # Class of committed instruction
@@ -1830,36 +1834,36 @@ system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.34% #
 system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.34% # Class of committed instruction
 system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.34% # Class of committed instruction
 system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc         4198      0.01%     67.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead       13285136     18.05%     85.39% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite      10754672     14.61%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc         4216      0.01%     67.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.35% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead       13252016     18.02%     85.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite      10758633     14.63%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total         73613528                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events              1851800                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                   174575850                       # The number of ROB reads
-system.cpu1.rob.rob_writes                  171636243                       # The number of ROB writes
-system.cpu1.timesIdled                         396046                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                        2639276                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  2436774880                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                   60795663                       # Number of Instructions Simulated
-system.cpu1.committedOps                     73540007                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.805169                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.805169                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.553965                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.553965                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                86363747                       # number of integer regfile reads
-system.cpu1.int_regfile_writes               49530768                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                    16607                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                   12960                       # number of floating regfile writes
-system.cpu1.cc_regfile_reads                280533576                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes                29711691                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads              196904196                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                794253                       # number of misc regfile writes
-system.iobus.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
+system.cpu1.commit.op_class_0::total         73537005                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events              1844040                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                   174349530                       # The number of ROB reads
+system.cpu1.rob.rob_writes                  171375071                       # The number of ROB writes
+system.cpu1.timesIdled                         393969                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                        2619276                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  2436753643                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                   60721837                       # Number of Instructions Simulated
+system.cpu1.committedOps                     73466233                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              1.805162                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.805162                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.553967                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.553967                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                86273419                       # number of integer regfile reads
+system.cpu1.int_regfile_writes               49465455                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                    16586                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                   13020                       # number of floating regfile writes
+system.cpu1.cc_regfile_reads                280148251                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes                29662918                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads              196736132                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                795813                       # number of misc regfile writes
+system.iobus.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
 system.iobus.trans_dist::ReadReq                30198                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30198                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
@@ -1910,23 +1914,23 @@ system.iobus.pkt_size_system.bridge.master::total       159125
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321224                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321224                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2480349                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             49485500                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy             49487000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy               100500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               338000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               335000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                29000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                29500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy                13000                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy                12500                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer7.occupancy                87500                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer8.occupancy               623500                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy               619500                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy               19500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
@@ -1936,40 +1940,40 @@ system.iobus.reqLayer16.occupancy               49000                       # La
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy                9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer19.occupancy                3000                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer21.occupancy                8500                       # Layer occupancy (ticks)
+system.iobus.reqLayer21.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6415000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6425500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            38220500                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            38207500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           187814925                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           187822672                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer3.occupancy            36770000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
 system.iocache.tags.replacements                36409                       # number of replacements
-system.iocache.tags.tagsinuse                0.981737                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                0.981311                       # Cycle average of tags in use
 system.iocache.tags.total_refs                     30                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36425                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000824                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         234297107000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     0.981737                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.061359                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.061359                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         234301648000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     0.981311                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.061332                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.061332                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
 system.iocache.tags.tag_accesses               328227                       # Number of tag accesses
 system.iocache.tags.data_accesses              328227                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
+system.iocache.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
 system.iocache.WriteLineReq_hits::realview.ide           29                       # number of WriteLineReq hits
 system.iocache.WriteLineReq_hits::total            29                       # number of WriteLineReq hits
 system.iocache.demand_hits::realview.ide           29                       # number of demand (read+write) hits
@@ -1984,14 +1988,14 @@ system.iocache.demand_misses::realview.ide        36444                       #
 system.iocache.demand_misses::total             36444                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide        36444                       # number of overall misses
 system.iocache.overall_misses::total            36444                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     31227677                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     31227677                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4282542248                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4282542248                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide   4313769925                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   4313769925                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide   4313769925                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   4313769925                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     31226877                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     31226877                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4279492795                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4279492795                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide   4310719672                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   4310719672                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide   4310719672                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   4310719672                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          249                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            249                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
@@ -2008,19 +2012,19 @@ system.iocache.demand_miss_rate::realview.ide     0.999205
 system.iocache.demand_miss_rate::total       0.999205                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide     0.999205                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total      0.999205                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 125412.357430                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 125412.357430                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118318.614394                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 118318.614394                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 118367.081687                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 118367.081687                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 118367.081687                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 118367.081687                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs           191                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 125409.144578                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 125409.144578                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118234.363724                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 118234.363724                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 118283.384700                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 118283.384700                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 118283.384700                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 118283.384700                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    2                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    95.500000                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.writebacks::writebacks           36160                       # number of writebacks
 system.iocache.writebacks::total                36160                       # number of writebacks
@@ -2032,14 +2036,14 @@ system.iocache.demand_mshr_misses::realview.ide        36444
 system.iocache.demand_mshr_misses::total        36444                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide        36444                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total        36444                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     18777677                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     18777677                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2470659836                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2470659836                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   2489437513                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   2489437513                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   2489437513                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   2489437513                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     18776877                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     18776877                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2467614128                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2467614128                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   2486391005                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   2486391005                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   2486391005                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   2486391005                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.999199                       # mshr miss rate for WriteLineReq accesses
@@ -2048,542 +2052,539 @@ system.iocache.demand_mshr_miss_rate::realview.ide     0.999205
 system.iocache.demand_mshr_miss_rate::total     0.999205                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide     0.999205                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total     0.999205                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75412.357430                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 75412.357430                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68259.699848                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68259.699848                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 68308.569669                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 68308.569669                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 68308.569669                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 68308.569669                       # average overall mshr miss latency
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements                   104028                       # number of replacements
-system.l2c.tags.tagsinuse                65127.134110                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    5124806                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   169274                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    30.275211                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   48520.895373                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    39.974246                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000253                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4816.133274                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2437.796190                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker    54.318644                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     5831.963518                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     3426.052612                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.740370                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000610                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.073488                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.037198                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000829                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.088989                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.052277                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.993761                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023           66                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        65180                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4           66                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          372                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         3219                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         8979                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        52594                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.001007                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.994568                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 45359933                       # Number of tag accesses
-system.l2c.tags.data_accesses                45359933                       # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.l2c.ReadReq_hits::cpu0.dtb.walker        34998                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         6494                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker        36104                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         6670                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                  84266                       # number of ReadReq hits
-system.l2c.WritebackDirty_hits::writebacks       702421                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total          702421                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks      1894027                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total         1894027                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data              70                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data              58                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 128                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data            30                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data            34                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                64                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            82284                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            74312                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               156596                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst        952993                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst        960231                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total           1913224                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       262086                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       277994                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total           540080                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker         34998                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          6494                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              952993                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              344370                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker         36104                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          6670                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              960231                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              352306                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2694166                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker        34998                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         6494                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             952993                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             344370                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker        36104                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         6670                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             960231                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             352306                       # number of overall hits
-system.l2c.overall_hits::total                2694166                       # number of overall hits
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75409.144578                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 75409.144578                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68175.552645                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68175.552645                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 68224.975442                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 68224.975442                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 68224.975442                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 68224.975442                       # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.l2c.tags.replacements                   104452                       # number of replacements
+system.l2c.tags.tagsinuse                65213.501449                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    5432730                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   169859                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    31.983763                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle              79304011000                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::cpu0.dtb.walker    47.675626                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.999974                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     4819.813719                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data    29687.680351                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker    45.444052                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     5864.770891                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data    24747.116836                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000727                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.000015                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.073545                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.452998                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000693                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.089489                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.377611                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.995079                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023           81                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        65326                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4           81                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2          149                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         7443                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        57733                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023     0.001236                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.996796                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 45059004                       # Number of tag accesses
+system.l2c.tags.data_accesses                45059004                       # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.l2c.ReadReq_hits::cpu0.dtb.walker        34072                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker         5784                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker        34667                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         5734                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                  80257                       # number of ReadReq hits
+system.l2c.WritebackDirty_hits::writebacks       702238                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total          702238                       # number of WritebackDirty hits
+system.l2c.WritebackClean_hits::writebacks      1896138                       # number of WritebackClean hits
+system.l2c.WritebackClean_hits::total         1896138                       # number of WritebackClean hits
+system.l2c.UpgradeReq_hits::cpu0.data            1486                       # number of UpgradeReq hits
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+system.l2c.ReadReq_accesses::cpu1.itb.walker         5734                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total              80388                       # number of ReadReq accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::writebacks       702238                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total       702238                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackClean_accesses::writebacks      1896138                       # number of WritebackClean accesses(hits+misses)
+system.l2c.WritebackClean_accesses::total      1896138                       # number of WritebackClean accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         1490                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         1351                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            2841                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data           39                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data           31                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total            70                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       154382                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       142228                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           296610                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu0.inst       969312                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu1.inst       966780                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::total       1936092                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data       271059                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data       283965                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total       555024                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker        34135                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         5785                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          969312                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          425441                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker        34734                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         5734                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          966780                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          426193                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2868114                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker        34135                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         5785                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         969312                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         425441                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker        34734                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         5734                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         966780                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::total            2868114                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.001846                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000173                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.001929                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.001630                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.002685                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.002961                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.002816                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.025641                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.032258                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.028571                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.457644                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.477824                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.467321                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.010454                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.011090                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.010772                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.026227                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.028827                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.027557                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.001846                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.000173                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.010454                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.182777                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.001929                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.011090                       # miss rate for demand accesses
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+system.l2c.demand_miss_rate::total           0.060978                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.001846                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.000173                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.010454                       # miss rate for overall accesses
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+system.l2c.overall_miss_rate::cpu1.inst      0.011090                       # miss rate for overall accesses
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+system.l2c.overall_miss_rate::total          0.060978                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 86023.809524                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        83500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 84239.436620                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 85203.703704                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   220.720721                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   337.074303                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   275.685558                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 21458.333333                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 15555.555556                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 18928.571429                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 84496.032404                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83403.230565                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 83967.357949                       # average ReadExReq miss latency
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-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 83956.331471                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 83371.861376                       # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 86223.231896                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90066.262826                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 88270.132350                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 86317.460317                       # average overall miss latency
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 system.l2c.demand_avg_miss_latency::cpu0.itb.walker        83500                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 82747.263483                       # average overall miss latency
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 system.l2c.overall_avg_miss_latency::cpu0.itb.walker        83500                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 82747.263483                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 84650.370119                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::total 84906.073988                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.writebacks::writebacks               95456                       # number of writebacks
-system.l2c.writebacks::total                    95456                       # number of writebacks
-system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            6                       # number of ReadCleanReq MSHR hits
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+system.l2c.writebacks::writebacks               95512                       # number of writebacks
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 system.l2c.ReadCleanReq_mshr_hits::total           11                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu0.data           74                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.data           64                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total          138                       # number of ReadSharedReq MSHR hits
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-system.l2c.demand_mshr_hits::cpu0.data             74                       # number of demand (read+write) MSHR hits
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-system.l2c.demand_mshr_hits::cpu1.data             64                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                149                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst             6                       # number of overall MSHR hits
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-system.l2c.overall_mshr_hits::total               149                       # number of overall MSHR hits
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 system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           63                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           71                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total             135                       # number of ReadReq MSHR misses
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-system.l2c.UpgradeReq_mshr_misses::cpu1.data         1292                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         2735                       # number of UpgradeReq MSHR misses
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 system.l2c.demand_mshr_misses::cpu0.dtb.walker           63                       # number of demand (read+write) MSHR misses
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 system.l2c.ReadReq_mshr_uncacheable::total        31794                       # number of ReadReq MSHR uncacheable
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 system.l2c.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
 system.l2c.overall_mshr_uncacheable_misses::cpu0.inst          667                       # number of overall MSHR uncacheable misses
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 system.l2c.overall_mshr_uncacheable_misses::total        59378                       # number of overall MSHR uncacheable misses
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 system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        73500                       # number of ReadReq MSHR miss cycles
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-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     24555000                       # number of UpgradeReq MSHR miss cycles
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 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst     43103498                       # number of ReadReq MSHR uncacheable cycles
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-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2819282000                       # number of ReadReq MSHR uncacheable cycles
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 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst     43103498                       # number of overall MSHR uncacheable cycles
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-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.001797                       # mshr miss rate for ReadReq accesses
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-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.957037                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.955292                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.285714                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.209302                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.247059                       # mshr miss rate for SCUpgradeReq accesses
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-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.011056                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.010744                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.026094                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.028051                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.027102                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.001797                       # mshr miss rate for demand accesses
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-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.010429                       # mshr miss rate for demand accesses
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-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.001963                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.011056                       # mshr miss rate for demand accesses
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-system.l2c.demand_mshr_miss_rate::total      0.061346                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.001797                       # mshr miss rate for overall accesses
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-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.010429                       # mshr miss rate for overall accesses
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-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.001963                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.011056                       # mshr miss rate for overall accesses
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-system.l2c.overall_mshr_miss_rate::total     0.061346                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 76317.460317                       # average ReadReq mshr miss latency
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+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.002961                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.002816                       # mshr miss rate for UpgradeReq accesses
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+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.032258                       # mshr miss rate for SCUpgradeReq accesses
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-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74239.436620                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 75203.703704                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19032.224532                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19005.417957                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19019.561243                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        24000                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 25333.333333                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24571.428571                       # average SCUpgradeReq mshr miss latency
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-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73403.230565                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 73967.357949                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72763.092194                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 73971.355473                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73387.314067                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 76326.381122                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80231.339564                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 78408.731544                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76317.460317                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74656.716418                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 75305.343511                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        19250                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        19250                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total        19250                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        70500                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        72000                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        71250                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 75191.303856                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74351.449382                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 74779.532075                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 73060.981434                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 73653.153573                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73365.476780                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 76830.868762                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 79654.476050                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 78344.034578                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76023.809524                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        73500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72763.092194                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 74658.033027                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74239.436620                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73971.355473                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74125.984304                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 74279.429720                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76317.460317                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73060.981434                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 75339.737401                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74656.716418                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73653.153573                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74917.502399                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 74920.373570                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76023.809524                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        73500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72763.092194                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 74658.033027                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74239.436620                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73971.355473                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74125.984304                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 74279.429720                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73060.981434                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 75339.737401                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74656.716418                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73653.153573                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74917.502399                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 74920.373570                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64622.935532                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189612.604888                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 190492.027027                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 187399.839529                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189662.053763                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 190431.603136                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 187397.008807                       # average ReadReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64622.935532                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96002.883989                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 106532.723700                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 100343.401563                       # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests        355735                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       149872                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests          505                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96012.740236                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 106522.475521                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 100341.885850                       # average overall mshr uncacheable latency
+system.membus.snoop_filter.tot_requests        352067                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests       145781                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests          504                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadReq               31794                       # Transaction distribution
-system.membus.trans_dist::ReadResp              68005                       # Transaction distribution
+system.membus.trans_dist::ReadResp              68171                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27584                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27584                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       131616                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             8821                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4625                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq             21                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       131672                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             9189                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              129                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            138237                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           138237                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         36212                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            138492                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           138492                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         36378                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36194                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           24                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2070                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       467969                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       575541                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       464721                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       572293                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72868                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total        72868                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 648409                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 645161                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          768                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4140                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17301276                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     17465309                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17331868                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     17495901                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2315200                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2315200                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                19780509                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              523                       # Total snoops (count)
-system.membus.snoopTraffic                      33344                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            274669                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.019252                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.137411                       # Request fanout histogram
+system.membus.pkt_size::total                19811101                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              522                       # Total snoops (count)
+system.membus.snoopTraffic                      33280                       # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples            270575                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.019532                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.138387                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  269381     98.07%     98.07% # Request fanout histogram
-system.membus.snoop_fanout::1                    5288      1.93%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  265290     98.05%     98.05% # Request fanout histogram
+system.membus.snoop_fanout::1                    5285      1.95%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              274669                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            95445000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              270575                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            95437500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               18156                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1705498                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1702998                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           921900685                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           917027178                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1007122750                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1009264500                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy            1322824                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy            1323623                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
 system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
 system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
 system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
 system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -2615,88 +2616,88 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
 system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests      5612083                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      2825755                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests        47584                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops            189                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops          189                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.snoop_filter.tot_requests      5615366                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      2827339                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests        47526                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops            188                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops          188                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2804565276000                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadReq             149636                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2639439                       # Transaction distribution
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2804492191000                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.trans_dist::ReadReq             149674                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2641289                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             27584                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            27584                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty       797877                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean      1933722                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict          157607                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            2864                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq            85                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           2948                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           296722                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          296722                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq       1934371                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq       555503                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq         4762                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5803440                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2678918                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        36089                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       166154                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               8684601                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    247577728                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     99675933                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        52660                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       284944                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              347591265                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          142991                       # Total snoops (count)
-system.toL2Bus.snoopTraffic                   6276420                       # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples          3079674                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.027770                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.164315                       # Request fanout histogram
+system.toL2Bus.trans_dist::WritebackDirty       797750                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean      1935798                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          157804                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            2842                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq            70                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp           2911                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           296610                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          296610                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq       1936426                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       555260                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq         4760                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5809649                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2677780                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        34247                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       164021                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               8685697                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    247843584                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     99641501                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        46076                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       275476                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              347806637                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          147441                       # Total snoops (count)
+system.toL2Bus.snoopTraffic                   6294736                       # Total snoop traffic (bytes)
+system.toL2Bus.snoop_fanout::samples          3081797                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.027693                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.164091                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                2994150     97.22%     97.22% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                  85524      2.78%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                2996454     97.23%     97.23% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                  85343      2.77%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            3079674                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         5529901884                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            3081797                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         5533506883                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           310676                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           309877                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        2904308481                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        2907318131                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        1324888971                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        1324202245                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          22963918                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          22762929                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          95377065                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          95604083                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    3038                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                    3039                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
index 864e3d209..539176c94 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
@@ -1,170 +1,170 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 47.445489                       # Number of seconds simulated
-sim_ticks                                47445489241000                       # Number of ticks simulated
-final_tick                               47445489241000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 47.276773                       # Number of seconds simulated
+sim_ticks                                47276772827000                       # Number of ticks simulated
+final_tick                               47276772827000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 208966                       # Simulator instruction rate (inst/s)
-host_op_rate                                   245756                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            10881126125                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 759660                       # Number of bytes of host memory used
-host_seconds                                  4360.35                       # Real time elapsed on the host
-sim_insts                                   911162440                       # Number of instructions simulated
-sim_ops                                    1071583187                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 146674                       # Simulator instruction rate (inst/s)
+host_op_rate                                   172507                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             7728246229                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 772984                       # Number of bytes of host memory used
+host_seconds                                  6117.40                       # Real time elapsed on the host
+sim_insts                                   897262562                       # Number of instructions simulated
+sim_ops                                    1055295890                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.dtb.walker       163648                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       157696                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          8375360                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         16685256                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher     18550592                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       100224                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker        74048                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          2844864                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          7994832                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher     10895744                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        436800                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             66279064                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      8375360                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      2844864                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total        11220224                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     78621824                       # Number of bytes written to this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu0.dtb.walker       117376                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker        90560                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          7953664                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         13400200                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher     16005120                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       165760                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       157376                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          3942400                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         13075216                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher     14708224                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        454784                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             70070680                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      7953664                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      3942400                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total        11896064                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     81443392                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          78642408                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         2557                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         2464                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst            130865                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            260720                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       289853                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         1566                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         1157                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             44451                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            124932                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher       170246                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6825                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1035636                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1228466                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          81463976                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         1834                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         1415                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst            124276                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            209391                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       250080                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         2590                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         2459                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             61600                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            204313                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher       229816                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           7106                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1094880                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1272553                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1231040                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          3449                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          3324                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              176526                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              351672                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher       390987                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          2112                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          1561                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               59961                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              168506                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       229648                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             9206                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1396952                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         176526                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          59961                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             236487                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1657098                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data                434                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1275127                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          2483                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          1916                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              168236                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              283442                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher       338541                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          3506                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          3329                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               83390                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              276567                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       311109                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             9620                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1482138                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         168236                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          83390                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             251626                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1722694                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data                435                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1657532                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1657098                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         3449                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         3324                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             176526                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             352106                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher       390987                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         2112                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         1561                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              59961                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             168506                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       229648                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            9206                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3054484                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1035636                       # Number of read requests accepted
-system.physmem.writeReqs                      1231040                       # Number of write requests accepted
-system.physmem.readBursts                     1035636                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1231040                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 66252160                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     28544                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  78640192                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  66279064                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               78642408                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      446                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2268                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bw_write::total                1723129                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1722694                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         2483                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         1916                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             168236                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             283877                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher       338541                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         3506                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         3329                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              83390                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             276568                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       311109                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            9620                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3205266                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1094880                       # Number of read requests accepted
+system.physmem.writeReqs                      1275127                       # Number of write requests accepted
+system.physmem.readBursts                     1094880                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1275127                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 70042240                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     30080                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  81461504                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  70070680                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               81463976                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      470                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2260                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               59521                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               66808                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               62154                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               70128                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               60732                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               72109                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               58717                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               62140                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               50595                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              107916                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              54809                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              63010                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              57730                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              64314                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              61474                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              63033                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               75175                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               80913                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               75568                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               82272                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               75546                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               83102                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               75765                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               76740                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               69114                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               73138                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              71733                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              77960                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              74616                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              78881                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              78631                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              79599                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               60604                       # Per bank write bursts
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+system.physmem.perBankRdBursts::5               80109                       # Per bank write bursts
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+system.physmem.perBankRdBursts::10              56514                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              69665                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              63387                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              66346                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              64421                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              60218                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               77101                       # Per bank write bursts
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+system.physmem.perBankWrBursts::4               79990                       # Per bank write bursts
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+system.physmem.perBankWrBursts::11              80687                       # Per bank write bursts
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+system.physmem.perBankWrBursts::13              80970                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              77560                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              77159                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          48                       # Number of times write queue was full causing retry
-system.physmem.totGap                    47445487151500                       # Total gap between requests
+system.physmem.numWrRetry                          62                       # Number of times write queue was full causing retry
+system.physmem.totGap                    47276770796500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       5                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1035606                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1094850                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1228466                       # Write request sizes (log2)
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-system.physmem.rdQLenPdf::1                    121307                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::20                        6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1272553                       # Write request sizes (log2)
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+system.physmem.rdQLenPdf::21                        5                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
@@ -189,174 +189,172 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::62                       69                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      144                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1012110                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      143.157878                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      97.072288                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     192.644368                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         686114     67.79%     67.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       195882     19.35%     87.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        47037      4.65%     91.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        20980      2.07%     93.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        15295      1.51%     95.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         9865      0.97%     96.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         6724      0.66%     97.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         5499      0.54%     97.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        24714      2.44%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1012110                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         60277                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        17.173764                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      160.670576                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          60274    100.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                    26459                       # What write queue length does an incoming req see
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+system.physmem.bytesPerActivate::samples      1013795                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      149.441747                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     100.507639                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     197.056675                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         662057     65.30%     65.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       208347     20.55%     85.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        52181      5.15%     91.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        23884      2.36%     93.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        17639      1.74%     95.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        11113      1.10%     96.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         7357      0.73%     96.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         6249      0.62%     97.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        24968      2.46%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1013795                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         63452                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        17.247415                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      156.483425                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          63450    100.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::25600-26623            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::29696-30719            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           60277                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         60277                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.385105                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.691366                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       13.394945                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           52026     86.31%     86.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23            2335      3.87%     90.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             778      1.29%     91.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             614      1.02%     92.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             994      1.65%     94.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             490      0.81%     94.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             334      0.55%     95.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47             282      0.47%     95.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             206      0.34%     96.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55             170      0.28%     96.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59             135      0.22%     96.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63             158      0.26%     97.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             477      0.79%     97.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71             137      0.23%     98.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75             123      0.20%     98.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79             110      0.18%     98.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              87      0.14%     98.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87              84      0.14%     98.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91              91      0.15%     98.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95             102      0.17%     99.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99              72      0.12%     99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103            71      0.12%     99.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107            64      0.11%     99.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111            59      0.10%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115            43      0.07%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119            45      0.07%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123            41      0.07%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127            40      0.07%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            47      0.08%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135            20      0.03%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139            11      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             5      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             4      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             2      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             4      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             8      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             4      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-187             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           60277                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    35377622933                       # Total ticks spent queuing
-system.physmem.totMemAccLat               54787435433                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   5175950000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       34175.00                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total           63452                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         63452                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.059825                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.482738                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       12.878895                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           55385     87.29%     87.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23            2264      3.57%     90.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             727      1.15%     92.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             608      0.96%     92.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35            1019      1.61%     94.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             457      0.72%     95.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             338      0.53%     95.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47             295      0.46%     96.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             198      0.31%     96.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55             179      0.28%     96.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59             127      0.20%     97.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63             154      0.24%     97.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             464      0.73%     98.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71             118      0.19%     98.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75             142      0.22%     98.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79             119      0.19%     98.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              89      0.14%     98.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87              71      0.11%     98.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91              72      0.11%     99.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95              80      0.13%     99.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99             103      0.16%     99.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103            73      0.12%     99.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107            46      0.07%     99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111            54      0.09%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115            48      0.08%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119            39      0.06%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123            53      0.08%     99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127            25      0.04%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            49      0.08%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135            20      0.03%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139            13      0.02%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             6      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             3      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             6      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-243             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           63452                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    38795138463                       # Total ticks spent queuing
+system.physmem.totMemAccLat               59315325963                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   5472050000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       35448.45                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  52925.00                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.40                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.66                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.40                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.66                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  54198.45                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.48                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.72                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.48                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.72                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.15                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        27.61                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     780044                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    471783                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   75.35                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  38.39                       # Row buffer hit rate for writes
-system.physmem.avgGap                     20931746.38                       # Average gap between requests
-system.physmem.pageHitRate                      55.29                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 3937837680                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 2148621750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                3995955600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               4050479520                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3098908325760                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1191842451045                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           27421814259750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             31726697931105                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.697958                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   45618359398995                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1584308960000                       # Time in different power states
+system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        23.57                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     817920                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    535530                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   74.74                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  42.07                       # Row buffer hit rate for writes
+system.physmem.avgGap                     19947945.64                       # Average gap between requests
+system.physmem.pageHitRate                      57.17                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 3880003680                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 2117065500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                4195752600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               4174344720                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3087888847680                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1190314271070                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           27321927289500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             31614497574750                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.711016                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   45452122728628                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1578675280000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    242820245005                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    245973030122                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 3713615640                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 2026278375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                4078440600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3911723280                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3098908325760                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1186342158240                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           27426639078000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             31725619619895                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.675231                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   45626361005854                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1584308960000                       # Time in different power states
+system.physmem_1.actEnergy                 3784278960                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 2064834750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                4340583000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               4073632560                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3087888847680                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1186461286245                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           27325307092500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             31613920555695                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.698811                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   45457733356018                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1578675280000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    234814164146                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    240362584982                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
 system.realview.nvmem.bytes_read::cpu0.inst          704                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst          640                       # Number of bytes read from this memory
@@ -372,41 +370,41 @@ system.realview.nvmem.num_reads::cpu1.data            1                       #
 system.realview.nvmem.num_reads::total             27                       # Number of read requests responded to by this memory
 system.realview.nvmem.bw_read::cpu0.inst           15                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst           13                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst           14                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_read::cpu1.data            0                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_read::total               29                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_inst_read::cpu0.inst           15                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst           13                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst           14                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_inst_read::total           28                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu0.inst           15                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst           13                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst           14                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total              29                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages                  1671                       # Number of full page size DMA writes.
-system.cf0.dma_write_bytes                    6846976                       # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs                         1674                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups              160314756                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted        112651620                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          7238532                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups           119384108                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               83018284                       # Number of BTB hits
+system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
+system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
+system.cpu0.branchPred.lookups              132137665                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         93617551                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          5999845                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            98810350                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               69427031                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            69.538807                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               19042266                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect           1248322                       # Number of incorrect RAS predictions.
-system.cpu0.branchPred.indirectLookups        4272460                       # Number of indirect predictor lookups.
-system.cpu0.branchPred.indirectHits           2939923                       # Number of indirect target hits.
-system.cpu0.branchPred.indirectMisses         1332537                       # Number of indirect misses.
-system.cpu0.branchPredindirectMispredicted       468796                       # Number of mispredicted indirect branches.
+system.cpu0.branchPred.BTBHitPct            70.262914                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               15260285                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect           1044115                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.indirectLookups        3387017                       # Number of indirect predictor lookups.
+system.cpu0.branchPred.indirectHits           2259695                       # Number of indirect target hits.
+system.cpu0.branchPred.indirectMisses         1127322                       # Number of indirect misses.
+system.cpu0.branchPredindirectMispredicted       409659                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -436,63 +434,64 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dtb.walker.walks                   329365                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               329365                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        11619                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        95372                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples       329365                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0         329365    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       329365                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples       106991                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 23090.091690                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 21491.120734                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 15706.739319                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535       105441     98.55%     98.55% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071         1327      1.24%     99.79% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607           42      0.04%     99.83% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143           76      0.07%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679           69      0.06%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215           15      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751           14      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287            6      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.walker.walks                   271762                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               271762                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        10351                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        74846                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples       271762                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0         271762    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       271762                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples        85197                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 23819.195512                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 22123.263295                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 14060.055266                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535        84296     98.94%     98.94% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071          776      0.91%     99.85% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607           35      0.04%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143           41      0.05%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679           35      0.04%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215            8      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total       106991                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total        85197                       # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walksPending::samples    734573704                       # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::0      734573704    100.00%    100.00% # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::total    734573704                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        95372     89.14%     89.14% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M        11619     10.86%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total       106991                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       329365                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkPageSizes::4K        74846     87.85%     87.85% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        10351     12.15%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total        85197                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       271762                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       329365                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       106991                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       271762                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        85197                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       106991                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       436356                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        85197                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       356959                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                   103710651                       # DTB read hits
-system.cpu0.dtb.read_misses                    276993                       # DTB read misses
-system.cpu0.dtb.write_hits                   90811723                       # DTB write hits
-system.cpu0.dtb.write_misses                    52372                       # DTB write misses
+system.cpu0.dtb.read_hits                    82756248                       # DTB read hits
+system.cpu0.dtb.read_misses                    224730                       # DTB read misses
+system.cpu0.dtb.write_hits                   74117187                       # DTB write hits
+system.cpu0.dtb.write_misses                    47032                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              43240                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                   1075                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   42132                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                     2205                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                 11314                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid              42591                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                   1052                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   34573                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                     2108                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  9506                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    11590                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses               103987644                       # DTB read accesses
-system.cpu0.dtb.write_accesses               90864095                       # DTB write accesses
+system.cpu0.dtb.perms_faults                    11030                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                82980978                       # DTB read accesses
+system.cpu0.dtb.write_accesses               74164219                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        194522374                       # DTB hits
-system.cpu0.dtb.misses                         329365                       # DTB misses
-system.cpu0.dtb.accesses                    194851739                       # DTB accesses
-system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.hits                        156873435                       # DTB hits
+system.cpu0.dtb.misses                         271762                       # DTB misses
+system.cpu0.dtb.accesses                    157145197                       # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -522,912 +521,906 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.cpu0.itb.walker.walks                    72209                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong                72209                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2          611                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3        59557                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples        72209                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0          72209    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        72209                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples        60168                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 25971.338585                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 23756.230706                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 17963.019846                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-32767        55134     91.63%     91.63% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-65535         3439      5.72%     97.35% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-98303            6      0.01%     97.36% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::98304-131071         1442      2.40%     99.76% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-163839           23      0.04%     99.79% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::163840-196607           16      0.03%     99.82% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-229375           52      0.09%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::229376-262143           23      0.04%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-294911            9      0.01%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::294912-327679           12      0.02%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-360447            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::360448-393215            4      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-491519            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total        60168                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.cpu0.itb.walker.walks                    60398                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                60398                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2          589                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        51882                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples        60398                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0          60398    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        60398                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        52471                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 25793.819443                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 24019.609428                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 15089.787613                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-32767        46836     89.26%     89.26% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-65535         4750      9.05%     98.31% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-98303           22      0.04%     98.36% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::98304-131071          772      1.47%     99.83% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-163839           22      0.04%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::163840-196607           15      0.03%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-229375           26      0.05%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::229376-262143            9      0.02%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-294911            3      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::294912-327679            5      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-360447            9      0.02%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::360448-393215            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-425983            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total        52471                       # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walksPending::samples    733851204                       # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::0      733851204    100.00%    100.00% # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::total    733851204                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        59557     98.98%     98.98% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M          611      1.02%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        60168                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::4K        51882     98.88%     98.88% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M          589      1.12%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        52471                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        72209                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        72209                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        60398                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        60398                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        60168                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        60168                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       132377                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   285203366                       # ITB inst hits
-system.cpu0.itb.inst_misses                     72209                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        52471                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        52471                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       112869                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   234456044                       # ITB inst hits
+system.cpu0.itb.inst_misses                     60398                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              43240                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                   1075                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   30424                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              42591                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                   1052                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   24118                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                   190431                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                   160109                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               285275575                       # ITB inst accesses
-system.cpu0.itb.hits                        285203366                       # DTB hits
-system.cpu0.itb.misses                          72209                       # DTB misses
-system.cpu0.itb.accesses                    285275575                       # DTB accesses
-system.cpu0.numPwrStateTransitions              26302                       # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples        13151                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean    3564690271.200593                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev   65409151988.663887                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::underflows         3759     28.58%     28.58% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10         9361     71.18%     99.76% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11            1      0.01%     99.77% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11            1      0.01%     99.78% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11            4      0.03%     99.81% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11            1      0.01%     99.82% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11            1      0.01%     99.83% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::5e+11-5.5e+11            2      0.02%     99.84% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11            1      0.01%     99.85% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11            1      0.01%     99.86% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::8.5e+11-9e+11            1      0.01%     99.86% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::overflows           18      0.14%    100.00% # Distribution of time spent in the clock gated state
+system.cpu0.itb.inst_accesses               234516442                       # ITB inst accesses
+system.cpu0.itb.hits                        234456044                       # DTB hits
+system.cpu0.itb.misses                          60398                       # DTB misses
+system.cpu0.itb.accesses                    234516442                       # DTB accesses
+system.cpu0.numPwrStateTransitions               8178                       # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples         4089                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean    11447226771.455124                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev   162386644618.467285                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows         2836     69.36%     69.36% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10         1230     30.08%     99.44% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11            1      0.02%     99.46% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11            2      0.05%     99.51% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11            2      0.05%     99.56% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11            1      0.02%     99.58% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11            1      0.02%     99.61% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11            1      0.02%     99.63% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11            1      0.02%     99.66% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::overflows           14      0.34%    100.00% # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::max_value 1988779311380                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total          13151                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON   566247484441                       # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 46879241756559                       # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles                      1132534446                       # number of cpu cycles simulated
+system.cpu0.pwrStateClkGateDist::max_value 7470355608744                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total           4089                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON   469062558520                       # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 46807710268480                       # Cumulative time (in ticks) in various power states
+system.cpu0.numCycles                       938130839                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                  532076805                       # Number of instructions committed
-system.cpu0.committedOps                    624758290                       # Number of ops (including micro ops) committed
-system.cpu0.discardedOps                     52154793                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends                     4664                       # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles                 93759282538                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi                              2.128517                       # CPI: cycles per instruction
-system.cpu0.ipc                              0.469811                       # IPC: instructions per cycle
-system.cpu0.op_class_0::No_OpClass                  0      0.00%      0.00% # Class of committed instruction
-system.cpu0.op_class_0::IntAlu              432780145     69.27%     69.27% # Class of committed instruction
-system.cpu0.op_class_0::IntMult               1412970      0.23%     69.50% # Class of committed instruction
-system.cpu0.op_class_0::IntDiv                  69899      0.01%     69.51% # Class of committed instruction
-system.cpu0.op_class_0::FloatAdd                    0      0.00%     69.51% # Class of committed instruction
-system.cpu0.op_class_0::FloatCmp                    0      0.00%     69.51% # Class of committed instruction
-system.cpu0.op_class_0::FloatCvt                    0      0.00%     69.51% # Class of committed instruction
-system.cpu0.op_class_0::FloatMult                   0      0.00%     69.51% # Class of committed instruction
-system.cpu0.op_class_0::FloatDiv                    0      0.00%     69.51% # Class of committed instruction
-system.cpu0.op_class_0::FloatSqrt                   0      0.00%     69.51% # Class of committed instruction
-system.cpu0.op_class_0::SimdAdd                     0      0.00%     69.51% # Class of committed instruction
-system.cpu0.op_class_0::SimdAddAcc                  0      0.00%     69.51% # Class of committed instruction
-system.cpu0.op_class_0::SimdAlu                     0      0.00%     69.51% # Class of committed instruction
-system.cpu0.op_class_0::SimdCmp                     0      0.00%     69.51% # Class of committed instruction
-system.cpu0.op_class_0::SimdCvt                     0      0.00%     69.51% # Class of committed instruction
-system.cpu0.op_class_0::SimdMisc                    0      0.00%     69.51% # Class of committed instruction
-system.cpu0.op_class_0::SimdMult                    0      0.00%     69.51% # Class of committed instruction
-system.cpu0.op_class_0::SimdMultAcc                 0      0.00%     69.51% # Class of committed instruction
-system.cpu0.op_class_0::SimdShift                   0      0.00%     69.51% # Class of committed instruction
-system.cpu0.op_class_0::SimdShiftAcc                0      0.00%     69.51% # Class of committed instruction
-system.cpu0.op_class_0::SimdSqrt                    0      0.00%     69.51% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatAdd                0      0.00%     69.51% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatAlu                0      0.00%     69.51% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatCmp                0      0.00%     69.51% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatCvt                0      0.00%     69.51% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatDiv                0      0.00%     69.51% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatMisc           79522      0.01%     69.52% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatMult               0      0.00%     69.52% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatMultAcc            0      0.00%     69.52% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatSqrt               0      0.00%     69.52% # Class of committed instruction
-system.cpu0.op_class_0::MemRead              99981749     16.00%     85.52% # Class of committed instruction
-system.cpu0.op_class_0::MemWrite             90434005     14.48%    100.00% # Class of committed instruction
+system.cpu0.committedInsts                  430200528                       # Number of instructions committed
+system.cpu0.committedOps                    505771410                       # Number of ops (including micro ops) committed
+system.cpu0.discardedOps                     45690974                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu0.numFetchSuspends                     3904                       # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles                 93616054941                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi                              2.180683                       # CPI: cycles per instruction
+system.cpu0.ipc                              0.458572                       # IPC: instructions per cycle
+system.cpu0.op_class_0::No_OpClass                  1      0.00%      0.00% # Class of committed instruction
+system.cpu0.op_class_0::IntAlu              351125189     69.42%     69.42% # Class of committed instruction
+system.cpu0.op_class_0::IntMult               1073769      0.21%     69.64% # Class of committed instruction
+system.cpu0.op_class_0::IntDiv                  52983      0.01%     69.65% # Class of committed instruction
+system.cpu0.op_class_0::FloatAdd                    0      0.00%     69.65% # Class of committed instruction
+system.cpu0.op_class_0::FloatCmp                    0      0.00%     69.65% # Class of committed instruction
+system.cpu0.op_class_0::FloatCvt                    0      0.00%     69.65% # Class of committed instruction
+system.cpu0.op_class_0::FloatMult                   0      0.00%     69.65% # Class of committed instruction
+system.cpu0.op_class_0::FloatDiv                    0      0.00%     69.65% # Class of committed instruction
+system.cpu0.op_class_0::FloatSqrt                   0      0.00%     69.65% # Class of committed instruction
+system.cpu0.op_class_0::SimdAdd                     0      0.00%     69.65% # Class of committed instruction
+system.cpu0.op_class_0::SimdAddAcc                  0      0.00%     69.65% # Class of committed instruction
+system.cpu0.op_class_0::SimdAlu                     0      0.00%     69.65% # Class of committed instruction
+system.cpu0.op_class_0::SimdCmp                     0      0.00%     69.65% # Class of committed instruction
+system.cpu0.op_class_0::SimdCvt                     0      0.00%     69.65% # Class of committed instruction
+system.cpu0.op_class_0::SimdMisc                    0      0.00%     69.65% # Class of committed instruction
+system.cpu0.op_class_0::SimdMult                    0      0.00%     69.65% # Class of committed instruction
+system.cpu0.op_class_0::SimdMultAcc                 0      0.00%     69.65% # Class of committed instruction
+system.cpu0.op_class_0::SimdShift                   0      0.00%     69.65% # Class of committed instruction
+system.cpu0.op_class_0::SimdShiftAcc                0      0.00%     69.65% # Class of committed instruction
+system.cpu0.op_class_0::SimdSqrt                    0      0.00%     69.65% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatAdd                8      0.00%     69.65% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatAlu                0      0.00%     69.65% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatCmp               13      0.00%     69.65% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatCvt               21      0.00%     69.65% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatDiv                0      0.00%     69.65% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatMisc           68782      0.01%     69.66% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatMult               0      0.00%     69.66% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatMultAcc            0      0.00%     69.66% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatSqrt               0      0.00%     69.66% # Class of committed instruction
+system.cpu0.op_class_0::MemRead              79655364     15.75%     85.41% # Class of committed instruction
+system.cpu0.op_class_0::MemWrite             73795280     14.59%    100.00% # Class of committed instruction
 system.cpu0.op_class_0::IprAccess                   0      0.00%    100.00% # Class of committed instruction
 system.cpu0.op_class_0::InstPrefetch                0      0.00%    100.00% # Class of committed instruction
-system.cpu0.op_class_0::total               624758290                       # Class of committed instruction
+system.cpu0.op_class_0::total               505771410                       # Class of committed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   13151                       # number of quiesce instructions executed
-system.cpu0.tickCycles                      847175236                       # Number of cycles that the object actually ticked
-system.cpu0.idleCycles                      285359210                       # Total number of cycles that the object has spent stopped
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements          6574289                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          508.066535                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          184992173                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          6574801                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            28.136543                       # Average number of references to valid blocks.
+system.cpu0.kern.inst.quiesce                    4089                       # number of quiesce instructions executed
+system.cpu0.tickCycles                      697846091                       # Number of cycles that the object actually ticked
+system.cpu0.idleCycles                      240284748                       # Total number of cycles that the object has spent stopped
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.tags.replacements          5497391                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          500.377946                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          148839422                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          5497903                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            27.072035                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle       5039429000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   508.066535                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.992317                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.992317                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   500.377946                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.977301                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.977301                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          211                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          229                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           72                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0           74                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          383                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           55                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        392594755                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       392594755                       # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data     95401287                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       95401287                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     84287466                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      84287466                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       321965                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       321965                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       280846                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       280846                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      2060188                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      2060188                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2061125                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      2061125                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    179969599                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       179969599                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    180291564                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      180291564                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      3840217                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      3840217                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      2718306                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      2718306                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       733729                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       733729                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       858022                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total       858022                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       199658                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       199658                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data       197397                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total       197397                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      7416545                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       7416545                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      8150274                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      8150274                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  59779296000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  59779296000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  54754909500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  54754909500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  28457275000                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total  28457275000                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2995014000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   2995014000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4953933500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total   4953933500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      3818500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total      3818500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 142991480500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 142991480500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 142991480500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 142991480500                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     99241504                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     99241504                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     87005772                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     87005772                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data      1055694                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total      1055694                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data      1138868                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total      1138868                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2259846                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      2259846                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2258522                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      2258522                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    187386144                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    187386144                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    188441838                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    188441838                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.038696                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.038696                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.031243                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.031243                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.695021                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.695021                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.753399                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.753399                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.088350                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.088350                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.087401                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.087401                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.039579                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.039579                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.043251                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.043251                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15566.645322                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 15566.645322                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20143.026392                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 20143.026392                       # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 33166.136766                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 33166.136766                       # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15000.721233                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15000.721233                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25096.295790                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25096.295790                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses        316768421                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       316768421                       # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.ReadReq_hits::cpu0.data     75978032                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       75978032                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     68482955                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      68482955                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       264842                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       264842                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       244065                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       244065                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1687572                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      1687572                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1654235                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      1654235                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    144705052                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       144705052                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    144969894                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      144969894                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      3066734                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      3066734                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      2419958                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      2419958                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       670609                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       670609                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       786129                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total       786129                       # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       148878                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       148878                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data       181031                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total       181031                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      6272821                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       6272821                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      6943430                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      6943430                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  47243422000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  47243422000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  49248110500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  49248110500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  26231986000                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total  26231986000                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2187373500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   2187373500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4323764500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total   4323764500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      2754000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total      2754000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 122723518500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 122723518500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 122723518500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 122723518500                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     79044766                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     79044766                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     70902913                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     70902913                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       935451                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       935451                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data      1030194                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total      1030194                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1836450                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      1836450                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1835266                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      1835266                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    150977873                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    150977873                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    151913324                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    151913324                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.038797                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.038797                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.034131                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.034131                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.716883                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.716883                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.763088                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.763088                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.081068                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.081068                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.098640                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.098640                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.041548                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.041548                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.045707                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.045707                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15405.125453                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 15405.125453                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20350.812080                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 20350.812080                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 33368.551472                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 33368.551472                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14692.389070                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14692.389070                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23884.111009                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23884.111009                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19280.066460                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 19280.066460                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17544.377097                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 17544.377097                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19564.326561                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 19564.326561                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17674.768594                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 17674.768594                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks      6574291                       # number of writebacks
-system.cpu0.dcache.writebacks::total          6574291                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       237792                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       237792                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1117306                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1117306                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data           90                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::total           90                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        48445                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        48445                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data           60                       # number of StoreCondReq MSHR hits
-system.cpu0.dcache.StoreCondReq_mshr_hits::total           60                       # number of StoreCondReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1355188                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1355188                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1355188                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1355188                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3602425                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      3602425                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1601000                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1601000                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       732137                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       732137                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       857932                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total       857932                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       151213                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       151213                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       197337                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total       197337                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      6061357                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      6061357                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      6793494                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      6793494                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        29793                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        29793                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        29400                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        29400                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        59193                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        59193                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  50925119500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  50925119500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  31536308500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  31536308500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  16544300500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  16544300500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  27594364000                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  27594364000                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1964885000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1964885000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   4754516500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   4754516500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      3441500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      3441500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 110055792000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 110055792000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 126600092500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 126600092500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5675765000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5675765000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5675765000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   5675765000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036300                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036300                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018401                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018401                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.693513                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.693513                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.753320                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.753320                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.066913                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.066913                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.087374                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.087374                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.032347                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.032347                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.036051                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.036051                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14136.344129                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14136.344129                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19697.881636                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19697.881636                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22597.274144                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22597.274144                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 32163.812517                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 32163.812517                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12994.153942                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12994.153942                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24093.385934                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24093.385934                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks      5497393                       # number of writebacks
+system.cpu0.dcache.writebacks::total          5497393                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       200047                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       200047                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1012976                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1012976                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data           94                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::total           94                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        39271                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        39271                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data           90                       # number of StoreCondReq MSHR hits
+system.cpu0.dcache.StoreCondReq_mshr_hits::total           90                       # number of StoreCondReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1213117                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1213117                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1213117                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1213117                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2866687                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      2866687                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1406982                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1406982                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       668415                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       668415                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       786035                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total       786035                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       109607                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       109607                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       180941                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total       180941                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      5059704                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      5059704                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      5728119                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      5728119                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        20634                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        20634                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        22275                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        22275                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        42909                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        42909                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  39457015000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  39457015000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  27671793000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  27671793000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  15966528000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  15966528000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  25439405000                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  25439405000                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1452927000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1452927000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   4140525000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   4140525000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      2476500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2476500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  92568213000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  92568213000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 108534741000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 108534741000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   4015086500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   4015086500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   4015086500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   4015086500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036267                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036267                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019844                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019844                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.714538                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.714538                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.762997                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.762997                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059684                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059684                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.098591                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.098591                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.033513                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.033513                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.037706                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.037706                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13763.977372                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13763.977372                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19667.481887                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19667.481887                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23887.147954                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23887.147954                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 32364.214062                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 32364.214062                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13255.786583                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13255.786583                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22883.287923                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22883.287923                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18156.955942                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18156.955942                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18635.490441                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18635.490441                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190506.662639                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190506.662639                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95885.746625                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 95885.746625                       # average overall mshr uncacheable latency
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements         10998491                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.932591                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          274007938                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs         10999003                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            24.912070                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      22037323000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.932591                       # Average occupied blocks per requestor
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18295.183473                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18295.183473                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18947.710584                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18947.710584                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 194585.950373                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 194585.950373                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93572.129390                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93572.129390                       # average overall mshr uncacheable latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.tags.replacements          9280608                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.932285                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          225009210                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          9281120                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            24.243756                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      22204306000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.932285                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999868                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.999868                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          207                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          273                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           32                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          121                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          312                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           79                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        581012885                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       581012885                       # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst    274007938                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      274007938                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    274007938                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       274007938                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    274007938                       # number of overall hits
-system.cpu0.icache.overall_hits::total      274007938                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst     10999003                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total     10999003                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst     10999003                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total      10999003                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst     10999003                       # number of overall misses
-system.cpu0.icache.overall_misses::total     10999003                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 111429437000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 111429437000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 111429437000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 111429437000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 111429437000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 111429437000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    285006941                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    285006941                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    285006941                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    285006941                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    285006941                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    285006941                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.038592                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.038592                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.038592                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.038592                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.038592                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.038592                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10130.867043                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 10130.867043                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10130.867043                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 10130.867043                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10130.867043                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 10130.867043                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        477861809                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       477861809                       # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.ReadReq_hits::cpu0.inst    225009210                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      225009210                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    225009210                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       225009210                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    225009210                       # number of overall hits
+system.cpu0.icache.overall_hits::total      225009210                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      9281130                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      9281130                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      9281130                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       9281130                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      9281130                       # number of overall misses
+system.cpu0.icache.overall_misses::total      9281130                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  94226606500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  94226606500                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  94226606500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  94226606500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  94226606500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  94226606500                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    234290340                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    234290340                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    234290340                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    234290340                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    234290340                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    234290340                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.039614                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.039614                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.039614                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.039614                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.039614                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.039614                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10152.492908                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 10152.492908                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10152.492908                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 10152.492908                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10152.492908                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 10152.492908                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks     10998491                       # number of writebacks
-system.cpu0.icache.writebacks::total         10998491                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst     10999003                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total     10999003                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst     10999003                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total     10999003                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst     10999003                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total     10999003                       # number of overall MSHR misses
+system.cpu0.icache.writebacks::writebacks      9280608                       # number of writebacks
+system.cpu0.icache.writebacks::total          9280608                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      9281130                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      9281130                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      9281130                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      9281130                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      9281130                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      9281130                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        52300                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total        52300                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        52300                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total        52300                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 105929935500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 105929935500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 105929935500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 105929935500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 105929935500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 105929935500                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  89586042000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  89586042000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  89586042000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  89586042000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  89586042000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  89586042000                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   4836784500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   4836784500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   4836784500                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total   4836784500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.038592                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.038592                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.038592                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.038592                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.038592                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.038592                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9630.867043                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9630.867043                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9630.867043                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total  9630.867043                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9630.867043                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total  9630.867043                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.039614                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.039614                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.039614                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.039614                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.039614                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.039614                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9652.492962                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9652.492962                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9652.492962                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total  9652.492962                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9652.492962                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total  9652.492962                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92481.539197                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92481.539197                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92481.539197                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92481.539197                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      8833822                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      8835143                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit         1166                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      7507862                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      7509065                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit         1069                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage      1192777                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.tags.replacements         3147716                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16192.217188                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs          27546589                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs         3163437                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            8.707804                       # Average number of references to valid blocks.
+system.cpu0.l2cache.prefetcher.pfSpanPage       942183                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.cpu0.l2cache.tags.replacements         2584098                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       15590.889787                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs          13248667                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs         2600019                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            5.095604                       # Average number of references to valid blocks.
 system.cpu0.l2cache.tags.warmup_cycle      5661168000                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 15379.701531                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    70.199902                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    67.449935                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   674.865820                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.938702                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.004285                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.004117                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.041191                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.988295                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1251                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023           80                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14390                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::0            7                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           16                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          214                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          985                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4           29                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_blocks::writebacks 15296.249521                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    39.752726                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    22.010194                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   232.877346                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.933609                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.002426                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.001343                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.014214                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.951592                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022          376                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023           68                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15477                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::0           12                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           15                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          104                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          124                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          121                       # Occupied blocks per task id
 system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
 system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           13                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           66                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          230                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          603                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4671                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         8629                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4          257                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.076355                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.004883                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.878296                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses       591522987                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses      591522987                       # Number of data accesses
-system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       626255                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       186723                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total        812978                       # number of ReadReq hits
-system.cpu0.l2cache.WritebackDirty_hits::writebacks      4288810                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackDirty_hits::total      4288810                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackClean_hits::writebacks     13280453                       # number of WritebackClean hits
-system.cpu0.l2cache.WritebackClean_hits::total     13280453                       # number of WritebackClean hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data          665                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total          665                       # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data            1                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::total            1                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data      1035920                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total      1035920                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst     10174002                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total     10174002                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      3369103                       # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total      3369103                       # number of ReadSharedReq hits
-system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       227555                       # number of InvalidateReq hits
-system.cpu0.l2cache.InvalidateReq_hits::total       227555                       # number of InvalidateReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       626255                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker       186723                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst     10174002                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data      4405023                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total       15392003                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       626255                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker       186723                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst     10174002                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data      4405023                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total      15392003                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        13618                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         9516                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total        23134                       # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       275991                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total       275991                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       197331                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total       197331                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            5                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::total            5                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data       297475                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total       297475                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       825000                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::total       825000                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data      1116183                       # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total      1116183                       # number of ReadSharedReq misses
-system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       628029                       # number of InvalidateReq misses
-system.cpu0.l2cache.InvalidateReq_misses::total       628029                       # number of InvalidateReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        13618                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker         9516                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst       825000                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data      1413658                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total      2261792                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        13618                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker         9516                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst       825000                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data      1413658                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total      2261792                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    516990000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    406929500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total    923919500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   2174724500                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total   2174724500                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   1540108000                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   1540108000                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      3340999                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      3340999                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  14927255997                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total  14927255997                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  27980842000                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::total  27980842000                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  40509457995                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::total  40509457995                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data    326706500                       # number of InvalidateReq miss cycles
-system.cpu0.l2cache.InvalidateReq_miss_latency::total    326706500                       # number of InvalidateReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    516990000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    406929500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst  27980842000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data  55436713992                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total  84341475492                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    516990000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    406929500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst  27980842000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data  55436713992                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total  84341475492                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       639873                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       196239                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total       836112                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::writebacks      4288810                       # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::total      4288810                       # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::writebacks     13280453                       # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::total     13280453                       # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       276656                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total       276656                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       197332                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total       197332                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            5                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            5                       # number of SCUpgradeFailReq accesses(hits+misses)
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-system.cpu0.l2cache.ReadExReq_accesses::total      1333395                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst     10999002                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::total     10999002                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      4485286                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::total      4485286                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       855584                       # number of InvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.InvalidateReq_accesses::total       855584                       # number of InvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       639873                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       196239                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst     10999002                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data      5818681                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total     17653795                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       639873                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       196239                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst     10999002                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data      5818681                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total     17653795                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.021282                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.048492                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.027669                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.997596                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.997596                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.999995                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.999995                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           21                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           33                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          194                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1649                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4407                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         5650                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3577                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.022949                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.004150                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.944641                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses       507607175                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses      507607175                       # Number of data accesses
+system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       496900                       # number of ReadReq hits
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+system.cpu0.l2cache.ReadCleanReq_miss_latency::total  23732034500                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  33660637494                       # number of ReadSharedReq miss cycles
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+system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data    333947500                       # number of InvalidateReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::total    333947500                       # number of InvalidateReq miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    614702000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    331371000                       # number of demand (read+write) miss cycles
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+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    331371000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst  23732034500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.data  47311513493                       # number of overall miss cycles
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+system.cpu0.l2cache.WritebackDirty_accesses::total      3675506                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::writebacks     11099665                       # number of WritebackClean accesses(hits+misses)
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+system.cpu0.l2cache.UpgradeReq_accesses::total       245426                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       180938                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total       180938                       # number of SCUpgradeReq accesses(hits+misses)
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+system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       784086                       # number of InvalidateReq accesses(hits+misses)
+system.cpu0.l2cache.InvalidateReq_accesses::total       784086                       # number of InvalidateReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       516703                       # number of demand (read+write) accesses
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+system.cpu0.l2cache.overall_accesses::cpu0.data      4814182                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total     14776421                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.038326                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.058507                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.043197                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data            1                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.223096                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.223096                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.075007                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.075007                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.248854                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.248854                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.734035                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.734035                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.021282                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.048492                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.075007                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.242952                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.128119                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.021282                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.048492                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.075007                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.242952                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.128119                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 37963.724482                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 42762.662884                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 39937.732342                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  7879.693541                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  7879.693541                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  7804.693637                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  7804.693637                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 668199.800000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 668199.800000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50179.867206                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50179.867206                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 33916.172121                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 33916.172121                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 36292.846240                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 36292.846240                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data   520.209258                       # average InvalidateReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total   520.209258                       # average InvalidateReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 37963.724482                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 42762.662884                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 33916.172121                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 39215.081718                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 37289.669206                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 37963.724482                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 42762.662884                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 33916.172121                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 39215.081718                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 37289.669206                       # average overall miss latency
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.238136                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.238136                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.073594                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.073594                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.261748                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.261748                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.742237                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.742237                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.038326                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.058507                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.073594                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.256009                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.131624                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.038326                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.058507                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.073594                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.256009                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.131624                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 31040.852396                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 34449.630939                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32155.291958                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  3562.670622                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  3562.670622                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  1632.266301                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  1632.266301                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 794666.333333                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 794666.333333                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 48995.832926                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 48995.832926                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 34744.924865                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 34744.924865                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 35288.754773                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 35288.754773                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data   573.814646                       # average InvalidateReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total   573.814646                       # average InvalidateReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 31040.852396                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 34449.630939                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34744.924865                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38387.371026                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 37013.914607                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 31040.852396                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 34449.630939                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34744.924865                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38387.371026                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 37013.914607                       # average overall miss latency
 system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.l2cache.unused_prefetches           56740                       # number of HardPF blocks evicted w/o reference
-system.cpu0.l2cache.writebacks::writebacks      1791276                       # number of writebacks
-system.cpu0.l2cache.writebacks::total         1791276                       # number of writebacks
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            1                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker            4                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::total            5                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data        10486                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total        10486                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           14                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           14                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data         1072                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total         1072                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data            4                       # number of InvalidateReq MSHR hits
-system.cpu0.l2cache.InvalidateReq_mshr_hits::total            4                       # number of InvalidateReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            1                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker            4                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           14                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data        11558                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total        11577                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker            1                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker            4                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           14                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data        11558                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total        11577                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        13617                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         9512                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total        23129                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       884711                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       884711                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       275991                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total       275991                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       197331                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       197331                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            5                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            5                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       286989                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total       286989                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       824986                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       824986                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data      1115111                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total      1115111                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       628025                       # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::total       628025                       # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        13617                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         9512                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       824986                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1402100                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total      2250215                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        13617                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         9512                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       824986                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1402100                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       884711                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total      3134926                       # number of overall MSHR misses
+system.cpu0.l2cache.unused_prefetches           44195                       # number of HardPF blocks evicted w/o reference
+system.cpu0.l2cache.writebacks::writebacks      1595582                       # number of writebacks
+system.cpu0.l2cache.writebacks::total         1595582                       # number of writebacks
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker           11                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker           92                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_hits::total          103                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         9447                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::total         9447                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           12                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           12                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          778                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          778                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data            2                       # number of InvalidateReq MSHR hits
+system.cpu0.l2cache.InvalidateReq_mshr_hits::total            2                       # number of InvalidateReq MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker           11                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker           92                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           12                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.data        10225                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::total        10340                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker           11                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker           92                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           12                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.data        10225                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::total        10340                       # number of overall MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        19792                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         9527                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::total        29319                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       781759                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::total       781759                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       245426                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total       245426                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       180938                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       180938                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            3                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            3                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       269166                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::total       269166                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       683024                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       683024                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       953085                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       953085                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       581976                       # number of InvalidateReq MSHR misses
+system.cpu0.l2cache.InvalidateReq_mshr_misses::total       581976                       # number of InvalidateReq MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        19792                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         9527                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       683024                       # number of demand (read+write) MSHR misses
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+system.cpu0.l2cache.demand_mshr_misses::total      1934594                       # number of demand (read+write) MSHR misses
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+system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1222251                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       781759                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::total      2716353                       # number of overall MSHR misses
 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        52300                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        29793                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        82093                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        29400                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        29400                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        20634                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        72934                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        22275                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        22275                       # number of WriteReq MSHR uncacheable
 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        52300                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        59193                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total       111493                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    435264000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    349787000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    785051000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  42685466504                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  42685466504                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   5679653996                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   5679653996                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   3269289499                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   3269289499                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      2944999                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2944999                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  11923656997                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  11923656997                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  23030463500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  23030463500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  33712054495                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  33712054495                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  20896498500                       # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  20896498500                       # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    435264000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    349787000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  23030463500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  45635711492                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total  69451225992                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    435264000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    349787000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  23030463500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  45635711492                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  42685466504                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total 112136692496                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        42909                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        95209                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    495686000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    272683000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    768369000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  38385674547                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  38385674547                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   4516919997                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   4516919997                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   2779143996                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   2779143996                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      2017999                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2017999                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  10852711499                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  10852711499                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  19633488000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  19633488000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  27859151994                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  27859151994                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  19308557500                       # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  19308557500                       # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    495686000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    272683000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  19633488000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  38711863493                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total  59113720493                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    495686000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    272683000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  19633488000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  38711863493                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  38385674547                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total  97499395040                       # number of overall MSHR miss cycles
 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   4418384500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5437142000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   9855526500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   3849707000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   8268091500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   4418384500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   5437142000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   9855526500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.021281                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.048472                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.027663                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   3849707000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   8268091500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.038304                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.057948                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.043046                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.997596                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.997596                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.999995                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.999995                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.215232                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.215232                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.075006                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.075006                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.248615                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.248615                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.734031                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.734031                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.021281                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.048472                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.075006                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.240965                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.127464                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.021281                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.048472                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.075006                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.240965                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.230062                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.230062                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.073593                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.073593                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.261534                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.261534                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.742235                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.742235                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.038304                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.057948                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.073593                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.253885                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.130924                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.038304                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.057948                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.073593                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.253885                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.177578                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 31964.749945                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 36773.233810                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 33942.280254                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48247.921077                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 48247.921077                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20579.127566                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20579.127566                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16567.541334                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16567.541334                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 588999.800000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 588999.800000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41547.435606                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41547.435606                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 27916.187063                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27916.187063                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 30232.016808                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30232.016808                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 33273.354564                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 33273.354564                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 31964.749945                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 36773.233810                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 27916.187063                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 32548.114608                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30864.262300                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 31964.749945                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36773.233810                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 27916.187063                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 32548.114608                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48247.921077                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35770.124238                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.183830                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25044.765562                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28622.126588                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26207.203520                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49101.672698                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49101.672698                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18404.407019                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18404.407019                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15359.648034                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15359.648034                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 672666.333333                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 672666.333333                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40319.771067                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40319.771067                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 28744.946005                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28744.946005                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 29230.500946                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29230.500946                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 33177.583784                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 33177.583784                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25044.765562                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 28622.126588                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 28744.946005                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31672.597112                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30556.137615                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25044.765562                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 28622.126588                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 28744.946005                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31672.597112                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49101.672698                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35893.492134                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84481.539197                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182497.298023                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 120053.189675                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 186571.047785                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 113364.020896                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84481.539197                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 91854.476036                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 88395.921717                       # average overall mshr uncacheable latency
-system.cpu0.toL2Bus.snoop_filter.tot_requests     36072564                       # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests     18399437                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         3515                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops      2427957                       # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops      2427386                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops          571                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.cpu0.toL2Bus.trans_dist::ReadReq       1003133                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp     16585926                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        29400                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        29400                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty      6083435                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean     13283967                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict      3350152                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq      1133444                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFResp            1                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq       490495                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       347636                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       543136                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           77                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          138                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq      1366077                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp      1342549                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq     10999003                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq      5499511                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq       903440                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateResp       855584                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     33101096                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     21166131                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       412052                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1345098                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total         56024377                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side   1411186752                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    800229141                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1569912                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      5118984                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total        2218104789                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    7999072                       # Total snoops (count)
-system.cpu0.toL2Bus.snoopTraffic            122429440                       # Total snoop traffic (bytes)
-system.cpu0.toL2Bus.snoop_fanout::samples     26916994                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       0.103450                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.304616                       # Request fanout histogram
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 89717.937962                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 86841.490825                       # average overall mshr uncacheable latency
+system.cpu0.toL2Bus.snoop_filter.tot_requests     30377137                       # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests     15497883                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         2826                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops       666100                       # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       666086                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops           14                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.cpu0.toL2Bus.trans_dist::ReadReq        826394                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp     13852976                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate            2                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        22275                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        22275                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty      5277668                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean     11102490                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict      1369040                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       998456                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq       452524                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       330100                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       496609                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           57                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          115                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq      1203701                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp      1179860                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      9281130                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4723846                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq       838465                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateResp       784086                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     27947466                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     17813968                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       344869                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1089699                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total         47196002                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side   1191298304                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    667170422                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1315256                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      4133624                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total        1863917606                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    5747559                       # Total snoops (count)
+system.cpu0.toL2Bus.snoopTraffic            110232304                       # Total snoop traffic (bytes)
+system.cpu0.toL2Bus.snoop_fanout::samples     21648150                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       0.044453                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.206103                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0          24132997     89.66%     89.66% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1           2783426     10.34%    100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2               571      0.00%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0          20685836     95.55%     95.55% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1            962300      4.45%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2                14      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total      26916994                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy   35963769502                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total      21648150                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy   30255355989                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    196401052                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    202143120                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy  16580139110                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy  14002739292                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   9441182874                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   7861824025                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy    215851922                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy    180564794                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy    705346257                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy    573087816                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups              118915951                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         85033049                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect          5367569                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            89750040                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               63411692                       # Number of BTB hits
+system.cpu1.branchPred.lookups              142890193                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted        101173603                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect          6378415                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups           107083119                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               74895456                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            70.653664                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS               13468810                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect            887929                       # Number of incorrect RAS predictions.
-system.cpu1.branchPred.indirectLookups        3084567                       # Number of indirect predictor lookups.
-system.cpu1.branchPred.indirectHits           1998882                       # Number of indirect target hits.
-system.cpu1.branchPred.indirectMisses         1085685                       # Number of indirect misses.
-system.cpu1.branchPredindirectMispredicted       396796                       # Number of mispredicted indirect branches.
-system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
+system.cpu1.branchPred.BTBHitPct            69.941422                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS               16732142                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect           1061167                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.indirectLookups        3812146                       # Number of indirect predictor lookups.
+system.cpu1.branchPred.indirectHits           2601182                       # Number of indirect target hits.
+system.cpu1.branchPred.indirectMisses         1210964                       # Number of indirect misses.
+system.cpu1.branchPredindirectMispredicted       435637                       # Number of mispredicted indirect branches.
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1457,69 +1450,63 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dtb.walker.walks                   246313                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong               246313                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         8582                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        75463                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples       246313                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0         246313    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total       246313                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples        84045                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 22346.070557                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 21064.042846                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 12361.258067                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-32767        79296     94.35%     94.35% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-65535         4004      4.76%     99.11% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-98303          175      0.21%     99.32% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::98304-131071          458      0.54%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-163839           22      0.03%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::163840-196607           12      0.01%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-229375           27      0.03%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::229376-262143           10      0.01%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-294911           13      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::294912-327679           13      0.02%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-360447            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::360448-393215            3      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-425983            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-491519            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total        84045                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples   -766256056                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0     -766256056    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total   -766256056                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        75463     89.79%     89.79% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M         8582     10.21%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total        84045                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       246313                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.walker.walks                   301450                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               301450                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        14052                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        94528                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples       301450                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0         301450    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total       301450                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples       108580                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 23842.945294                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 21967.326975                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 15932.247293                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535       107036     98.58%     98.58% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071         1312      1.21%     99.79% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607           57      0.05%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143           69      0.06%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679           74      0.07%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215           19      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751            9      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total       108580                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples   -588118056                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0     -588118056    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total   -588118056                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        94528     87.06%     87.06% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M        14052     12.94%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total       108580                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       301450                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       246313                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        84045                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       301450                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       108580                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        84045                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total       330358                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       108580                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total       410030                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    74020776                       # DTB read hits
-system.cpu1.dtb.read_misses                    200548                       # DTB read misses
-system.cpu1.dtb.write_hits                   65603987                       # DTB write hits
-system.cpu1.dtb.write_misses                    45765                       # DTB write misses
+system.cpu1.dtb.read_hits                    92214946                       # DTB read hits
+system.cpu1.dtb.read_misses                    251350                       # DTB read misses
+system.cpu1.dtb.write_hits                   79863458                       # DTB write hits
+system.cpu1.dtb.write_misses                    50100                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              43240                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                   1075                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   34845                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      889                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  6796                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid              42591                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                   1052                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   41485                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                     1017                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  8355                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    11277                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                74221324                       # DTB read accesses
-system.cpu1.dtb.write_accesses               65649752                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    11459                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                92466296                       # DTB read accesses
+system.cpu1.dtb.write_accesses               79913558                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        139624763                       # DTB hits
-system.cpu1.dtb.misses                         246313                       # DTB misses
-system.cpu1.dtb.accesses                    139871076                       # DTB accesses
-system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.hits                        172078404                       # DTB hits
+system.cpu1.dtb.misses                         301450                       # DTB misses
+system.cpu1.dtb.accesses                    172379854                       # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1549,899 +1536,892 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.cpu1.itb.walker.walks                    60327                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong                60327                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2          545                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        52409                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples        60327                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0          60327    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        60327                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        52954                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 24879.980738                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 23402.458623                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 13318.614145                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-32767        48523     91.63%     91.63% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-65535         3764      7.11%     98.74% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-98303           13      0.02%     98.76% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::98304-131071          577      1.09%     99.85% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-163839           18      0.03%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::163840-196607            8      0.02%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-229375           20      0.04%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::229376-262143           20      0.04%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-294911            3      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::294912-327679            4      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-360447            1      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::360448-393215            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.cpu1.itb.walker.walks                    68405                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                68405                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2          536                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        57692                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples        68405                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0          68405    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        68405                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        58228                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 26184.473106                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 23792.146832                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 18243.083639                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-32767        52664     90.44%     90.44% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-65535         3935      6.76%     97.20% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-98303           14      0.02%     97.23% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::98304-131071         1454      2.50%     99.72% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-163839           38      0.07%     99.79% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::163840-196607           17      0.03%     99.82% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-229375           63      0.11%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::229376-262143           12      0.02%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-294911           10      0.02%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::294912-327679           10      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-360447            7      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::360448-393215            3      0.01%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walkCompletionTime::393216-425983            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        52954                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples   -766782556                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0     -766782556    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total   -766782556                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        52409     98.97%     98.97% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M          545      1.03%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        52954                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkCompletionTime::total        58228                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples   -588816556                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0     -588816556    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total   -588816556                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K        57692     99.08%     99.08% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M          536      0.92%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        58228                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        60327                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total        60327                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        68405                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        68405                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        52954                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        52954                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       113281                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   210682225                       # ITB inst hits
-system.cpu1.itb.inst_misses                     60327                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        58228                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        58228                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       126633                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   253981708                       # ITB inst hits
+system.cpu1.itb.inst_misses                     68405                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              43240                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                   1075                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   24520                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              42591                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                   1052                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   29878                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                   163777                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                   186858                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               210742552                       # ITB inst accesses
-system.cpu1.itb.hits                        210682225                       # DTB hits
-system.cpu1.itb.misses                          60327                       # DTB misses
-system.cpu1.itb.accesses                    210742552                       # DTB accesses
-system.cpu1.numPwrStateTransitions              10392                       # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples         5196                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean    9053828227.255966                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev   188730440437.234528                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::underflows         3531     67.96%     67.96% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1000-5e+10         1645     31.66%     99.62% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::5e+10-1e+11            9      0.17%     99.79% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11            1      0.02%     99.81% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11            1      0.02%     99.83% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11            1      0.02%     99.85% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12            1      0.02%     99.87% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::overflows            7      0.13%    100.00% # Distribution of time spent in the clock gated state
+system.cpu1.itb.inst_accesses               254050113                       # ITB inst accesses
+system.cpu1.itb.hits                        253981708                       # DTB hits
+system.cpu1.itb.misses                          68405                       # DTB misses
+system.cpu1.itb.accesses                    254050113                       # DTB accesses
+system.cpu1.numPwrStateTransitions              29008                       # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples        14504                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean    3226000342.121070                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev   122202778079.734619                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows         4515     31.13%     31.13% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10         9966     68.71%     99.84% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5e+10-1e+11            7      0.05%     99.89% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11            3      0.02%     99.91% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11            1      0.01%     99.92% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11            1      0.01%     99.92% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11            1      0.01%     99.93% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::overflows           10      0.07%    100.00% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::max_value 7351146453012                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total           5196                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON   401797772178                       # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 47043691468822                       # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles                       803603609                       # number of cpu cycles simulated
+system.cpu1.pwrStateClkGateDist::max_value 11813587669000                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total          14504                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON   486863864876                       # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 46789908962124                       # Cumulative time (in ticks) in various power states
+system.cpu1.numCycles                       973770006                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                  379085635                       # Number of instructions committed
-system.cpu1.committedOps                    446824897                       # Number of ops (including micro ops) committed
-system.cpu1.discardedOps                     44295367                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends                     4823                       # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles                 94088042190                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi                              2.119847                       # CPI: cycles per instruction
-system.cpu1.ipc                              0.471732                       # IPC: instructions per cycle
-system.cpu1.op_class_0::No_OpClass                  1      0.00%      0.00% # Class of committed instruction
-system.cpu1.op_class_0::IntAlu              309274392     69.22%     69.22% # Class of committed instruction
-system.cpu1.op_class_0::IntMult                866353      0.19%     69.41% # Class of committed instruction
-system.cpu1.op_class_0::IntDiv                  49212      0.01%     69.42% # Class of committed instruction
-system.cpu1.op_class_0::FloatAdd                    0      0.00%     69.42% # Class of committed instruction
-system.cpu1.op_class_0::FloatCmp                    0      0.00%     69.42% # Class of committed instruction
-system.cpu1.op_class_0::FloatCvt                    0      0.00%     69.42% # Class of committed instruction
-system.cpu1.op_class_0::FloatMult                   0      0.00%     69.42% # Class of committed instruction
-system.cpu1.op_class_0::FloatDiv                    0      0.00%     69.42% # Class of committed instruction
-system.cpu1.op_class_0::FloatSqrt                   0      0.00%     69.42% # Class of committed instruction
-system.cpu1.op_class_0::SimdAdd                     0      0.00%     69.42% # Class of committed instruction
-system.cpu1.op_class_0::SimdAddAcc                  0      0.00%     69.42% # Class of committed instruction
-system.cpu1.op_class_0::SimdAlu                     0      0.00%     69.42% # Class of committed instruction
-system.cpu1.op_class_0::SimdCmp                     0      0.00%     69.42% # Class of committed instruction
-system.cpu1.op_class_0::SimdCvt                     0      0.00%     69.42% # Class of committed instruction
-system.cpu1.op_class_0::SimdMisc                    0      0.00%     69.42% # Class of committed instruction
-system.cpu1.op_class_0::SimdMult                    0      0.00%     69.42% # Class of committed instruction
-system.cpu1.op_class_0::SimdMultAcc                 0      0.00%     69.42% # Class of committed instruction
-system.cpu1.op_class_0::SimdShift                   0      0.00%     69.42% # Class of committed instruction
-system.cpu1.op_class_0::SimdShiftAcc                0      0.00%     69.42% # Class of committed instruction
-system.cpu1.op_class_0::SimdSqrt                    0      0.00%     69.42% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatAdd                8      0.00%     69.42% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatAlu                0      0.00%     69.42% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatCmp               13      0.00%     69.42% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatCvt               21      0.00%     69.42% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatDiv                0      0.00%     69.42% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatMisc           34424      0.01%     69.43% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatMult               0      0.00%     69.43% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatMultAcc            0      0.00%     69.43% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatSqrt               0      0.00%     69.43% # Class of committed instruction
-system.cpu1.op_class_0::MemRead              71272038     15.95%     85.38% # Class of committed instruction
-system.cpu1.op_class_0::MemWrite             65328435     14.62%    100.00% # Class of committed instruction
+system.cpu1.committedInsts                  467062034                       # Number of instructions committed
+system.cpu1.committedOps                    549524480                       # Number of ops (including micro ops) committed
+system.cpu1.discardedOps                     49354477                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu1.numFetchSuspends                     5829                       # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles                 93580668477                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi                              2.084884                       # CPI: cycles per instruction
+system.cpu1.ipc                              0.479643                       # IPC: instructions per cycle
+system.cpu1.op_class_0::No_OpClass                  0      0.00%      0.00% # Class of committed instruction
+system.cpu1.op_class_0::IntAlu              379758717     69.11%     69.11% # Class of committed instruction
+system.cpu1.op_class_0::IntMult               1174710      0.21%     69.32% # Class of committed instruction
+system.cpu1.op_class_0::IntDiv                  62873      0.01%     69.33% # Class of committed instruction
+system.cpu1.op_class_0::FloatAdd                    0      0.00%     69.33% # Class of committed instruction
+system.cpu1.op_class_0::FloatCmp                    0      0.00%     69.33% # Class of committed instruction
+system.cpu1.op_class_0::FloatCvt                    0      0.00%     69.33% # Class of committed instruction
+system.cpu1.op_class_0::FloatMult                   0      0.00%     69.33% # Class of committed instruction
+system.cpu1.op_class_0::FloatDiv                    0      0.00%     69.33% # Class of committed instruction
+system.cpu1.op_class_0::FloatSqrt                   0      0.00%     69.33% # Class of committed instruction
+system.cpu1.op_class_0::SimdAdd                     0      0.00%     69.33% # Class of committed instruction
+system.cpu1.op_class_0::SimdAddAcc                  0      0.00%     69.33% # Class of committed instruction
+system.cpu1.op_class_0::SimdAlu                     0      0.00%     69.33% # Class of committed instruction
+system.cpu1.op_class_0::SimdCmp                     0      0.00%     69.33% # Class of committed instruction
+system.cpu1.op_class_0::SimdCvt                     0      0.00%     69.33% # Class of committed instruction
+system.cpu1.op_class_0::SimdMisc                    0      0.00%     69.33% # Class of committed instruction
+system.cpu1.op_class_0::SimdMult                    0      0.00%     69.33% # Class of committed instruction
+system.cpu1.op_class_0::SimdMultAcc                 0      0.00%     69.33% # Class of committed instruction
+system.cpu1.op_class_0::SimdShift                   0      0.00%     69.33% # Class of committed instruction
+system.cpu1.op_class_0::SimdShiftAcc                0      0.00%     69.33% # Class of committed instruction
+system.cpu1.op_class_0::SimdSqrt                    0      0.00%     69.33% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatAdd                0      0.00%     69.33% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatAlu                0      0.00%     69.33% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatCmp                0      0.00%     69.33% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatCvt                0      0.00%     69.33% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatDiv                0      0.00%     69.33% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatMisc           42788      0.01%     69.34% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatMult               0      0.00%     69.34% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatMultAcc            0      0.00%     69.34% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatSqrt               0      0.00%     69.34% # Class of committed instruction
+system.cpu1.op_class_0::MemRead              88942339     16.19%     85.53% # Class of committed instruction
+system.cpu1.op_class_0::MemWrite             79543053     14.47%    100.00% # Class of committed instruction
 system.cpu1.op_class_0::IprAccess                   0      0.00%    100.00% # Class of committed instruction
 system.cpu1.op_class_0::InstPrefetch                0      0.00%    100.00% # Class of committed instruction
-system.cpu1.op_class_0::total               446824897                       # Class of committed instruction
+system.cpu1.op_class_0::total               549524480                       # Class of committed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    5196                       # number of quiesce instructions executed
-system.cpu1.tickCycles                      627540865                       # Number of cycles that the object actually ticked
-system.cpu1.idleCycles                      176062744                       # Total number of cycles that the object has spent stopped
-system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.tags.replacements          4660684                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          434.489996                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs          132775101                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs          4661196                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            28.485200                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     8377585211000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   434.489996                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.848613                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.848613                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0           72                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          401                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           39                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses        281793929                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses       281793929                       # Number of data accesses
-system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.ReadReq_hits::cpu1.data     67965873                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       67965873                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data     61015488                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total      61015488                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data       190971                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total       190971                       # number of SoftPFReq hits
-system.cpu1.dcache.WriteLineReq_hits::cpu1.data        44349                       # number of WriteLineReq hits
-system.cpu1.dcache.WriteLineReq_hits::total        44349                       # number of WriteLineReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1561438                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total      1561438                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1518539                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total      1518539                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data    129025710                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total       129025710                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data    129216681                       # number of overall hits
-system.cpu1.dcache.overall_hits::total      129216681                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data      2729495                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total      2729495                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data      2149690                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      2149690                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data       616052                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total       616052                       # number of SoftPFReq misses
-system.cpu1.dcache.WriteLineReq_misses::cpu1.data       399927                       # number of WriteLineReq misses
-system.cpu1.dcache.WriteLineReq_misses::total       399927                       # number of WriteLineReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       143085                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total       143085                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data       184951                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total       184951                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data      5279112                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total       5279112                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data      5895164                       # number of overall misses
-system.cpu1.dcache.overall_misses::total      5895164                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  39717227000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total  39717227000                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  40094025500                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  40094025500                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data   9755721000                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::total   9755721000                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2101168500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total   2101168500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4571201000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total   4571201000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      4144500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      4144500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  89566973500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  89566973500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  89566973500                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  89566973500                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data     70695368                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     70695368                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data     63165178                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total     63165178                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       807023                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total       807023                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       444276                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::total       444276                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1704523                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total      1704523                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1703490                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total      1703490                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data    134304822                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total    134304822                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data    135111845                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total    135111845                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.038609                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.038609                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.034033                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.034033                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.763364                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.763364                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.900177                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::total     0.900177                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.083944                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.083944                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.108572                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.108572                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.039307                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.039307                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.043632                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.043632                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14551.126490                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14551.126490                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18651.073178                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 18651.073178                       # average WriteReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24393.754360                       # average WriteLineReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24393.754360                       # average WriteLineReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14684.757312                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14684.757312                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24715.740926                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24715.740926                       # average StoreCondReq miss latency
+system.cpu1.kern.inst.quiesce                   14504                       # number of quiesce instructions executed
+system.cpu1.tickCycles                      754340504                       # Number of cycles that the object actually ticked
+system.cpu1.idleCycles                      219429502                       # Total number of cycles that the object has spent stopped
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.tags.replacements          5584308                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          440.375822                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs          163963779                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs          5584818                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            29.358840                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     8377741807000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   440.375822                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.860109                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.860109                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0          114                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          162                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          234                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses        347150058                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses       347150058                       # Number of data accesses
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.ReadReq_hits::cpu1.data     84821089                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       84821089                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data     74565342                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total      74565342                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data       240493                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total       240493                       # number of SoftPFReq hits
+system.cpu1.dcache.WriteLineReq_hits::cpu1.data        73857                       # number of WriteLineReq hits
+system.cpu1.dcache.WriteLineReq_hits::total        73857                       # number of WriteLineReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1888770                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total      1888770                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1879546                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total      1879546                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data    159460288                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total       159460288                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data    159700781                       # number of overall hits
+system.cpu1.dcache.overall_hits::total      159700781                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data      3413550                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total      3413550                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      2348662                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      2348662                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data       664960                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total       664960                       # number of SoftPFReq misses
+system.cpu1.dcache.WriteLineReq_misses::cpu1.data       462804                       # number of WriteLineReq misses
+system.cpu1.dcache.WriteLineReq_misses::total       462804                       # number of WriteLineReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       186013                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total       186013                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data       193851                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total       193851                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data      6225016                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total       6225016                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data      6889976                       # number of overall misses
+system.cpu1.dcache.overall_misses::total      6889976                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  52244752500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total  52244752500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  43500498500                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  43500498500                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  11517052000                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::total  11517052000                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2853085500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total   2853085500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4630433000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total   4630433000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      2585500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      2585500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 107262303000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 107262303000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 107262303000                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 107262303000                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data     88234639                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total     88234639                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data     76914004                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total     76914004                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       905453                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total       905453                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       536661                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::total       536661                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      2074783                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total      2074783                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      2073397                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total      2073397                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data    165685304                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total    165685304                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data    166590757                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total    166590757                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.038687                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.038687                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.030536                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.030536                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.734395                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.734395                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.862377                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::total     0.862377                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.089654                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.089654                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.093494                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.093494                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.037571                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.037571                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.041359                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.041359                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15305.108318                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15305.108318                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18521.395799                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 18521.395799                       # average WriteReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24885.376963                       # average WriteLineReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24885.376963                       # average WriteLineReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15338.097337                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15338.097337                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23886.557201                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23886.557201                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16966.295373                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 16966.295373                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15193.296319                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 15193.296319                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17230.847760                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 17230.847760                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15567.877595                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 15567.877595                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.writebacks::writebacks      4660691                       # number of writebacks
-system.cpu1.dcache.writebacks::total          4660691                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       132278                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total       132278                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       894898                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total       894898                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data           69                       # number of WriteLineReq MSHR hits
-system.cpu1.dcache.WriteLineReq_mshr_hits::total           69                       # number of WriteLineReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        37558                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        37558                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data           59                       # number of StoreCondReq MSHR hits
-system.cpu1.dcache.StoreCondReq_mshr_hits::total           59                       # number of StoreCondReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data      1027245                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total      1027245                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data      1027245                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total      1027245                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2597217                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total      2597217                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1254792                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total      1254792                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       615702                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total       615702                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       399858                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::total       399858                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       105527                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total       105527                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       184892                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total       184892                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data      4251867                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total      4251867                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data      4867569                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total      4867569                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         8793                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total         8793                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         9091                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total         9091                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        17884                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total        17884                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  34245614000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total  34245614000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  22880344500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total  22880344500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  13431113500                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  13431113500                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data   9350661500                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total   9350661500                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1405417000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1405417000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   4384302500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   4384302500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      3898500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      3898500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  66476620000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total  66476620000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  79907733500                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total  79907733500                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   1305175500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   1305175500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1305175500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1305175500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036738                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036738                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.019865                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.019865                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.762930                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.762930                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.900022                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.900022                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.061910                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.061910                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.108537                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.108537                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.031658                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.031658                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.036026                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.036026                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13185.503560                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13185.503560                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18234.372310                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18234.372310                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21814.308708                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21814.308708                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23384.955409                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23384.955409                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13318.079733                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13318.079733                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23712.775566                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23712.775566                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks      5584335                       # number of writebacks
+system.cpu1.dcache.writebacks::total          5584335                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       169267                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total       169267                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       957224                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total       957224                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data           58                       # number of WriteLineReq MSHR hits
+system.cpu1.dcache.WriteLineReq_mshr_hits::total           58                       # number of WriteLineReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        44866                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        44866                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data           87                       # number of StoreCondReq MSHR hits
+system.cpu1.dcache.StoreCondReq_mshr_hits::total           87                       # number of StoreCondReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data      1126549                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total      1126549                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data      1126549                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total      1126549                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      3244283                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total      3244283                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1391438                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total      1391438                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       664681                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total       664681                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       462746                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::total       462746                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       141147                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total       141147                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       193764                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total       193764                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data      5098467                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total      5098467                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data      5763148                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total      5763148                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        17608                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total        17608                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        15853                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total        15853                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        33461                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total        33461                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  45298654500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total  45298654500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  25106196000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total  25106196000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  14639124500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  14639124500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  11050641000                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  11050641000                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1898988000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1898988000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   4434665000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   4434665000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      2119500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      2119500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  81455491500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total  81455491500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  96094616000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total  96094616000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2936127500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2936127500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   2936127500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   2936127500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036769                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036769                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018091                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018091                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.734087                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.734087                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.862269                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.862269                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.068030                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.068030                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.093452                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.093452                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.030772                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.030772                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.034595                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.034595                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13962.608841                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13962.608841                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18043.345086                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18043.345086                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22024.286086                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22024.286086                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23880.575953                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23880.575953                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13453.973517                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13453.973517                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22886.939782                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22886.939782                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15634.689420                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15634.689420                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16416.353523                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16416.353523                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 148433.469806                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 148433.469806                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 72980.065981                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 72980.065981                       # average overall mshr uncacheable latency
-system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.cpu1.icache.tags.replacements          8014386                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          507.062567                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs          202497896                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs          8014898                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            25.265187                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     8368004575000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   507.062567                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.990357                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.990357                       # Average percentage of cache occupancy
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15976.467338                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15976.467338                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16673.980262                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16673.980262                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 166749.630850                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 166749.630850                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 87747.751113                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 87747.751113                       # average overall mshr uncacheable latency
+system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.cpu1.icache.tags.replacements          9521452                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          507.043038                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs          244267020                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs          9521964                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            25.653008                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     8368158607000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   507.043038                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.990318                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.990318                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0          113                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          354                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2           45                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0          273                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          180                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2           59                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses        429040515                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses       429040515                       # Number of data accesses
-system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.cpu1.icache.ReadReq_hits::cpu1.inst    202497896                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total      202497896                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst    202497896                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total       202497896                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst    202497896                       # number of overall hits
-system.cpu1.icache.overall_hits::total      202497896                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst      8014908                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total      8014908                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst      8014908                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total       8014908                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst      8014908                       # number of overall misses
-system.cpu1.icache.overall_misses::total      8014908                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  81330977500                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total  81330977500                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst  81330977500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total  81330977500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst  81330977500                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total  81330977500                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst    210512804                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total    210512804                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst    210512804                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total    210512804                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst    210512804                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total    210512804                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.038073                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.038073                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.038073                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.038073                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.038073                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.038073                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10147.462391                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 10147.462391                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10147.462391                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 10147.462391                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10147.462391                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 10147.462391                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses        517099934                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses       517099934                       # Number of data accesses
+system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.cpu1.icache.ReadReq_hits::cpu1.inst    244267020                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total      244267020                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst    244267020                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total       244267020                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst    244267020                       # number of overall hits
+system.cpu1.icache.overall_hits::total      244267020                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst      9521965                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total      9521965                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst      9521965                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total       9521965                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst      9521965                       # number of overall misses
+system.cpu1.icache.overall_misses::total      9521965                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  96688620500                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total  96688620500                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst  96688620500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total  96688620500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst  96688620500                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total  96688620500                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst    253788985                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total    253788985                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst    253788985                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total    253788985                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst    253788985                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total    253788985                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.037519                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.037519                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.037519                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.037519                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.037519                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.037519                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10154.271781                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 10154.271781                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10154.271781                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 10154.271781                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10154.271781                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 10154.271781                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.writebacks::writebacks      8014386                       # number of writebacks
-system.cpu1.icache.writebacks::total          8014386                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      8014908                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total      8014908                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst      8014908                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total      8014908                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst      8014908                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total      8014908                       # number of overall MSHR misses
+system.cpu1.icache.writebacks::writebacks      9521452                       # number of writebacks
+system.cpu1.icache.writebacks::total          9521452                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      9521965                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total      9521965                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst      9521965                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total      9521965                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst      9521965                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total      9521965                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst           95                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total           95                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst           95                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total           95                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  77323524000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total  77323524000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  77323524000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total  77323524000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  77323524000                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total  77323524000                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8766500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      8766500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      8766500                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total      8766500                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.038073                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.038073                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.038073                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.038073                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.038073                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.038073                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  9647.462454                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  9647.462454                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  9647.462454                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  9647.462454                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  9647.462454                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  9647.462454                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92278.947368                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92278.947368                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92278.947368                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92278.947368                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.prefetcher.num_hwpf_issued      6532358                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified      6532555                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit          172                       # number of redundant prefetches already in prefetch queue
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  91927638500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total  91927638500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  91927638500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total  91927638500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  91927638500                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total  91927638500                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9070500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      9070500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      9070500                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total      9070500                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.037519                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.037519                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.037519                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.037519                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.037519                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.037519                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  9654.271834                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  9654.271834                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  9654.271834                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  9654.271834                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  9654.271834                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  9654.271834                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95478.947368                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95478.947368                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95478.947368                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95478.947368                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.cpu1.l2cache.prefetcher.num_hwpf_issued      7586302                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified      7586460                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit          136                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage       799581                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.tags.replacements         2133098                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       13038.197584                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs          20019506                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs         2148887                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs            9.316221                       # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle    9619713453000                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 11987.780509                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    23.994022                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    12.035388                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  1014.387665                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.731676                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.001464                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000735                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.061913                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.795788                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022          829                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           65                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14895                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::0           11                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           17                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          152                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          567                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4           82                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            8                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           55                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            1                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          105                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1161                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         5545                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         7510                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4          574                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.050598                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.003967                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.909119                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses       428778233                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses      428778233                       # Number of data accesses
-system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       473132                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       155315                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total        628447                       # number of ReadReq hits
-system.cpu1.l2cache.WritebackDirty_hits::writebacks      2939776                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackDirty_hits::total      2939776                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackClean_hits::writebacks      9733319                       # number of WritebackClean hits
-system.cpu1.l2cache.WritebackClean_hits::total      9733319                       # number of WritebackClean hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data          413                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total          413                       # number of UpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data       783674                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total       783674                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      7365861                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total      7365861                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2414791                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total      2414791                       # number of ReadSharedReq hits
-system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       165268                       # number of InvalidateReq hits
-system.cpu1.l2cache.InvalidateReq_hits::total       165268                       # number of InvalidateReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       473132                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker       155315                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst      7365861                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data      3198465                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total       11192773                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       473132                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker       155315                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst      7365861                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data      3198465                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total      11192773                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        11255                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         7950                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total        19205                       # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       218866                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total       218866                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       184883                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total       184883                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            9                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::total            9                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data       254182                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total       254182                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       649047                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total       649047                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       903423                       # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total       903423                       # number of ReadSharedReq misses
-system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       232791                       # number of InvalidateReq misses
-system.cpu1.l2cache.InvalidateReq_misses::total       232791                       # number of InvalidateReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        11255                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker         7950                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst       649047                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data      1157605                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total      1825857                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        11255                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker         7950                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst       649047                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data      1157605                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total      1825857                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    391701000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    275187000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total    666888000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   1898630500                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total   1898630500                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   1381240500                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   1381240500                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      3788499                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      3788499                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  10033557499                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total  10033557499                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  20842529000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::total  20842529000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  28170928990                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total  28170928990                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data    350412000                       # number of InvalidateReq miss cycles
-system.cpu1.l2cache.InvalidateReq_miss_latency::total    350412000                       # number of InvalidateReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    391701000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    275187000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst  20842529000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data  38204486489                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total  59713903489                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    391701000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    275187000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst  20842529000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data  38204486489                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total  59713903489                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       484387                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       163265                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total       647652                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::writebacks      2939776                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::total      2939776                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::writebacks      9733319                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::total      9733319                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       219279                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total       219279                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       184883                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total       184883                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            9                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            9                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1037856                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total      1037856                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      8014908                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total      8014908                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3318214                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total      3318214                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       398059                       # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.InvalidateReq_accesses::total       398059                       # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       484387                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       163265                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst      8014908                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data      4356070                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total     13018630                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       484387                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       163265                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst      8014908                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data      4356070                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total     13018630                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.023236                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.048694                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.029653                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.998117                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.998117                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.prefetcher.pfSpanPage       987804                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.cpu1.l2cache.tags.replacements         2406613                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       13125.467163                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs          13856134                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs         2421819                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs            5.721375                       # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
+system.cpu1.l2cache.tags.occ_blocks::writebacks 12849.276806                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    27.086630                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    14.305413                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   234.798314                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.784258                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.001653                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000873                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.014331                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.801115                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022          271                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           79                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14856                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           10                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          106                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          108                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4           47                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::0            1                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           65                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            9                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          402                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          743                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         6180                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         6756                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4          775                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.016541                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.004822                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.906738                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses       519862521                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses      519862521                       # Number of data accesses
+system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       578094                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       171981                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total        750075                       # number of ReadReq hits
+system.cpu1.l2cache.WritebackDirty_hits::writebacks      3464322                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackDirty_hits::total      3464322                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackClean_hits::writebacks     11639503                       # number of WritebackClean hits
+system.cpu1.l2cache.WritebackClean_hits::total     11639503                       # number of WritebackClean hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data       901874                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total       901874                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      8781698                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::total      8781698                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      3023137                       # number of ReadSharedReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::total      3023137                       # number of ReadSharedReq hits
+system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       191670                       # number of InvalidateReq hits
+system.cpu1.l2cache.InvalidateReq_hits::total       191670                       # number of InvalidateReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       578094                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker       171981                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst      8781698                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.data      3925011                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total       13456784                       # number of demand (read+write) hits
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       578094                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker       171981                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst      8781698                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data      3925011                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total      13456784                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        22586                       # number of ReadReq misses
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+system.cpu1.l2cache.ReadReq_misses::total        33636                       # number of ReadReq misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       232349                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total       232349                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       193761                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total       193761                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            3                       # number of SCUpgradeFailReq misses
+system.cpu1.l2cache.SCUpgradeFailReq_misses::total            3                       # number of SCUpgradeFailReq misses
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data       259533                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadExReq_misses::total       259533                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       740267                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::total       740267                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data      1026659                       # number of ReadSharedReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::total      1026659                       # number of ReadSharedReq misses
+system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       269262                       # number of InvalidateReq misses
+system.cpu1.l2cache.InvalidateReq_misses::total       269262                       # number of InvalidateReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        22586                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker        11050                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.inst       740267                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.data      1286192                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::total      2060095                       # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        22586                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker        11050                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst       740267                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data      1286192                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total      2060095                       # number of overall misses
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    726971000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    437240000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::total   1164211000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    947721000                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total    947721000                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    273329000                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    273329000                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      2036499                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      2036499                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  11444500498                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::total  11444500498                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  24621036000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::total  24621036000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  35849827996                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::total  35849827996                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data    304696500                       # number of InvalidateReq miss cycles
+system.cpu1.l2cache.InvalidateReq_miss_latency::total    304696500                       # number of InvalidateReq miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    726971000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    437240000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.inst  24621036000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.data  47294328494                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::total  73079575494                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    726971000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    437240000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst  24621036000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.data  47294328494                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total  73079575494                       # number of overall miss cycles
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       600680                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       183031                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total       783711                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::writebacks      3464322                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::total      3464322                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::writebacks     11639503                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::total     11639503                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       232349                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total       232349                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       193761                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total       193761                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            3                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            3                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1161407                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total      1161407                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      9521965                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::total      9521965                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      4049796                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::total      4049796                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       460932                       # number of InvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.InvalidateReq_accesses::total       460932                       # number of InvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       600680                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       183031                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst      9521965                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data      5211203                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total     15516879                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       600680                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       183031                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst      9521965                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data      5211203                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total     15516879                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.037601                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.060372                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.042919                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.244911                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.244911                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.080980                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.080980                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.272262                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.272262                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.584815                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.584815                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.023236                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.048694                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.080980                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.265745                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.140250                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.023236                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.048694                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.080980                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.265745                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.140250                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 34802.398934                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 34614.716981                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 34724.707108                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  8674.853563                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  8674.853563                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  7470.889698                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  7470.889698                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 420944.333333                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 420944.333333                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39473.910422                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39473.910422                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 32112.511112                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 32112.511112                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 31182.435017                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 31182.435017                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data  1505.264379                       # average InvalidateReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total  1505.264379                       # average InvalidateReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 34802.398934                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 34614.716981                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 32112.511112                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33003.042047                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 32704.589400                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 34802.398934                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 34614.716981                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 32112.511112                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33003.042047                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 32704.589400                       # average overall miss latency
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.223464                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.223464                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.077743                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.077743                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.253509                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.253509                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.584169                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.584169                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.037601                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.060372                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.077743                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.246813                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.132765                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.037601                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.060372                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.077743                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.246813                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.132765                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 32186.797131                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 39569.230769                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 34612.052563                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  4078.868426                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  4078.868426                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  1410.650234                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  1410.650234                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data       678833                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total       678833                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44096.513730                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44096.513730                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 33259.669822                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 33259.669822                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 34918.924391                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 34918.924391                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data  1131.598592                       # average InvalidateReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total  1131.598592                       # average InvalidateReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 32186.797131                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 39569.230769                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 33259.669822                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 36770.815317                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 35473.886153                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 32186.797131                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 39569.230769                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 33259.669822                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 36770.815317                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 35473.886153                       # average overall miss latency
 system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.l2cache.unused_prefetches           43626                       # number of HardPF blocks evicted w/o reference
-system.cpu1.l2cache.writebacks::writebacks      1060166                       # number of writebacks
-system.cpu1.l2cache.writebacks::total         1060166                       # number of writebacks
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker            1                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker            5                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::total            6                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         5457                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total         5457                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            3                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            3                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          376                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          376                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data            5                       # number of InvalidateReq MSHR hits
-system.cpu1.l2cache.InvalidateReq_mshr_hits::total            5                       # number of InvalidateReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker            5                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            3                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data         5833                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total         5842                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker            1                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker            5                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            3                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data         5833                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total         5842                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        11254                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         7945                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total        19199                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       690270                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total       690270                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       218866                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total       218866                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       184883                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       184883                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            9                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            9                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       248725                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total       248725                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       649044                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       649044                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       903047                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       903047                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       232786                       # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::total       232786                       # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        11254                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         7945                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       649044                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1151772                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total      1820015                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        11254                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         7945                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       649044                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1151772                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       690270                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total      2510285                       # number of overall MSHR misses
+system.cpu1.l2cache.unused_prefetches           49424                       # number of HardPF blocks evicted w/o reference
+system.cpu1.l2cache.writebacks::writebacks      1233392                       # number of writebacks
+system.cpu1.l2cache.writebacks::total         1233392                       # number of writebacks
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker           16                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker          110                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_hits::total          126                       # number of ReadReq MSHR hits
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+system.cpu1.l2cache.ReadExReq_mshr_hits::total         7522                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            2                       # number of ReadCleanReq MSHR hits
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          653                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          653                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker           16                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker          110                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            2                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.data         8175                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total         8303                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker           16                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker          110                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            2                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.data         8175                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::total         8303                       # number of overall MSHR hits
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+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker        10940                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::total        33510                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       779944                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total       779944                       # number of HardPFReq MSHR misses
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+system.cpu1.l2cache.UpgradeReq_mshr_misses::total       232349                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       193761                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       193761                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            3                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            3                       # number of SCUpgradeFailReq MSHR misses
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+system.cpu1.l2cache.ReadExReq_mshr_misses::total       252011                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       740265                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       740265                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data      1026006                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::total      1026006                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       269262                       # number of InvalidateReq MSHR misses
+system.cpu1.l2cache.InvalidateReq_mshr_misses::total       269262                       # number of InvalidateReq MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        22570                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker        10940                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       740265                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1278017                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::total      2051792                       # number of demand (read+write) MSHR misses
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+system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker        10940                       # number of overall MSHR misses
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+system.cpu1.l2cache.overall_mshr_misses::total      2831736                       # number of overall MSHR misses
 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst           95                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         8793                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         8888                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         9091                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         9091                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        17608                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        17703                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        15853                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        15853                       # number of WriteReq MSHR uncacheable
 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst           95                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        17884                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        17979                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    324079500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    227423500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    551503000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  26884842389                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  26884842389                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   4561523494                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   4561523494                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2993192497                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2993192497                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      3356499                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      3356499                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   7853418999                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   7853418999                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  16948153000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  16948153000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  22723854990                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  22723854990                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data   6164226500                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total   6164226500                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    324079500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    227423500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  16948153000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  30577273989                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total  48076929989                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    324079500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    227423500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  16948153000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  30577273989                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  26884842389                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total  74961772378                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8006500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   1234720500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   1242727000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      8006500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   1234720500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1242727000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.023233                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.048663                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.029644                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        33461                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        33556                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    591166500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    369748000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    960914500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  34084097769                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  34084097769                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   4320296500                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   4320296500                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2976407492                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2976407492                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1712499                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1712499                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   8961948498                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   8961948498                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  20179405000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  20179405000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  29636625496                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  29636625496                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data   7368901000                       # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total   7368901000                       # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    591166500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    369748000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  20179405000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  38598573994                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total  59738893494                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    591166500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    369748000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  20179405000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  38598573994                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  34084097769                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total  93822991263                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8310500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2795199500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2803510000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      8310500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   2795199500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   2803510000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.037574                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.059771                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.042758                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.998117                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.998117                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.239653                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.239653                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.080980                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.080980                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.272149                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.272149                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.584803                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.584803                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.023233                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.048663                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.080980                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.264406                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.139801                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.023233                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.048663                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.080980                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.264406                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.216988                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.216988                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.077743                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.077743                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.253348                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.253348                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.584169                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.584169                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.037574                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.059771                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.077743                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.245244                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.132230                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.037574                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.059771                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.077743                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.245244                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.192823                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 28796.827795                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 28624.732536                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 28725.610709                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38948.299055                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 38948.299055                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20841.626813                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20841.626813                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16189.657767                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16189.657767                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 372944.333333                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 372944.333333                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31574.707002                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31574.707002                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 26112.486981                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 26112.486981                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 25163.535220                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 25163.535220                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26480.228622                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26480.228622                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 28796.827795                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 28624.732536                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26112.486981                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26548.026857                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26415.677887                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 28796.827795                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 28624.732536                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26112.486981                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26548.026857                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38948.299055                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29861.857270                       # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 84278.947368                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 140420.846128                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 139820.769577                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 84278.947368                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 69040.511071                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 69121.030091                       # average overall mshr uncacheable latency
-system.cpu1.toL2Bus.snoop_filter.tot_requests     26150144                       # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests     13381244                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         1981                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops      1969364                       # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops      1969026                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops          338                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.cpu1.toL2Bus.trans_dist::ReadReq        732517                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp     12156991                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq         9091                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp         9091                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty      4007359                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean      9735300                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict      2694691                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq       886167                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFResp            3                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq       430328                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       337223                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp       468486                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           75                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          138                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq      1067899                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp      1044213                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq      8014908                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4433895                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq       458319                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateResp       398059                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     24044391                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     15175224                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       343569                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1027712                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total         40590896                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side   1025880832                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    583383788                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1306120                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      3875096                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total        1614445836                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                    6456023                       # Total snoops (count)
-system.cpu1.toL2Bus.snoopTraffic             75189768                       # Total snoop traffic (bytes)
-system.cpu1.toL2Bus.snoop_fanout::samples     20132697                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       0.112928                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.316558                       # Request fanout histogram
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.182494                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 26192.578644                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 33797.806216                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 28675.455088                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43700.698728                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43700.698728                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18593.996531                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18593.996531                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15361.231063                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15361.231063                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       570833                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       570833                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 35561.735393                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 35561.735393                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 27259.704295                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27259.704295                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28885.430978                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28885.430978                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 27367.029139                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 27367.029139                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 26192.578644                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 33797.806216                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27259.704295                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 30201.925322                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29115.472472                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 26192.578644                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 33797.806216                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27259.704295                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 30201.925322                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43700.698728                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33132.675950                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87478.947368                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158745.996138                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158363.554200                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87478.947368                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 83536.041959                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 83547.204673                       # average overall mshr uncacheable latency
+system.cpu1.toL2Bus.snoop_filter.tot_requests     31064178                       # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests     15870221                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         1958                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops       609547                       # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       609525                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops           22                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.cpu1.toL2Bus.trans_dist::ReadReq        891069                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp     14544906                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq        15853                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp        15853                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty      4703319                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean     11641461                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict      1517999                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq       982833                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq       435735                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       338791                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp       485404                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           64                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          115                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq      1187635                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp      1166992                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq      9521965                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq      5021918                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq       508584                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateResp       460932                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     28565571                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     17994817                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       387517                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1269560                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total         48217465                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side   1218784704                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    696648341                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1464248                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4805440                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total        1921702733                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                    5371031                       # Total snoops (count)
+system.cpu1.toL2Bus.snoopTraffic             85625912                       # Total snoop traffic (bytes)
+system.cpu1.toL2Bus.snoop_fanout::samples     21661443                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       0.043843                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.204751                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0          17859482     88.71%     88.71% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1           2272877     11.29%    100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2               338      0.00%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0          20711756     95.62%     95.62% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1            949665      4.38%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2                22      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total      20132697                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy   25974578977                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total      21661443                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy   30930175985                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy    179053447                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy    161428122                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy  12025219550                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy  14285968218                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy   6952751265                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy   8290126100                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy    180351405                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy    204584802                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy    543399850                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy    668995768                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq                40387                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40387                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136979                       # Transaction distribution
-system.iobus.trans_dist::WriteResp             136979                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47808                       # Packet count per connected master and slave (bytes)
+system.iobus.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.iobus.trans_dist::ReadReq                40347                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40347                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136610                       # Transaction distribution
+system.iobus.trans_dist::WriteResp             136610                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47638                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
@@ -2452,15 +2432,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29808                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       122950                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231702                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231702                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       122572                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231262                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231262                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  354732                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47828                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353914                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47658                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -2471,105 +2451,105 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17703                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       155965                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7355160                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7355160                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       155679                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7339064                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7339064                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7513211                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             42458502                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7496829                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             41998503                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               311001                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               312000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                 9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                 9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy                 9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy                9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy               10500                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy               10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer15.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               15000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               15500                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy                9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            26063002                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            25719009                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            34444001                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            34474500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           570734934                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           569697884                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            92958000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            92693000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           148142000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147958000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements               115832                       # number of replacements
-system.iocache.tags.tagsinuse               11.305903                       # Cycle average of tags in use
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.replacements               115612                       # number of replacements
+system.iocache.tags.tagsinuse               11.289058                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115848                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115628                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         9127528857000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.833923                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     7.471980                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.239620                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.466999                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.706619                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         9127814531000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.847615                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     7.441443                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.240476                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.465090                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.705566                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1043016                       # Number of tag accesses
-system.iocache.tags.data_accesses             1043016                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.tag_accesses              1041036                       # Number of tag accesses
+system.iocache.tags.data_accesses             1041036                       # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8867                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8904                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8903                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8940                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
-system.iocache.WriteLineReq_misses::realview.ide       106984                       # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total       106984                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide       115851                       # number of demand (read+write) misses
-system.iocache.demand_misses::total            115891                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide       115631                       # number of demand (read+write) misses
+system.iocache.demand_misses::total            115671                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide       115851                       # number of overall misses
-system.iocache.overall_misses::total           115891                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5198000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1647274031                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1652472031                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide       115631                       # number of overall misses
+system.iocache.overall_misses::total           115671                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5198500                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1683130463                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1688328963                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  12886794903                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  12886794903                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5567000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide  14534068934                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  14539635934                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5567000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide  14534068934                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  14539635934                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  12860878921                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  12860878921                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5567500                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide  14544009384                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  14549576884                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5567500                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide  14544009384                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total  14549576884                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8867                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8904                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8903                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8940                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::realview.ide       106984                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total       106984                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide       115851                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total          115891                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide       115631                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total          115671                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide       115851                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total         115891                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide       115631                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total         115671                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -2583,53 +2563,53 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 185775.801398                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 185587.604560                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet       140500                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 189052.056947                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 188851.114430                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120455.347557                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 120455.347557                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       139175                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 125454.842289                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 125459.577827                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       139175                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 125454.842289                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 125459.577827                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         32243                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120501.451550                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 120501.451550                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet 139187.500000                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 125779.500169                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 125784.136767                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet 139187.500000                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 125779.500169                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 125784.136767                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         33720                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3515                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3566                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.172973                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.455973                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks          106950                       # number of writebacks
-system.iocache.writebacks::total               106950                       # number of writebacks
+system.iocache.writebacks::writebacks          106694                       # number of writebacks
+system.iocache.writebacks::total               106694                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8867                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8904                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8903                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8940                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::realview.ide       106984                       # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total       106984                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide       115851                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total       115891                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide       115631                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total       115671                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide       115851                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total       115891                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3348000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1203924031                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1207272031                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide       115631                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total       115671                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3348500                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1237980463                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1241328963                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7528956843                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   7528956843                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3567000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   8732880874                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   8736447874                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3567000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   8732880874                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   8736447874                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7515783412                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   7515783412                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3567500                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   8753763875                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   8757331375                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3567500                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   8753763875                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   8757331375                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -2643,660 +2623,661 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135775.801398                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 135587.604560                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet        90500                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139052.056947                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 138851.114430                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70374.605950                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70374.605950                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        89175                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 75380.280481                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 75385.041755                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        89175                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 75380.280481                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 75385.041755                       # average overall mshr miss latency
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements                  1436798                       # number of replacements
-system.l2c.tags.tagsinuse                63641.257392                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    6808742                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1497176                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     4.547723                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle               8050623000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   20256.980304                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   307.265586                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   477.600666                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     6075.269789                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data    12531.509900                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 19419.437449                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker    11.305032                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker     4.128844                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     2389.320183                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     1436.582929                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher   731.856711                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.309097                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.004689                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.007288                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.092701                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.191216                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.296317                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000173                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.000063                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.036458                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.021921                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.011167                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.971089                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        10768                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023          197                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        49413                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::1            9                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2          162                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3         3598                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4         6999                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3           18                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          179                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          298                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2209                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3        15374                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        31482                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.164307                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.003006                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.753983                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 82887108                       # Number of tag accesses
-system.l2c.tags.data_accesses                82887108                       # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.l2c.WritebackDirty_hits::writebacks      2851442                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total         2851442                       # number of WritebackDirty hits
-system.l2c.UpgradeReq_hits::cpu0.data          184675                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data          129782                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total              314457                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data         47164                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data         36238                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total             83402                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            58975                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            57393                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               116368                       # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         7045                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker         4376                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst       746247                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       677498                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       343450                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         6710                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4818                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst       604538                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       564393                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       306025                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total          3265100                       # number of ReadSharedReq hits
-system.l2c.InvalidateReq_hits::cpu0.data       138219                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::cpu1.data       125546                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::total           263765                       # number of InvalidateReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          7045                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          4376                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              746247                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              736473                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher       343450                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          6710                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          4818                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              604538                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              621786                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher       306025                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 3381468                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         7045                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         4376                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             746247                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             736473                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher       343450                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         6710                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         4818                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             604538                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             621786                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher       306025                       # number of overall hits
-system.l2c.overall_hits::total                3381468                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data         65595                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         60730                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total            126325                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data        12636                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data        10558                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total           23194                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          86809                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          47256                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             134065                       # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         2557                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.itb.walker         2464                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.inst        78739                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       176748                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       289930                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         1566                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.itb.walker         1157                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.inst        44505                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data        80821                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       170404                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         848891                       # number of ReadSharedReq misses
-system.l2c.InvalidateReq_misses::cpu0.data       477170                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::cpu1.data        94656                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::total         571826                       # number of InvalidateReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         2557                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         2464                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             78739                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            263557                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher       289930                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker         1566                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker         1157                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             44505                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            128077                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher       170404                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                982956                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         2557                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         2464                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            78739                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           263557                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       289930                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker         1566                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker         1157                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            44505                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           128077                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher       170404                       # number of overall misses
-system.l2c.overall_misses::total               982956                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data    456935000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data    428124500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total    885059500                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data     88094500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data     70625000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total    158719500                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   7719270500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   3911139500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  11630410000                       # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    226838000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    219007500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.inst   6705086500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data  15776824000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  36609242451                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    145187000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    107589500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.inst   3760779000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data   7519043500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  21421936717                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total  92491534168                       # number of ReadSharedReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu0.data     63068500                       # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu1.data     48974000                       # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::total    112042500                       # number of InvalidateReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker    226838000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker    219007500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   6705086500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  23496094500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  36609242451                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker    145187000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker    107589500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst   3760779000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data  11430183000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  21421936717                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total    104121944168                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker    226838000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker    219007500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   6705086500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  23496094500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  36609242451                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker    145187000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker    107589500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst   3760779000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data  11430183000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  21421936717                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total   104121944168                       # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks      2851442                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total      2851442                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data       250270                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data       190512                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total          440782                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data        59800                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data        46796                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total        106596                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       145784                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       104649                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           250433                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker         9602                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         6840                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.inst       824986                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data       854246                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       633380                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         8276                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         5975                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.inst       649043                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data       645214                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       476429                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      4113991                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu0.data       615389                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu1.data       220202                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::total       835591                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker         9602                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         6840                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          824986                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1000030                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher       633380                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         8276                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         5975                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          649043                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          749863                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher       476429                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             4364424                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker         9602                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         6840                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         824986                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1000030                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       633380                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         8276                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         5975                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         649043                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         749863                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher       476429                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            4364424                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.262097                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.318773                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.286593                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.211304                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.225618                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.217588                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.595463                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.451567                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.535333                       # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.266299                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.360234                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.095443                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.206905                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.457750                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.189222                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.193640                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.068570                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.125262                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.357669                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.206342                       # miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu0.data     0.775396                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu1.data     0.429860                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::total     0.684337                       # miss rate for InvalidateReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.266299                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.360234                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.095443                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.263549                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.457750                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.189222                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.193640                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.068570                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.170801                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.357669                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.225220                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.266299                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.360234                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.095443                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.263549                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.457750                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.189222                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.193640                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.068570                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.170801                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.357669                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.225220                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  6966.003506                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  7049.637741                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  7006.210172                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  6971.707819                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  6689.240386                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  6843.127533                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 88922.467716                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82764.929321                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 86752.023272                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 88712.553774                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 88882.913961                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 85155.850341                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 89261.683301                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 126269.245856                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 92712.005109                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 92990.060501                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 84502.392990                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 93033.289615                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 125712.640061                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 108955.724784                       # average ReadSharedReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu0.data   132.171972                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu1.data   517.389283                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::total   195.938100                       # average InvalidateReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 88712.553774                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 88882.913961                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 85155.850341                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 89149.954279                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 126269.245856                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 92712.005109                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 92990.060501                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 84502.392990                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 89244.618472                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 125712.640061                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 105927.370267                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 88712.553774                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 88882.913961                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 85155.850341                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 89149.954279                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 126269.245856                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 92712.005109                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 92990.060501                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 84502.392990                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 89244.618472                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 125712.640061                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 105927.370267                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs               198                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70419.978000                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70419.978000                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89187.500000                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 75704.299669                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 75708.962272                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89187.500000                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 75704.299669                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 75708.962272                       # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.l2c.tags.replacements                  1555997                       # number of replacements
+system.l2c.tags.tagsinuse                65230.630092                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    7273929                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1617589                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     4.496772                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle               7807986500                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks    8906.310468                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker    15.466536                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     9.611192                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3875.011018                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     9658.633081                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher  3787.473530                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   432.466953                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   495.764320                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     3981.420883                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data    15318.580710                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 18749.891401                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.135900                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000236                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.000147                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.059128                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.147379                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.057792                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.006599                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.007565                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.060752                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.233743                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.286101                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.995340                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022        10605                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023          254                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        50733                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::1            4                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2           57                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3          363                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4        10181                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::2            7                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          246                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           22                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          110                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         1499                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         4720                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        44382                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.161819                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.003876                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.774124                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 80901066                       # Number of tag accesses
+system.l2c.tags.data_accesses                80901066                       # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.l2c.WritebackDirty_hits::writebacks      2828973                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total         2828973                       # number of WritebackDirty hits
+system.l2c.UpgradeReq_hits::cpu0.data          204859                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data          171268                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total              376127                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data         49678                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data         57164                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total            106842                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            57243                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            53868                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               111111                       # number of ReadExReq hits
+system.l2c.ReadSharedReq_hits::cpu0.dtb.walker        12667                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.itb.walker         5625                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.inst       610867                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data       589040                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       292600                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.dtb.walker        12537                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4791                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.inst       678625                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data       607071                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       308630                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total          3122453                       # number of ReadSharedReq hits
+system.l2c.InvalidateReq_hits::cpu0.data       131047                       # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::cpu1.data       131317                       # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::total           262364                       # number of InvalidateReq hits
+system.l2c.demand_hits::cpu0.dtb.walker         12667                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          5625                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              610867                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              646283                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.l2cache.prefetcher       292600                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker         12537                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          4791                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              678625                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              660939                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.l2cache.prefetcher       308630                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 3233564                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker        12667                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         5625                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             610867                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             646283                       # number of overall hits
+system.l2c.overall_hits::cpu0.l2cache.prefetcher       292600                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker        12537                       # number of overall hits
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+system.l2c.overall_hits::total                3233564                       # number of overall hits
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+system.l2c.UpgradeReq_misses::cpu1.data         26656                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             47716                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data          518                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data          636                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total            1154                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          76722                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          60050                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             136772                       # number of ReadExReq misses
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+system.l2c.ReadSharedReq_misses::total         900362                       # number of ReadSharedReq misses
+system.l2c.InvalidateReq_misses::cpu0.data       438466                       # number of InvalidateReq misses
+system.l2c.InvalidateReq_misses::cpu1.data       125863                       # number of InvalidateReq misses
+system.l2c.InvalidateReq_misses::total         564329                       # number of InvalidateReq misses
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+system.l2c.overall_misses::total              1037134                       # number of overall misses
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+system.l2c.UpgradeReq_miss_latency::cpu1.data    162277500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total    328021000                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data      8669000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data      8803000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total     17472000                       # number of SCUpgradeReq miss cycles
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+system.l2c.InvalidateReq_miss_latency::cpu0.data     31523000                       # number of InvalidateReq miss cycles
+system.l2c.InvalidateReq_miss_latency::cpu1.data     29313000                       # number of InvalidateReq miss cycles
+system.l2c.InvalidateReq_miss_latency::total     60836000                       # number of InvalidateReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker    169372000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.itb.walker    128340500                       # number of demand (read+write) miss cycles
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+system.l2c.demand_miss_latency::total    111534173216                       # number of demand (read+write) miss cycles
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+system.l2c.overall_miss_latency::total   111534173216                       # number of overall miss cycles
+system.l2c.WritebackDirty_accesses::writebacks      2828973                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total      2828973                       # number of WritebackDirty accesses(hits+misses)
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+system.l2c.UpgradeReq_accesses::cpu1.data       197924                       # number of UpgradeReq accesses(hits+misses)
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+system.l2c.SCUpgradeReq_accesses::cpu1.data        57800                       # number of SCUpgradeReq accesses(hits+misses)
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+system.l2c.ReadSharedReq_accesses::total      4022815                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu0.data       569513                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu1.data       257180                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::total       826693                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker        14501                       # number of demand (read+write) accesses
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+system.l2c.demand_accesses::total             4270698                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker        14501                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::total            4270698                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.093219                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.134678                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.112579                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.010320                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.011003                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.010686                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.572702                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.527134                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.551760                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.126474                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.200994                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.105642                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.184592                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.460976                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.171217                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.339172                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.083267                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.192575                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.426901                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.223814                       # miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu0.data     0.769896                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu1.data     0.489397                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::total     0.682634                       # miss rate for InvalidateReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.126474                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.200994                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.105642                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.245307                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.460976                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.171217                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.339172                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.083267                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.236596                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.426901                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.242849                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.126474                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.200994                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.105642                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.245307                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.460976                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.171217                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.339172                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.083267                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.236596                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.426901                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.242849                       # miss rate for overall accesses
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+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  6087.841387                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  6874.444631                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 16735.521236                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 13841.194969                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total 15140.381282                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 91313.417273                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 87267.876736                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 89537.215205                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 92351.145038                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker        90700                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 85481.345973                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 92255.810029                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 132294.480600                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 89261.003861                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 87929.849532                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 86246.090201                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90060.794944                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 124456.443527                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 110275.632710                       # average ReadSharedReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu0.data    71.893830                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu1.data   232.896085                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::total   107.802364                       # average InvalidateReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 92351.145038                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker        90700                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 85481.345973                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 91911.626656                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 132294.480600                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89261.003861                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 87929.849532                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 86246.090201                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 89242.035237                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 124456.443527                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 107540.754826                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 92351.145038                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker        90700                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 85481.345973                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 91911.626656                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 132294.480600                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::total 107540.754826                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs               751                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        3                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                       17                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs            66                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs     44.176471                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.writebacks::writebacks             1121516                       # number of writebacks
-system.l2c.writebacks::total                  1121516                       # number of writebacks
-system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          148                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu0.data           11                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          139                       # number of ReadSharedReq MSHR hits
+system.l2c.writebacks::writebacks             1165859                       # number of writebacks
+system.l2c.writebacks::total                  1165859                       # number of writebacks
+system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          169                       # number of ReadSharedReq MSHR hits
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 system.l2c.ReadSharedReq_mshr_hits::cpu1.data           17                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total          315                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst            148                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data             11                       # number of demand (read+write) MSHR hits
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 system.l2c.demand_mshr_hits::cpu1.data             17                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                315                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst           148                       # number of overall MSHR hits
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 system.l2c.overall_mshr_hits::cpu1.data            17                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total               315                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks        53239                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total        53239                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data        65595                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data        60730                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total       126325                       # number of UpgradeReq MSHR misses
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-system.l2c.InvalidateReq_mshr_misses::cpu1.data        94656                       # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::total       571826                       # number of InvalidateReq MSHR misses
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 system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        52300                       # number of overall MSHR uncacheable misses
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+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   4639903563                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total  10878391146                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker    151031002                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker    114190001                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   5436084068                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  10966992245                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  30601839845                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    205285501                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    191629001                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   4693018541                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  11590786168                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  26313170250                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total  90264026622                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data   9157417500                       # number of InvalidateReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   2543921000                       # number of InvalidateReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::total  11701338500                       # number of InvalidateReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    151031002                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    114190001                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst   5436084068                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  17205479828                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  30601839845                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    205285501                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    191629001                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst   4693018541                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data  16230689731                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  26313170250                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 101142417768                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    151031002                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    114190001                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   5436084068                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  17205479828                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  30601839845                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    205285501                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    191629001                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst   4693018541                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data  16230689731                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  26313170250                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 101142417768                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   3320084000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   4900695009                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      6011000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   1076346004                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   9303136013                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   3477966008                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      6312000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2478199000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   9282561008                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   3320084000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   4900695009                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      6011000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1076346004                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   9303136013                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3477966008                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      6312000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   2478199000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   9282561008                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.262097                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.318773                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.286593                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.211304                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.225618                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.217588                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.595463                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.451567                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.535333                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.266299                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.360234                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.095263                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.206892                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.457750                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.189222                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.193640                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.068356                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.125236                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.357669                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.206266                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.775396                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.429860                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::total     0.684337                       # mshr miss rate for InvalidateReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.266299                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.360234                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.095263                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.263538                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.457750                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.189222                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.193640                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.068356                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.170778                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.357669                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.225148                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.266299                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.360234                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.095263                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.263538                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.457750                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.189222                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.193640                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.068356                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.170778                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.357669                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.225148                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21504.428630                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21588.308809                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21544.753533                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24597.736546                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24607.311801                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24602.095240                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 78922.059614                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72763.810098                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 76751.364510                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 78712.358623                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 78882.508929                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75186.249850                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 79262.094163                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116268.528234                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 82711.049170                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 82989.197926                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 74551.369900                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 83037.216747                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115710.968135                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 98969.705542                       # average ReadSharedReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20911.097724                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20861.825980                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20902.941631                       # average InvalidateReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78712.358623                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78882.508929                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75186.249850                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79150.090720                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116268.528234                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 82711.049170                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 82989.197926                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74551.369900                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 79246.180478                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115710.968135                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 95938.382922                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78712.358623                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78882.508929                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75186.249850                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79150.090720                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116268.528234                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 82711.049170                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 82989.197926                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74551.369900                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 79246.180478                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115710.968135                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 95938.382922                       # average overall mshr miss latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.093219                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.134678                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.112579                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.010320                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.011003                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.010686                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.572702                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.527134                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.551760                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.126474                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.200994                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.105395                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.184563                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.460976                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.171217                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.339172                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.083119                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.192553                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.426901                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.223735                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.769896                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.489397                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::total     0.682634                       # mshr miss rate for InvalidateReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.126474                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.200994                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.105395                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.245282                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.460976                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.171217                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.339172                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.083119                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.236577                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.426901                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.242775                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.126474                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.200994                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.105395                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.245282                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.460976                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.171217                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.339172                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.083119                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.236577                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.426901                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.242775                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20324.905081                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20303.646459                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20313.029194                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 23768.339768                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23863.207547                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 23820.623917                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 81312.890475                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 77267.336603                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 79536.682552                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 82350.600872                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80699.647350                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75514.802228                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 82256.965971                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 122293.381948                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79260.811197                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 77929.646604                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76272.038697                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80061.794451                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114455.846723                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 100288.348496                       # average ReadSharedReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20885.125643                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20211.825556                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20734.958685                       # average InvalidateReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 82350.600872                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80699.647350                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75514.802228                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 81912.133550                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 122293.381948                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79260.811197                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 77929.646604                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76272.038697                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 79242.515396                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114455.846723                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 97550.886770                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 82350.600872                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80699.647350                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75514.802228                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 81912.133550                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 122293.381948                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79260.811197                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 77929.646604                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76272.038697                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 79242.515396                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114455.846723                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 97550.886770                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63481.529637                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164491.491592                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63273.684211                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122437.265840                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 102255.861386                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 168555.103615                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 66442.105263                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 140758.775417                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 102416.958217                       # average ReadReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63481.529637                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82791.799858                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63273.684211                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 60191.589531                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 71855.534201                       # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests       3914348                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests      2362357                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests         2871                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 81054.464285                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 66442.105263                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 74066.738396                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 72090.282208                       # average overall mshr uncacheable latency
+system.membus.snoop_filter.tot_requests       3909047                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests      2292243                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests         2625                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq               90979                       # Transaction distribution
-system.membus.trans_dist::ReadResp             948459                       # Transaction distribution
-system.membus.trans_dist::WriteReq              38491                       # Transaction distribution
-system.membus.trans_dist::WriteResp             38491                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1228466                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           265252                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           443986                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq         298688                       # Transaction distribution
+system.membus.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadReq               90635                       # Transaction distribution
+system.membus.trans_dist::ReadResp             999620                       # Transaction distribution
+system.membus.trans_dist::WriteReq              38128                       # Transaction distribution
+system.membus.trans_dist::WriteResp             38128                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1272553                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           289712                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           348270                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq         267748                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp              23                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq            2                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            145286                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           128554                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        857480                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        675140                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122950                       # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::SCUpgradeFailReq            3                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            152656                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           136047                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        908985                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        669058                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122572                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           54                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        25980                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4768940                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4917924                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       238548                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       238548                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5156472                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155965                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        24944                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4823028                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4970598                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       238389                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       238389                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5208987                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155679                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1388                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        51960                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    137639872                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    137849185                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7281600                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7281600                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               145130785                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           603530                       # Total snoops (count)
-system.membus.snoopTraffic                     179328                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples           2550056                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.011955                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.108685                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        49888                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    144251456                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    144458411                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7283200                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7283200                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               151741611                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           583612                       # Total snoops (count)
+system.membus.snoopTraffic                     163584                       # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples           2475487                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.012229                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.109905                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 2519569     98.80%     98.80% # Request fanout histogram
-system.membus.snoop_fanout::1                   30487      1.20%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 2445215     98.78%     98.78% # Request fanout histogram
+system.membus.snoop_fanout::1                   30272      1.22%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2550056                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           103375494                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             2475487                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           102607988                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               34812                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            21768496                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            20962995                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          8632891321                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          8793410200                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         5537724663                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         5849158337                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           45395946                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           45598905                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
 system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
 system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
 system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
 system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
 system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
@@ -3339,78 +3320,78 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
 system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests     12809826                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      6934559                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests      2124865                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops         137043                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops       124917                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops        12126                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47445489241000                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadReq              90981                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           4987806                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             38491                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            38491                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty      3972958                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         3104635                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          749262                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq        382090                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp        1131352                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq          138                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp          138                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           306540                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          306540                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      4897318                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq       863164                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp       835591                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     11082342                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7735233                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              18817575                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    276628165                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    188875292                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              465503457                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         2889580                       # Total snoops (count)
-system.toL2Bus.snoopTraffic                 125478224                       # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples          8764836                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.360858                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.483121                       # Request fanout histogram
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.snoop_filter.tot_requests     12529275                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      6783970                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests      2045593                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops         207524                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops       190768                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops        16756                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47276772827000                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.trans_dist::ReadReq              90637                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           4878287                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             38128                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            38128                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty      3994832                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         3079472                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          721673                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq        374590                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp        1096263                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq          115                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp          115                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           301835                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          301835                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      4787847                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq       854297                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp       826693                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      9608901                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      8808719                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              18417620                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    240252134                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    217815813                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              458067947                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         2968837                       # Total snoops (count)
+system.toL2Bus.snoopTraffic                 127024720                       # Total snoop traffic (bytes)
+system.toL2Bus.snoop_fanout::samples          8725155                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.358566                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.483567                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                5614105     64.05%     64.05% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                3138605     35.81%     99.86% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                  12126      0.14%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                5613365     64.34%     64.34% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                3095034     35.47%     99.81% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                  16756      0.19%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            8764836                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         9763497454                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            8725155                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         9593262018                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          2559907                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          2632911                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        5082599079                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        4411209152                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        3859782501                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        4336941336                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
index d21e89078..c77078f22 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
@@ -1,140 +1,140 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.660717                       # Number of seconds simulated
-sim_ticks                                51660717372000                       # Number of ticks simulated
-final_tick                               51660717372000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.687765                       # Number of seconds simulated
+sim_ticks                                51687764518000                       # Number of ticks simulated
+final_tick                               51687764518000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 187164                       # Simulator instruction rate (inst/s)
-host_op_rate                                   219920                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            10422609624                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 677216                       # Number of bytes of host memory used
-host_seconds                                  4956.60                       # Real time elapsed on the host
-sim_insts                                   927696922                       # Number of instructions simulated
-sim_ops                                    1090057089                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 151884                       # Simulator instruction rate (inst/s)
+host_op_rate                                   178474                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             8204277049                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 687220                       # Number of bytes of host memory used
+host_seconds                                  6300.10                       # Real time elapsed on the host
+sim_insts                                   956884636                       # Number of instructions simulated
+sim_ops                                    1124405089                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.dtb.walker       368128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker       311744                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst          10118784                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          60722568                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        418176                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             71939400                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst     10118784                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total        10118784                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     88730048                       # Number of bytes written to this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.dtb.walker       423488                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker       359680                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst          10197440                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          68348040                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        416768                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             79745416                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst     10197440                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total        10197440                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     96812416                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          88750628                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker         5752                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker         4871                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             158106                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             948803                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6534                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1124066                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1386407                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          96832996                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker         6617                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker         5620                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             159335                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1067951                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6512                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1246035                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1512694                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1388980                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker           7126                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker           6034                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               195870                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1175411                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8095                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1392536                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          195870                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             195870                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1717554                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1515267                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           8193                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker           6959                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               197289                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1322325                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8063                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1542830                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          197289                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             197289                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1873024                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                 398                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1717952                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1717554                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          7126                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker          6034                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              195870                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1175809                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8095                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3110488                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1124066                       # Number of read requests accepted
-system.physmem.writeReqs                      1388980                       # Number of write requests accepted
-system.physmem.readBursts                     1124066                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1388980                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 71890560                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     49664                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  88748928                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  71939400                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               88750628                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      776                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2249                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bw_write::total                1873422                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1873024                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          8193                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker          6959                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              197289                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1322723                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8063                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3416252                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1246035                       # Number of read requests accepted
+system.physmem.writeReqs                      1515267                       # Number of write requests accepted
+system.physmem.readBursts                     1246035                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1515267                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 79703040                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     43200                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  96830656                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  79745416                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               96832996                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      675                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2258                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               65344                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               73127                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               68334                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               62589                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               65747                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               73971                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               66723                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               65172                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               63356                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              122297                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              70526                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              71466                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              64199                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              65172                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              60121                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              65146                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               84316                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               87030                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               86821                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               84154                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               87756                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               92254                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               85357                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               85828                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               86266                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               90537                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              89139                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              90914                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              83868                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              84845                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              82305                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              85312                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               74796                       # Per bank write bursts
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+system.physmem.perBankWrBursts::6               95600                       # Per bank write bursts
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+system.physmem.perBankWrBursts::9               99710                       # Per bank write bursts
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+system.physmem.perBankWrBursts::15              93203                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          29                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51660715485000                       # Total gap between requests
+system.physmem.numWrRetry                          30                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51687762664000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
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-system.physmem.readPktSize::6                 1124051                       # Read request sizes (log2)
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 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
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 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1386407                       # Write request sizes (log2)
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 system.physmem.rdQLenPdf::14                      123                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::18                       79                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       60                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        4                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
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 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
@@ -160,164 +160,173 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
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-system.physmem.bytesPerActivate::mean      251.530251                       # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::stdev     286.508507                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         275744     43.18%     43.18% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::256-383        60231      9.43%     78.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        32872      5.15%     83.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        22951      3.59%     87.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        16028      2.51%     89.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        11191      1.75%     91.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         9395      1.47%     92.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        45952      7.20%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         638647                       # Bytes accessed per row activation
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-system.physmem.rdPerTurnAround::mean        14.781369                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      142.935713                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          75988    100.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            1      0.00%    100.00% # Reads before turning the bus around for writes
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 system.physmem.rdPerTurnAround::25600-26623            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::28672-29695            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           75991                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         75991                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        18.248240                       # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::stdev        7.085121                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           64109     84.36%     84.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23            9386     12.35%     96.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             485      0.64%     97.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             369      0.49%     97.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              63      0.08%     97.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             114      0.15%     98.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             258      0.34%     98.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              31      0.04%     98.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             303      0.40%     98.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              66      0.09%     98.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              30      0.04%     98.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              60      0.08%     99.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             313      0.41%     99.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              41      0.05%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              27      0.04%     99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79             117      0.15%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83             162      0.21%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               3      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.00%     99.93% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::108-111             2      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            21      0.03%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             2      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             3      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147            12      0.02%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             3      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             4      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::212-215             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           75991                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    16312474093                       # Total ticks spent queuing
-system.physmem.totMemAccLat               37374161593                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   5616450000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       14522.05                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total           80666                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         80666                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        18.756093                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.057108                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        7.363487                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           67894     84.17%     84.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23            3915      4.85%     89.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27            3350      4.15%     93.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31            2485      3.08%     96.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35            1103      1.37%     97.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             521      0.65%     98.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             244      0.30%     98.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47             153      0.19%     98.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              79      0.10%     98.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              83      0.10%     98.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              83      0.10%     99.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              89      0.11%     99.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             450      0.56%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              43      0.05%     99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              41      0.05%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              30      0.04%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              23      0.03%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               5      0.01%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               1      0.00%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               4      0.00%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               3      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             6      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             2      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             9      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             1      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            18      0.02%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             7      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             4      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             5      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-211             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           80666                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    17151209707                       # Total ticks spent queuing
+system.physmem.totMemAccLat               40501709707                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   6226800000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       13772.09                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  33272.05                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.39                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.72                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.39                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.72                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  32522.09                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.54                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.87                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.54                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.87                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        26.67                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     859362                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                   1011981                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   76.50                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  72.98                       # Row buffer hit rate for writes
-system.physmem.avgGap                     20557011.49                       # Average gap between requests
-system.physmem.pageHitRate                      74.55                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 2420719560                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 1320829125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                4219854600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               4493983680                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3374226435840                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1315006290315                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29842911750000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34544599863120                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.682250                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49645601262378                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1725064640000                       # Time in different power states
+system.physmem.avgWrQLen                        25.30                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     964137                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                   1107294                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   77.42                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.18                       # Row buffer hit rate for writes
+system.physmem.avgGap                     18718619.94                       # Average gap between requests
+system.physmem.pageHitRate                      75.10                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 2629783800                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1434901875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                4687519200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               4930197840                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3375993173280                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1305935149860                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29867098550250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34562709276105                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.682675                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49685845654409                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1725967880000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    290044177622                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    275945978091                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 2407451760                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 1313589750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                4541752800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               4491845280                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3374226435840                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1315022855940                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29842897218750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34544901150120                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.688082                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49645554021211                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1725064640000                       # Time in different power states
+system.physmem_1.actEnergy                 2563233120                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1398589500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                5026242000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               4873906080                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3375993173280                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1305717731910                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29867289276000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34562862151890                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.685632                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49686132095770                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1725967880000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    290092863289                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    275664064230                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
 system.realview.nvmem.bytes_read::cpu.inst          704                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           740                       # Number of bytes read from this memory
@@ -334,30 +343,30 @@ system.realview.nvmem.bw_inst_read::total           14                       # I
 system.realview.nvmem.bw_total::cpu.inst           14                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total              14                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups               256052360                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         178125867                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          12215850                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            188334497                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               126943208                       # Number of BTB hits
+system.cpu.branchPred.lookups               264432116                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         184777930                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          12360480                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            195121872                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               131792442                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             67.403057                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                31309548                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            2129742                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups         7077002                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits            5011250                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses          2065752                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted       841782                       # Number of mispredicted indirect branches.
+system.cpu.branchPred.BTBHitPct             67.543654                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                32005520                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            2166164                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         7202634                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits            5156312                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses          2046322                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted       848562                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -387,65 +396,70 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks                    558947                       # Table walker walks requested
-system.cpu.dtb.walker.walksLong                558947                       # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksLongTerminationLevel::Level2        19870                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksLongTerminationLevel::Level3       181727                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walkWaitTime::samples       558947                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0          558947    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total       558947                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples       201597                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 27104.207900                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 22942.325413                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 21051.309840                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-65535       199234     98.83%     98.83% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-131071            4      0.00%     98.83% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-196607         2010      1.00%     99.83% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-262143           57      0.03%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-327679          120      0.06%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-393215           59      0.03%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::393216-458751           92      0.05%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::458752-524287           13      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::524288-589823            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::589824-655359            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total       201597                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples  -1569310592                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0     -1569310592    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total  -1569310592                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K        181728     90.14%     90.14% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M         19870      9.86%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total       201598                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       558947                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.walks                    584775                       # Table walker walks requested
+system.cpu.dtb.walker.walksLong                584775                       # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2        23234                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3       194431                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walkWaitTime::samples       584775                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0          584775    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total       584775                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples       217665                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 25428.727632                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 21638.505013                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 16299.176879                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-32767       136227     62.59%     62.59% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::32768-65535        78767     36.19%     98.77% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-98303         1401      0.64%     99.42% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::98304-131071          854      0.39%     99.81% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-163839           27      0.01%     99.82% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::163840-196607          133      0.06%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::196608-229375           57      0.03%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::229376-262143           75      0.03%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-294911           47      0.02%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::294912-327679           26      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::327680-360447           20      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::360448-393215           15      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-425983            8      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::425984-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::458752-491519            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::491520-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total       217665                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples    -10206296                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0       -10206296    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total    -10206296                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K        194432     89.33%     89.33% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M         23234     10.67%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total       217666                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       584775                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total       558947                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       201598                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total       584775                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       217666                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total       201598                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total       760545                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total       217666                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total       802441                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                    179275780                       # DTB read hits
-system.cpu.dtb.read_misses                     461379                       # DTB read misses
-system.cpu.dtb.write_hits                   158920483                       # DTB write hits
-system.cpu.dtb.write_misses                     97568                       # DTB write misses
+system.cpu.dtb.read_hits                    184602893                       # DTB read hits
+system.cpu.dtb.read_misses                     481054                       # DTB read misses
+system.cpu.dtb.write_hits                   163948315                       # DTB write hits
+system.cpu.dtb.write_misses                    103721                       # DTB write misses
 system.cpu.dtb.flush_tlb                           11                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid               45647                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid                    1093                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                    78530                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                      1411                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                  14509                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_tlb_mva_asid               47766                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                    1117                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                    80755                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                      1436                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                  15519                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                     22879                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                179737159                       # DTB read accesses
-system.cpu.dtb.write_accesses               159018051                       # DTB write accesses
+system.cpu.dtb.perms_faults                     23435                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                185083947                       # DTB read accesses
+system.cpu.dtb.write_accesses               164052036                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                         338196263                       # DTB hits
-system.cpu.dtb.misses                          558947                       # DTB misses
-system.cpu.dtb.accesses                     338755210                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.hits                         348551208                       # DTB hits
+system.cpu.dtb.misses                          584775                       # DTB misses
+system.cpu.dtb.accesses                     349135983                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -475,634 +489,639 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks                    134834                       # Table walker walks requested
-system.cpu.itb.walker.walksLong                134834                       # Table walker walks initiated with long descriptors
-system.cpu.itb.walker.walksLongTerminationLevel::Level2         1067                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksLongTerminationLevel::Level3       117333                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walkWaitTime::samples       134834                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0          134834    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total       134834                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples       118400                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 30431.579392                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 25904.631312                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 24094.406061                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-65535       115676     97.70%     97.70% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-131071            5      0.00%     97.70% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-196607         2464      2.08%     99.78% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::196608-262143           78      0.07%     99.85% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::262144-327679          124      0.10%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::327680-393215           31      0.03%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::393216-458751           17      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::458752-524287            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total       118400                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples  -1570341092                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0     -1570341092    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total  -1570341092                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K        117333     99.10%     99.10% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::2M          1067      0.90%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total       118400                       # Table walker page sizes translated
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.walks                    136740                       # Table walker walks requested
+system.cpu.itb.walker.walksLong                136740                       # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walksLongTerminationLevel::Level2         1077                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksLongTerminationLevel::Level3       118526                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walkWaitTime::samples       136740                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0          136740    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total       136740                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples       119603                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 27883.393393                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 23898.853743                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 18564.311346                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-32767        67731     56.63%     56.63% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::32768-65535        48774     40.78%     97.41% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-98303         1154      0.96%     98.37% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::98304-131071         1639      1.37%     99.74% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-163839           37      0.03%     99.78% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::163840-196607          137      0.11%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::196608-229375           43      0.04%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::229376-262143           18      0.02%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-294911           21      0.02%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::294912-327679           20      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-360447           18      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::360448-393215            9      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::393216-425983            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total       119603                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples    -10844796                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0       -10844796    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total    -10844796                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K        118526     99.10%     99.10% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M          1077      0.90%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total       119603                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       134834                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total       134834                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       136740                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total       136740                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       118400                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total       118400                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total       253234                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                    442741882                       # ITB inst hits
-system.cpu.itb.inst_misses                     134834                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       119603                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total       119603                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total       256343                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                    457894474                       # ITB inst hits
+system.cpu.itb.inst_misses                     136740                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.itb.flush_tlb                           11                       # Number of times complete TLB was flushed
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid               45647                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid                    1093                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                    56540                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb_mva_asid               47766                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                    1117                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                    57885                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                    318606                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                    331252                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                442876716                       # ITB inst accesses
-system.cpu.itb.hits                         442741882                       # DTB hits
-system.cpu.itb.misses                          134834                       # DTB misses
-system.cpu.itb.accesses                     442876716                       # DTB accesses
-system.cpu.numPwrStateTransitions               33004                       # Number of power state transitions
-system.cpu.pwrStateClkGateDist::samples         16502                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::mean     3052827188.483881                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::stdev    59796953066.006256                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::underflows         7205     43.66%     43.66% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1000-5e+10         9262     56.13%     99.79% # Distribution of time spent in the clock gated state
+system.cpu.itb.inst_accesses                458031214                       # ITB inst accesses
+system.cpu.itb.hits                         457894474                       # DTB hits
+system.cpu.itb.misses                          136740                       # DTB misses
+system.cpu.itb.accesses                     458031214                       # DTB accesses
+system.cpu.numPwrStateTransitions               33262                       # Number of power state transitions
+system.cpu.pwrStateClkGateDist::samples         16631                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean     3032078673.597498                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev    59558384510.943253                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::underflows         7336     44.11%     44.11% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1000-5e+10         9260     55.68%     99.79% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::5e+10-1e+11            5      0.03%     99.82% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::1e+11-1.5e+11            2      0.01%     99.83% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::1.5e+11-2e+11            2      0.01%     99.84% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::2e+11-2.5e+11            2      0.01%     99.85% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::2e+11-2.5e+11            2      0.01%     99.86% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::2.5e+11-3e+11            2      0.01%     99.87% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::3e+11-3.5e+11            1      0.01%     99.87% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::4.5e+11-5e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::5.5e+11-6e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::9e+11-9.5e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::6e+11-6.5e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::8.5e+11-9e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::overflows           18      0.11%    100.00% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::max_value 1988777699120                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::total           16502                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateResidencyTicks::ON    1282963107639                       # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::CLK_GATED 50377754264361                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                       2565980290                       # number of cpu cycles simulated
+system.cpu.pwrStateClkGateDist::max_value 1988777698120                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::total           16631                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateResidencyTicks::ON    1261264097400                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 50426500420600                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                       2522582223                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   927696922                       # Number of instructions committed
-system.cpu.committedOps                    1090057089                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      94830796                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends                      7642                       # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles                 100756547271                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi                               2.765968                       # CPI: cycles per instruction
-system.cpu.ipc                               0.361537                       # IPC: instructions per cycle
+system.cpu.committedInsts                   956884636                       # Number of instructions committed
+system.cpu.committedOps                    1124405089                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                      99545013                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                      7771                       # Number of times Execute suspended instruction fetching
+system.cpu.quiesceCycles                 100854059486                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi                               2.636245                       # CPI: cycles per instruction
+system.cpu.ipc                               0.379327                       # IPC: instructions per cycle
 system.cpu.op_class_0::No_OpClass                   1      0.00%      0.00% # Class of committed instruction
-system.cpu.op_class_0::IntAlu               755349201     69.29%     69.29% # Class of committed instruction
-system.cpu.op_class_0::IntMult                2273269      0.21%     69.50% # Class of committed instruction
-system.cpu.op_class_0::IntDiv                   98990      0.01%     69.51% # Class of committed instruction
-system.cpu.op_class_0::FloatAdd                     0      0.00%     69.51% # Class of committed instruction
-system.cpu.op_class_0::FloatCmp                     0      0.00%     69.51% # Class of committed instruction
-system.cpu.op_class_0::FloatCvt                     0      0.00%     69.51% # Class of committed instruction
-system.cpu.op_class_0::FloatMult                    0      0.00%     69.51% # Class of committed instruction
-system.cpu.op_class_0::FloatDiv                     0      0.00%     69.51% # Class of committed instruction
-system.cpu.op_class_0::FloatSqrt                    0      0.00%     69.51% # Class of committed instruction
-system.cpu.op_class_0::SimdAdd                      0      0.00%     69.51% # Class of committed instruction
-system.cpu.op_class_0::SimdAddAcc                   0      0.00%     69.51% # Class of committed instruction
-system.cpu.op_class_0::SimdAlu                      0      0.00%     69.51% # Class of committed instruction
-system.cpu.op_class_0::SimdCmp                      0      0.00%     69.51% # Class of committed instruction
-system.cpu.op_class_0::SimdCvt                      0      0.00%     69.51% # Class of committed instruction
-system.cpu.op_class_0::SimdMisc                     0      0.00%     69.51% # Class of committed instruction
-system.cpu.op_class_0::SimdMult                     0      0.00%     69.51% # Class of committed instruction
-system.cpu.op_class_0::SimdMultAcc                  0      0.00%     69.51% # Class of committed instruction
-system.cpu.op_class_0::SimdShift                    0      0.00%     69.51% # Class of committed instruction
-system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     69.51% # Class of committed instruction
-system.cpu.op_class_0::SimdSqrt                     0      0.00%     69.51% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatAdd                 8      0.00%     69.51% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     69.51% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatCmp                13      0.00%     69.51% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatCvt                21      0.00%     69.51% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     69.51% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMisc           109509      0.01%     69.52% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMult                0      0.00%     69.52% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     69.52% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     69.52% # Class of committed instruction
-system.cpu.op_class_0::MemRead              173855507     15.95%     85.47% # Class of committed instruction
-system.cpu.op_class_0::MemWrite             158370570     14.53%    100.00% # Class of committed instruction
+system.cpu.op_class_0::IntAlu               779381648     69.32%     69.32% # Class of committed instruction
+system.cpu.op_class_0::IntMult                2317785      0.21%     69.52% # Class of committed instruction
+system.cpu.op_class_0::IntDiv                   99593      0.01%     69.53% # Class of committed instruction
+system.cpu.op_class_0::FloatAdd                     0      0.00%     69.53% # Class of committed instruction
+system.cpu.op_class_0::FloatCmp                     0      0.00%     69.53% # Class of committed instruction
+system.cpu.op_class_0::FloatCvt                     0      0.00%     69.53% # Class of committed instruction
+system.cpu.op_class_0::FloatMult                    0      0.00%     69.53% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv                     0      0.00%     69.53% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt                    0      0.00%     69.53% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd                      0      0.00%     69.53% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc                   0      0.00%     69.53% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu                      0      0.00%     69.53% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp                      0      0.00%     69.53% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt                      0      0.00%     69.53% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc                     0      0.00%     69.53% # Class of committed instruction
+system.cpu.op_class_0::SimdMult                     0      0.00%     69.53% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc                  0      0.00%     69.53% # Class of committed instruction
+system.cpu.op_class_0::SimdShift                    0      0.00%     69.53% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     69.53% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt                     0      0.00%     69.53% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd                 8      0.00%     69.53% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     69.53% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp                13      0.00%     69.53% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt                21      0.00%     69.53% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     69.53% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc           108729      0.01%     69.54% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult                0      0.00%     69.54% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     69.54% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     69.54% # Class of committed instruction
+system.cpu.op_class_0::MemRead              179105650     15.93%     85.47% # Class of committed instruction
+system.cpu.op_class_0::MemWrite             163391641     14.53%    100.00% # Class of committed instruction
 system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
-system.cpu.op_class_0::total               1090057089                       # Class of committed instruction
+system.cpu.op_class_0::total               1124405089                       # Class of committed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    16502                       # number of quiesce instructions executed
-system.cpu.tickCycles                      1756726391                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       809253899                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements          10800470                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.930063                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           322845784                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs          10800982                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             29.890410                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        7088310500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.930063                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999863                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999863                       # Average percentage of cache occupancy
+system.cpu.kern.inst.quiesce                    16631                       # number of quiesce instructions executed
+system.cpu.tickCycles                      1810679239                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       711902984                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements          11237287                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.957340                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           332608189                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs          11237799                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             29.597272                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        4326295500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.957340                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999917                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999917                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          390                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           57                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           71                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          392                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           48                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1354272764                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1354272764                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data    165477998                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       165477998                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    148389977                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      148389977                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       514152                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        514152                       # number of SoftPFReq hits
-system.cpu.dcache.WriteLineReq_hits::cpu.data       336855                       # number of WriteLineReq hits
-system.cpu.dcache.WriteLineReq_hits::total       336855                       # number of WriteLineReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      3884412                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      3884412                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data      4194010                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      4194010                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     314204830                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        314204830                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    314718982                       # number of overall hits
-system.cpu.dcache.overall_hits::total       314718982                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      5939711                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       5939711                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      4167073                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      4167073                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data      1413293                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total      1413293                       # number of SoftPFReq misses
-system.cpu.dcache.WriteLineReq_misses::cpu.data      1239143                       # number of WriteLineReq misses
-system.cpu.dcache.WriteLineReq_misses::total      1239143                       # number of WriteLineReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data       311310                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total       311310                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses        1395920077                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1395920077                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data    170244902                       # number of ReadReq hits
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+system.cpu.dcache.WriteLineReq_hits::cpu.data       336678                       # number of WriteLineReq hits
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+system.cpu.dcache.WriteLineReq_misses::cpu.data      1246141                       # number of WriteLineReq misses
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 system.cpu.dcache.StoreCondReq_misses::cpu.data            1                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data     11345927                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       11345927                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     12759220                       # number of overall misses
-system.cpu.dcache.overall_misses::total      12759220                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 110013337000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 110013337000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 204497661000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 204497661000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  53262030500                       # number of WriteLineReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::total  53262030500                       # number of WriteLineReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   5161319000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total   5161319000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        82000                       # number of StoreCondReq miss cycles
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-system.cpu.dcache.demand_miss_latency::cpu.data 367773028500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 367773028500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 367773028500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 367773028500                       # number of overall miss cycles
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-system.cpu.dcache.WriteLineReq_accesses::cpu.data      1575998                       # number of WriteLineReq accesses(hits+misses)
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-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4195722                       # number of LoadLockedReq accesses(hits+misses)
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-system.cpu.dcache.demand_accesses::total    325550757                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    327478202                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    327478202                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.034651                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.034651                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.027315                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.027315                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.733247                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.733247                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.786259                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::total     0.786259                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.074197                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.074197                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_misses::cpu.data     11771553                       # number of demand (read+write) misses
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+system.cpu.dcache.ReadReq_miss_latency::cpu.data 101076172500                       # number of ReadReq miss cycles
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+system.cpu.dcache.WriteLineReq_miss_latency::total  27433825500                       # number of WriteLineReq miss cycles
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+system.cpu.dcache.LoadLockedReq_miss_latency::total   4889648000                       # number of LoadLockedReq miss cycles
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+system.cpu.dcache.demand_miss_latency::total 286223426000                       # number of demand (read+write) miss cycles
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+system.cpu.dcache.overall_miss_latency::total 286223426000                       # number of overall miss cycles
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+system.cpu.dcache.SoftPFReq_accesses::total      2029102                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::cpu.data      1582819                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::total      1582819                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4386978                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      4386978                       # number of LoadLockedReq accesses(hits+misses)
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+system.cpu.dcache.demand_accesses::cpu.data    335369239                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    335369239                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    337398341                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    337398341                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.034936                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.034936                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.027719                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.027719                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.741243                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.741243                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.787292                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::total     0.787292                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.073135                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.073135                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000000                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.034851                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.034851                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.038962                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.038962                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18521.664943                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 18521.664943                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49074.652880                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 49074.652880                       # average WriteReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 42982.957173                       # average WriteLineReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::total 42982.957173                       # average WriteLineReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16579.354984                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16579.354984                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        82000                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total        82000                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 32414.542108                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 32414.542108                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 28824.099631                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 28824.099631                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.035100                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.035100                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.039347                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.039347                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16400.338615                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16400.338615                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36153.251980                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 36153.251980                       # average WriteReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 22015.025186                       # average WriteLineReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::total 22015.025186                       # average WriteLineReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15240.097120                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15240.097120                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        83000                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total        83000                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 24314.839852                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 24314.839852                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 21560.094372                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 21560.094372                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks      8297164                       # number of writebacks
-system.cpu.dcache.writebacks::total           8297164                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       307308                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       307308                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1836532                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1836532                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data          159                       # number of WriteLineReq MSHR hits
-system.cpu.dcache.WriteLineReq_mshr_hits::total          159                       # number of WriteLineReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        69724                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        69724                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      2143999                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      2143999                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      2143999                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      2143999                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5632403                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      5632403                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2330541                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      2330541                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1405812                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total      1405812                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1238984                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::total      1238984                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       241586                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total       241586                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks      8619796                       # number of writebacks
+system.cpu.dcache.writebacks::total           8619796                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       315342                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       315342                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1930607                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1930607                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data          154                       # number of WriteLineReq MSHR hits
+system.cpu.dcache.WriteLineReq_mshr_hits::total          154                       # number of WriteLineReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        70929                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        70929                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      2246103                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      2246103                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      2246103                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2246103                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5847712                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      5847712                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2431751                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      2431751                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1496531                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total      1496531                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1245987                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::total      1245987                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       249912                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total       249912                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            1                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      9201928                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9201928                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data     10607740                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total     10607740                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33697                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.ReadReq_mshr_uncacheable::total        33697                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33706                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total        33706                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67403                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total        67403                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  96403190500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  96403190500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 108391524000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 108391524000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  26704093000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  26704093000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  52015388000                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  52015388000                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3504907500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3504907500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        81000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        81000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 256810102500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 256810102500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 283514195500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 283514195500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6197989500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6197989500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6197989500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   6197989500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032858                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032858                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015277                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015277                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.729366                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.729366                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.786158                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.786158                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.057579                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.057579                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data      9525450                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9525450                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data     11021981                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total     11021981                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33698                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.ReadReq_mshr_uncacheable::total        33698                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33707                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total        33707                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67405                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total        67405                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  89040002500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  89040002500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  82314078000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  82314078000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  24215113000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  24215113000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  26183606500                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  26183606500                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3424677000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3424677000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        82000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        82000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 197537687000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 197537687000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 221752800000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 221752800000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6231251500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6231251500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6231251500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   6231251500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.033149                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.033149                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015452                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015452                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.737534                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.737534                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.787195                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.787195                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.056967                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.056967                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000000                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.028266                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.028266                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.032392                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.032392                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17115.819039                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17115.819039                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46509.168472                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46509.168472                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18995.493708                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18995.493708                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 41982.291942                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 41982.291942                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14507.908157                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14507.908157                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        81000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        81000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27908.292969                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 27908.292969                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26727.106386                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26727.106386                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183932.976229                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183932.976229                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91954.208270                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91954.208270                       # average overall mshr uncacheable latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements          24348068                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.885312                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           418063563                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs          24348580                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             17.169936                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       32786837500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.885312                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.999776                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.999776                       # Average percentage of cache occupancy
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.028403                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.028403                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.032668                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.032668                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15226.468489                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15226.468489                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33849.714876                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33849.714876                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16180.829532                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16180.829532                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 21014.349668                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 21014.349668                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13703.531643                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13703.531643                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        82000                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        82000                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20737.885034                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20737.885034                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20119.141922                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20119.141922                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184914.579500                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184914.579500                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92444.944737                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92444.944737                       # average overall mshr uncacheable latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements          24740790                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.930482                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           432810859                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs          24741302                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             17.493455                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       20587192500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.930482                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.999864                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.999864                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           95                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          318                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           99                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           87                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          308                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          117                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         466760742                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        466760742                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst    418063563                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       418063563                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     418063563                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        418063563                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    418063563                       # number of overall hits
-system.cpu.icache.overall_hits::total       418063563                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst     24348590                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total      24348590                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst     24348590                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total       24348590                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst     24348590                       # number of overall misses
-system.cpu.icache.overall_misses::total      24348590                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 329659145500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 329659145500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 329659145500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 329659145500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 329659145500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 329659145500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    442412153                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    442412153                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    442412153                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    442412153                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    442412153                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    442412153                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.055036                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.055036                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.055036                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.055036                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.055036                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.055036                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13539.147257                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13539.147257                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13539.147257                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13539.147257                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13539.147257                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13539.147257                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses         482293482                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        482293482                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst    432810859                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       432810859                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     432810859                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        432810859                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    432810859                       # number of overall hits
+system.cpu.icache.overall_hits::total       432810859                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst     24741312                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total      24741312                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst     24741312                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total       24741312                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst     24741312                       # number of overall misses
+system.cpu.icache.overall_misses::total      24741312                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 329592002500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 329592002500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 329592002500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 329592002500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 329592002500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 329592002500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    457552171                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    457552171                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    457552171                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    457552171                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    457552171                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    457552171                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.054073                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.054073                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.054073                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.054073                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.054073                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.054073                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13321.524845                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13321.524845                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13321.524845                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13321.524845                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13321.524845                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13321.524845                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks     24348068                       # number of writebacks
-system.cpu.icache.writebacks::total          24348068                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst     24348590                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total     24348590                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst     24348590                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total     24348590                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst     24348590                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total     24348590                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        52309                       # number of ReadReq MSHR uncacheable
-system.cpu.icache.ReadReq_mshr_uncacheable::total        52309                       # number of ReadReq MSHR uncacheable
-system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        52309                       # number of overall MSHR uncacheable misses
-system.cpu.icache.overall_mshr_uncacheable_misses::total        52309                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 305310556500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 305310556500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 305310556500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 305310556500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 305310556500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 305310556500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   6746653000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   6746653000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   6746653000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total   6746653000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.055036                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.055036                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.055036                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.055036                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.055036                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.055036                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12539.147298                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12539.147298                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12539.147298                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12539.147298                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12539.147298                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12539.147298                       # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 128976.906460                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 128976.906460                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 128976.906460                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 128976.906460                       # average overall mshr uncacheable latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements          1508622                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65349.873719                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           66336088                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1571990                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            42.198798                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      10459942000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 36987.173983                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   327.335267                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   410.823725                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  8044.893687                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 19579.647057                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.564379                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004995                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006269                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.122755                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.298762                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.997160                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023          289                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        63079                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4          289                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           45                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          541                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2400                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5595                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54498                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004410                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.962509                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        577006805                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       577006805                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       916908                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       278918                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1195826                       # number of ReadReq hits
-system.cpu.l2cache.WritebackDirty_hits::writebacks      8297164                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      8297164                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks     24344519                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total     24344519                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data        10512                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total        10512                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1646050                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1646050                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     24242763                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total     24242763                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6965917                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      6965917                       # number of ReadSharedReq hits
-system.cpu.l2cache.InvalidateReq_hits::cpu.data       704740                       # number of InvalidateReq hits
-system.cpu.l2cache.InvalidateReq_hits::total       704740                       # number of InvalidateReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker       916908                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker       278918                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst     24242763                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      8611967                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total        34050556                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker       916908                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker       278918                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst     24242763                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      8611967                       # number of overall hits
-system.cpu.l2cache.overall_hits::total       34050556                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         5752                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         4871                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        10623                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data        37790                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total        37790                       # number of UpgradeReq misses
+system.cpu.icache.writebacks::writebacks     24740790                       # number of writebacks
+system.cpu.icache.writebacks::total          24740790                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst     24741312                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total     24741312                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst     24741312                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total     24741312                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst     24741312                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total     24741312                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        52293                       # number of ReadReq MSHR uncacheable
+system.cpu.icache.ReadReq_mshr_uncacheable::total        52293                       # number of ReadReq MSHR uncacheable
+system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        52293                       # number of overall MSHR uncacheable misses
+system.cpu.icache.overall_mshr_uncacheable_misses::total        52293                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 304850691500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 304850691500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 304850691500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 304850691500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 304850691500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 304850691500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   4087122500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   4087122500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   4087122500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total   4087122500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.054073                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.054073                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.054073                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.054073                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.054073                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.054073                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12321.524885                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12321.524885                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12321.524885                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12321.524885                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12321.524885                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12321.524885                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 78158.118677                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 78158.118677                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 78158.118677                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 78158.118677                       # average overall mshr uncacheable latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.replacements          1647378                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65415.989966                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           70152651                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1710758                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            41.006765                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle       5897369000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks  9082.397486                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   468.031396                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   465.228429                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  8079.882193                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 47320.450462                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.138586                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.007142                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.007099                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.123289                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.722053                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.998169                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023          304                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        63076                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4          301                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          292                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          861                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5993                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55903                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004639                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.962463                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        587932179                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       587932179                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       928594                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       259345                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1187939                       # number of ReadReq hits
+system.cpu.l2cache.WritebackDirty_hits::writebacks      8619796                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      8619796                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks     24737128                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total     24737128                       # number of WritebackClean hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data        30047                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total        30047                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1665980                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1665980                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     24634240                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total     24634240                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      7256699                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      7256699                       # number of ReadSharedReq hits
+system.cpu.l2cache.InvalidateReq_hits::cpu.data       698207                       # number of InvalidateReq hits
+system.cpu.l2cache.InvalidateReq_hits::total       698207                       # number of InvalidateReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker       928594                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker       259345                       # number of demand (read+write) hits
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+system.cpu.l2cache.demand_hits::total        34744858                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker       928594                       # number of overall hits
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+system.cpu.l2cache.overall_hits::cpu.data      8922679                       # number of overall hits
+system.cpu.l2cache.overall_hits::total       34744858                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         6617                       # number of ReadReq misses
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+system.cpu.l2cache.ReadReq_misses::total        12237                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data         4025                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total         4025                       # number of UpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            1                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            1                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       636382                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       636382                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst       105826                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total       105826                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       313691                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       313691                       # number of ReadSharedReq misses
-system.cpu.l2cache.InvalidateReq_misses::cpu.data       534244                       # number of InvalidateReq misses
-system.cpu.l2cache.InvalidateReq_misses::total       534244                       # number of InvalidateReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker         5752                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker         4871                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst       105826                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       950073                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       1066522                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker         5752                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker         4871                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst       105826                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       950073                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1066522                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    785759500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    668656000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   1454415500                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data   1443890500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total   1443890500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data        79500                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::total        79500                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  84519588500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  84519588500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst  14015218000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total  14015218000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  42318242000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  42318242000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data     10682500                       # number of InvalidateReq miss cycles
-system.cpu.l2cache.InvalidateReq_miss_latency::total     10682500                       # number of InvalidateReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    785759500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    668656000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst  14015218000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 126837830500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 142307464000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker    785759500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    668656000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst  14015218000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 126837830500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 142307464000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       922660                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       283789                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1206449                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      8297164                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total      8297164                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks     24344519                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total     24344519                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data        48302                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total        48302                       # number of UpgradeReq accesses(hits+misses)
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 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            1                       # number of SCUpgradeReq accesses(hits+misses)
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+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.007075                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.021210                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.010196                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.118132                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.118132                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.278818                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.278818                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.004346                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.004346                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.043092                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.043092                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.431195                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::total     0.431195                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.006234                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.017164                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.004346                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.099359                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.030370                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.006234                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.017164                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.004346                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.099359                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.030370                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 136606.310848                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 137272.839253                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 136911.936364                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 38208.269383                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 38208.269383                       # average UpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        79500                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        79500                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 132812.663620                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 132812.663620                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132436.433391                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132436.433391                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134904.227409                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134904.227409                       # average ReadSharedReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data    19.995545                       # average InvalidateReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::total    19.995545                       # average InvalidateReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136606.310848                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 137272.839253                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132436.433391                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 133503.247119                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 133431.344126                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136606.310848                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 137272.839253                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132436.433391                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 133503.247119                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 133431.344126                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.305219                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.305219                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.004328                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.004328                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.044415                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.044415                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.439635                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::total     0.439635                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.007075                       # miss rate for demand accesses
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+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 88356.850534                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 88218.231593                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 17972.298137                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 17972.298137                       # average UpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        80500                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        80500                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82944.880088                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82944.880088                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82689.995424                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82689.995424                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85550.018234                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85550.018234                       # average ReadSharedReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data     3.421081                       # average InvalidateReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::total     3.421081                       # average InvalidateReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 88100.498715                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 88356.850534                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82689.995424                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83766.724656                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 83715.554881                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 88100.498715                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 88356.850534                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82689.995424                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83766.724656                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 83715.554881                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks      1279776                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1279776                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks      1406063                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1406063                       # number of writebacks
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            3                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total            3                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           21                       # number of ReadSharedReq MSHR hits
@@ -1113,191 +1132,191 @@ system.cpu.l2cache.demand_mshr_hits::total           24                       #
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            3                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data           21                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total           24                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         5752                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         4871                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        10623                       # number of ReadReq MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            4                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total            4                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        37790                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total        37790                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         6617                       # number of ReadReq MSHR misses
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+system.cpu.l2cache.ReadReq_mshr_misses::total        12237                       # number of ReadReq MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            3                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total            3                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         4025                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         4025                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            1                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       636382                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       636382                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst       105823                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total       105823                       # number of ReadCleanReq MSHR misses
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-system.cpu.l2cache.InvalidateReq_mshr_misses::total       534244                       # number of InvalidateReq MSHR misses
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-system.cpu.l2cache.overall_mshr_misses::total      1066498                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        52309                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33697                       # number of ReadReq MSHR uncacheable
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-system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33706                       # number of WriteReq MSHR uncacheable
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-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1348185500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   2569159500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   2569159500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        69500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        69500                       # number of SCUpgradeReq MSHR miss cycles
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-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total  12956680572                       # number of ReadCleanReq MSHR miss cycles
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-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  37222318500                       # number of InvalidateReq MSHR miss cycles
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-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 117334990928                       # number of demand (read+write) MSHR miss cycles
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-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5776686000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  11712542500                       # number of ReadReq MSHR uncacheable cycles
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-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.006234                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.017164                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.008805                       # mshr miss rate for ReadReq accesses
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    440365500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    957156500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     76811500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     76811500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        70500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        70500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  53386023001                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  53386023001                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   7782841501                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   7782841501                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  25481161022                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  25481161022                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  11306022501                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  11306022501                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    516791000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    440365500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   7782841501                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  78867184023                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  87607182024                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    516791000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    440365500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   7782841501                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  78867184023                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  87607182024                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   3276571500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5809931000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   9086502500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   3276571500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5809931000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   9086502500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.007075                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.021210                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.010196                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.782369                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.782369                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.118132                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.118132                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.278818                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.278818                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.004346                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.004346                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.043089                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.043089                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.431195                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.431195                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.006234                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.017164                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.004346                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.099357                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.030370                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.006234                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.017164                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.004346                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.099357                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.030370                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126606.310848                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 127272.839253                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 126911.936364                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 67985.168034                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 67985.168034                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        69500                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        69500                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 122812.641665                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 122812.641665                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122437.282746                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122437.282746                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124905.908758                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124905.908758                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69672.880744                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69672.880744                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126606.310848                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127272.839253                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122437.282746                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123503.756561                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123431.883604                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126606.310848                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127272.839253                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122437.282746                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123503.756561                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123431.883604                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113476.772640                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171430.275692                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136182.853522                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113476.772640                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85703.692714                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 97839.335238                       # average overall mshr uncacheable latency
-system.cpu.toL2Bus.snoop_filter.tot_requests     71038022                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests     35888421                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         4192                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         2302                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2302                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.305219                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.305219                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.004327                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.004327                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.044412                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.044412                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.439635                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.439635                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.007075                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.021210                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.004327                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.107001                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.033073                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.007075                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.021210                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.004327                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.107001                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.033073                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 78100.498715                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 78356.850534                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 78218.231593                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19083.602484                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19083.602484                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        70500                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        70500                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72944.879406                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72944.879406                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72690.640537                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72690.640537                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75552.119164                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75552.119164                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20639.713938                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20639.713938                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 78100.498715                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 78356.850534                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72690.640537                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73767.351916                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73716.178974                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 78100.498715                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 78356.850534                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72690.640537                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73767.351916                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73716.178974                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62657.937009                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172411.745504                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 105668.064100                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62657.937009                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86194.362436                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 75911.899113                       # average overall mshr uncacheable latency
+system.cpu.toL2Bus.snoop_filter.tot_requests     72719983                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests     36740859                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         4284                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         1912                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1912                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadReq        1730261                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      33359239                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         33706                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        33706                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      9683600                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean     24348068                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      2741013                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq        48305                       # Transaction distribution
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadReq        1798088                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      34134170                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         33707                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        33707                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty     10025859                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean     24740790                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      2858806                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq        34075                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            1                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp        48306                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      2282432                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      2282432                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq     24348590                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      7288491                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq      1345648                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateResp      1238984                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     73149864                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     32634714                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       686896                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2163808                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total         108635282                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   3119933760                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1143229458                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2270312                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      7381280                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         4272814810                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     2178284                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic              92284400                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples     38701577                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.018037                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.133086                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeResp        34076                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      2397848                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      2397848                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq     24741312                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      7596551                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq      1271756                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateResp      1245987                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     74327998                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     33916673                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       673778                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2238495                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total         111156944                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   3170201152                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1191384986                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2119720                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      7481688                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         4371187546                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     2188425                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic              94133704                       # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples     39520716                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.018595                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.135091                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           38003503     98.20%     98.20% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             698074      1.80%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           38785811     98.14%     98.14% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             734905      1.86%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       38701577                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    68717300491                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       39520716                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    70288980496                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy      1477390                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy      1482392                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy   36605927318                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy   37194713363                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   15037927648                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   15679329987                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy     403140932                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy     408839447                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy    1241184926                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy    1303303960                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq                40331                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40331                       # Transaction distribution
+system.iobus.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.iobus.trans_dist::ReadReq                40309                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40309                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
 system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
@@ -1314,11 +1333,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231020                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231020                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230976                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230976                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353804                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353760                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
@@ -1333,16 +1352,16 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334512                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334512                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334336                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334336                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492432                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             37711500                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7492256                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             37793000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                11000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               336000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               335000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer3.occupancy                10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
@@ -1352,7 +1371,7 @@ system.iobus.reqLayer10.occupancy                9000                       # La
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer13.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy                9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer15.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
@@ -1360,75 +1379,75 @@ system.iobus.reqLayer16.occupancy               16000                       # La
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            25249000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            25128500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            36460500                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            36456000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           567164602                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           569339894                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147780000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147736000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements               115492                       # number of replacements
-system.iocache.tags.tagsinuse               10.441393                       # Cycle average of tags in use
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.replacements               115470                       # number of replacements
+system.iocache.tags.tagsinuse               10.448409                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115508                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115486                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13153371816000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.521310                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.920084                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.220082                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.432505                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.652587                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13140724969000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.519445                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.928964                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.219965                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.433060                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.653026                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039947                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039947                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.tag_accesses              1039749                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039749                       # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8846                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8883                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8824                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8861                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide       115510                       # number of demand (read+write) misses
-system.iocache.demand_misses::total            115550                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide       115488                       # number of demand (read+write) misses
+system.iocache.demand_misses::total            115528                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide       115510                       # number of overall misses
-system.iocache.overall_misses::total           115550                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5070000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1687962584                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1693032584                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide       115488                       # number of overall misses
+system.iocache.overall_misses::total           115528                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5086000                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1631024611                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1636110611                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  13411761018                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  13411761018                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5421000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide  15099723602                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  15105144602                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5421000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide  15099723602                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  15105144602                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  12739251283                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  12739251283                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5437000                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide  14370275894                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  14375712894                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5437000                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide  14370275894                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total  14375712894                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8846                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8883                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8824                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8861                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide       115510                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total          115550                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide       115488                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total          115528                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide       115510                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total         115550                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide       115488                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total         115528                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -1442,53 +1461,53 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137027.027027                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 190816.480217                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 190592.433187                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 184839.597801                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 184641.757251                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125738.403004                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 125738.403004                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       135525                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 130722.219739                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 130723.882319                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       135525                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 130722.219739                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 130723.882319                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         34055                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 119433.466615                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 119433.466615                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet       135925                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 124430.900994                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 124434.880670                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet       135925                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 124430.900994                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 124434.880670                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         31942                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3409                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3389                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.989733                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.425199                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.writebacks::writebacks          106631                       # number of writebacks
 system.iocache.writebacks::total               106631                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8846                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8883                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8824                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8861                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide       115510                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total       115550                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide       115488                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total       115528                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide       115510                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total       115550                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3220000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1245662584                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1248882584                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide       115488                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total       115528                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3236000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1189824611                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1193060611                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8073418582                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   8073418582                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3421000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   9319081166                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   9322502166                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3421000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   9319081166                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   9322502166                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7399114026                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   7399114026                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3437000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   8588938637                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   8592375637                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3437000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   8588938637                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   8592375637                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -1502,89 +1521,95 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87027.027027                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 140816.480217                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 140592.433187                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134839.597801                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 134641.757251                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75690.191461                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75690.191461                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85525                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 80677.700338                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 80679.378330                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85525                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 80677.700338                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 80679.378330                       # average overall mshr miss latency
-system.membus.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq               86006                       # Transaction distribution
-system.membus.trans_dist::ReadResp             525005                       # Transaction distribution
-system.membus.trans_dist::WriteReq              33706                       # Transaction distribution
-system.membus.trans_dist::WriteResp             33706                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1386407                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           236604                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            38552                       # Transaction distribution
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69368.428204                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69368.428204                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85925                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 74370.831922                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 74374.832396                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85925                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 74370.831922                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 74374.832396                       # average overall mshr miss latency
+system.membus.snoop_filter.tot_requests       3617552                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests      1792214                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests         3206                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
+system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadReq               85991                       # Transaction distribution
+system.membus.trans_dist::ReadResp             551423                       # Transaction distribution
+system.membus.trans_dist::WriteReq              33707                       # Transaction distribution
+system.membus.trans_dist::WriteResp             33707                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1512694                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           249055                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4641                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               7                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            635760                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           635760                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        438999                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        640771                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            731311                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           731311                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        465432                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        654388                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           32                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6916                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4321043                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4450695                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237576                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       237576                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4688271                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6920                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4683490                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4813146                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237510                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       237510                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5050656                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          740                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13832                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    153447468                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    153617874                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7242560                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7242560                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               160860434                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             3013                       # Total snoops (count)
-system.membus.snoopTraffic                     192384                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples           3496836                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13840                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    169337260                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    169507674                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7241152                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7241152                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               176748826                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             3012                       # Total snoops (count)
+system.membus.snoopTraffic                     192320                       # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples           1975472                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.014689                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.120303                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 3496836    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 1946455     98.53%     98.53% # Request fanout histogram
+system.membus.snoop_fanout::1                   29017      1.47%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3496836                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            99852500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             1975472                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            99807500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               18828                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5614500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5588000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          9224879373                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          9976212567                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         6035081327                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         6680987810                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           44925690                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           44817130                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
 system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
 system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
 system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
 system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
 system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
@@ -1627,28 +1652,28 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
 system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000                       # Cumulative time (in ticks) in various power states
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000                       # Cumulative time (in ticks) in various power states
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt
index 0a085b4b5..12a2f6bdf 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt
@@ -1,140 +1,140 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.327143                       # Number of seconds simulated
-sim_ticks                                51327142820000                       # Number of ticks simulated
-final_tick                               51327142820000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.558015                       # Number of seconds simulated
+sim_ticks                                51558014828000                       # Number of ticks simulated
+final_tick                               51558014828000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 124063                       # Simulator instruction rate (inst/s)
-host_op_rate                                   145776                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             7507150065                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 681576                       # Number of bytes of host memory used
-host_seconds                                  6837.10                       # Real time elapsed on the host
-sim_insts                                   848230502                       # Number of instructions simulated
-sim_ops                                     996685945                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 110619                       # Simulator instruction rate (inst/s)
+host_op_rate                                   130023                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5152408080                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 695916                       # Number of bytes of host memory used
+host_seconds                                 10006.59                       # Real time elapsed on the host
+sim_insts                                  1106923026                       # Number of instructions simulated
+sim_ops                                    1301083589                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.dtb.walker       227712                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker       212864                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           5673056                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          41642312                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        444928                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             48200872                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      5673056                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5673056                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     68445056                       # Number of bytes written to this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.dtb.walker       667968                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker       559488                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           6546400                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         112650248                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        429376                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            120853480                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      6546400                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         6546400                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks    140957120                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          68465636                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker         3558                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker         3326                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             104594                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             650674                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6952                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                769104                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1069454                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total         140977700                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker        10437                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker         8742                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             118240                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1760173                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6709                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1904301                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         2202455                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1072027                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker           4436                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker           4147                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               110527                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               811312                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8668                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                  939091                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          110527                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             110527                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1333506                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data                 401                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1333907                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1333506                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          4436                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker          4147                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              110527                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              811713                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8668                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2272998                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        769104                       # Number of read requests accepted
-system.physmem.writeReqs                      1072027                       # Number of write requests accepted
-system.physmem.readBursts                      769104                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1072027                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 49176064                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     46592                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  68464384                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  48200872                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               68465636                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      728                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2250                       # Number of DRAM write bursts merged with an existing one
+system.physmem.num_writes::total              2205028                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker          12956                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker          10852                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               126972                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2184922                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8328                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2344029                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          126972                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             126972                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2733952                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data                 399                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2734351                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2733952                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker         12956                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker         10852                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              126972                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2185321                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8328                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                5078380                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1904301                       # Number of read requests accepted
+system.physmem.writeReqs                      2205028                       # Number of write requests accepted
+system.physmem.readBursts                     1904301                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    2205028                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                121838144                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     37120                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                 140976896                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 120853480                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys              140977700                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      580                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               44564                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               52315                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               47721                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               44538                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               44659                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               50872                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               46439                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               47959                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               44018                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               71274                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              43972                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              51692                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              45026                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              46672                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              42515                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              44140                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               64758                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               69412                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               67623                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               66442                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               66817                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               69740                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               65132                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               69008                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               65482                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               70623                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              64235                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              70444                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              64965                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              66804                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              64273                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              63998                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              114327                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              123692                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              118245                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              117057                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              115229                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              125268                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              115683                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              119593                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              115543                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              144676                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             112600                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             120122                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             113965                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             118266                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             113146                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             116309                       # Per bank write bursts
+system.physmem.perBankWrBursts::0              135142                       # Per bank write bursts
+system.physmem.perBankWrBursts::1              141643                       # Per bank write bursts
+system.physmem.perBankWrBursts::2              136917                       # Per bank write bursts
+system.physmem.perBankWrBursts::3              137997                       # Per bank write bursts
+system.physmem.perBankWrBursts::4              135684                       # Per bank write bursts
+system.physmem.perBankWrBursts::5              143871                       # Per bank write bursts
+system.physmem.perBankWrBursts::6              135153                       # Per bank write bursts
+system.physmem.perBankWrBursts::7              138864                       # Per bank write bursts
+system.physmem.perBankWrBursts::8              135935                       # Per bank write bursts
+system.physmem.perBankWrBursts::9              142790                       # Per bank write bursts
+system.physmem.perBankWrBursts::10             134947                       # Per bank write bursts
+system.physmem.perBankWrBursts::11             140191                       # Per bank write bursts
+system.physmem.perBankWrBursts::12             134987                       # Per bank write bursts
+system.physmem.perBankWrBursts::13             137976                       # Per bank write bursts
+system.physmem.perBankWrBursts::14             134592                       # Per bank write bursts
+system.physmem.perBankWrBursts::15             136075                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          34                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51327141408500                       # Total gap between requests
+system.physmem.numWrRetry                         125                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51558013451500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                   21272                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  747819                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1883016                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1069454                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    515353                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    203905                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     30484                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     12938                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       574                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       579                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       553                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      1284                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       806                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       364                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      401                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      183                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      172                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      141                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      125                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      125                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      111                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      106                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       94                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       69                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        9                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                2202455                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1140639                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    689076                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     48103                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     20384                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       609                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       486                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       633                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       498                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      1348                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       388                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      416                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      194                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      189                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      133                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      126                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      123                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      108                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      105                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       90                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       64                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        8                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
@@ -160,171 +160,170 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    26806                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    32475                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    49254                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    54613                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    60437                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    61007                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    61838                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    62183                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    62151                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    69842                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    64006                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    76985                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    62423                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    65026                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    68511                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    60500                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    59306                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    57192                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     3147                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     1524                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1240                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      919                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      939                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      829                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      673                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      609                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      591                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      462                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      293                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      314                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      359                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      262                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      302                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      251                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      241                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      318                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      215                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      262                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      145                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      182                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      155                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      131                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      121                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      143                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      131                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      126                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       82                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       74                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       471870                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      249.306089                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     149.569568                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     290.567780                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         207742     44.03%     44.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       122462     25.95%     69.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        42886      9.09%     79.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        22733      4.82%     83.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        14982      3.18%     87.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         9606      2.04%     89.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         7566      1.60%     90.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         6003      1.27%     91.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        37890      8.03%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         471870                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         54238                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        14.166341                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev       76.651597                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511           54233     99.99%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-1023            2      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-1535            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                    30482                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    38490                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    83702                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                   117171                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                   125843                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                   130438                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                   133004                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                   138248                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                   140822                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                   137539                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                   142466                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                   143357                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                   133954                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::30                   127299                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                   130102                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                   120942                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::35                     2807                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::39                     1875                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::41                     1659                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                     1634                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::45                     1307                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::56                     1049                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      833                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      758                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::62                      312                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                      365                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       933198                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      281.628105                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     167.352526                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     309.404332                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         371108     39.77%     39.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       233427     25.01%     64.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        88383      9.47%     74.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        51664      5.54%     79.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        37413      4.01%     83.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        26389      2.83%     86.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895        21045      2.26%     88.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023        17945      1.92%     90.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        85824      9.20%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         933198                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples        116229                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        16.379053                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev       52.340079                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511          116223     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023            4      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::13824-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           54238                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         54238                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        19.723367                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.775784                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        8.950161                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           40620     74.89%     74.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23            4585      8.45%     83.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27            5200      9.59%     92.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31            1381      2.55%     95.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             413      0.76%     96.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             235      0.43%     96.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             311      0.57%     97.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47             127      0.23%     97.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             390      0.72%     98.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55             127      0.23%     98.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              50      0.09%     98.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              65      0.12%     98.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             327      0.60%     99.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              36      0.07%     99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              29      0.05%     99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79             111      0.20%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83             166      0.31%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               3      0.01%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               3      0.01%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.00%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               1      0.00%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.00%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.00%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             2      0.00%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             2      0.00%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.00%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             5      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            17      0.03%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.00%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147            12      0.02%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             5      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::212-215             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           54238                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    15209667379                       # Total ticks spent queuing
-system.physmem.totMemAccLat               29616717379                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   3841880000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       19794.56                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total          116229                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples        116228                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        18.951965                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.478061                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       17.079115                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-31          111884     96.26%     96.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-47            1770      1.52%     97.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-63             397      0.34%     98.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-79             626      0.54%     98.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-95             488      0.42%     99.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-111            246      0.21%     99.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-127           362      0.31%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-143           120      0.10%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-159            64      0.06%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-175            59      0.05%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-191            51      0.04%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-207            11      0.01%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-223            17      0.01%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-239            10      0.01%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-255            37      0.03%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-271            24      0.02%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-287            14      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::288-303             3      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::304-319             2      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::320-335             1      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::336-351             2      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::352-367             6      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::368-383             5      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::384-399             4      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::400-415             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::416-431             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::480-495             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::496-511             3      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::512-527             4      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::528-543             3      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::544-559             2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::608-623             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::624-639             2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::640-655             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::752-767             2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::768-783             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::976-991             2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total          116228                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    42075497859                       # Total ticks spent queuing
+system.physmem.totMemAccLat               77770266609                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   9518605000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       22101.71                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  38544.56                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           0.96                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.33                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        0.94                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.33                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  40851.71                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.36                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.73                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.34                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.73                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.49                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     580662                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    785598                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   75.57                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.44                       # Row buffer hit rate for writes
-system.physmem.avgGap                     27878049.64                       # Average gap between requests
-system.physmem.pageHitRate                      74.33                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 1803657240                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  984138375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                2956722600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3492279360                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3352439216880                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1235640856320                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29712388110000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34309704980775                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.451533                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49429181288166                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1713925980000                       # Time in different power states
+system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        26.62                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1533744                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                   1639539                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   80.57                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  74.43                       # Row buffer hit rate for writes
+system.physmem.avgGap                     12546577.18                       # Average gap between requests
+system.physmem.pageHitRate                      77.27                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 3530119320                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1926156375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                7402894200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               7162084800                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3367518529440                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1313077918185                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29782982922000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34483600624320                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.831109                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49545451951432                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1721635240000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    184032075584                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    290927248568                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 1763679960                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  962325375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                3036563400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3439739520                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3352439216880                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1235034526230                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29712919978500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34309596029865                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.449411                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49430060847495                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1713925980000                       # Time in different power states
+system.physmem_1.actEnergy                 3524804640                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1923256500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                7446082800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               7111728720                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3367518529440                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1314046606680                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29782133195250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34483704204030                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.833118                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49544014933949                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1721635240000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    183155359005                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    292364518051                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
 system.realview.nvmem.bytes_read::cpu.inst          384                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           420                       # Number of bytes read from this memory
@@ -341,30 +340,30 @@ system.realview.nvmem.bw_inst_read::total            7                       # I
 system.realview.nvmem.bw_total::cpu.inst            7                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups               225047911                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         149825196                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          12305756                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            158986930                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                98148773                       # Number of BTB hits
+system.cpu.branchPred.lookups               290131106                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         198353835                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          13679752                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            208494226                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               130534623                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             61.733863                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                30878370                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             343644                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups         6734089                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits            4745857                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses          1988232                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted       765703                       # Number of mispredicted indirect branches.
+system.cpu.branchPred.BTBHitPct             62.608268                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                37597374                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             402079                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         8125236                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits            6045082                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses          2080154                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted       800698                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
 system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -394,47 +393,47 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.checker.dstage2_mmu.stage2_tlb.hits            0                       # DTB hits
 system.cpu.checker.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.cpu.checker.dtb.walker.walks            197474                       # Table walker walks requested
-system.cpu.checker.dtb.walker.walksLong        197474                       # Table walker walks initiated with long descriptors
-system.cpu.checker.dtb.walker.walkWaitTime::samples       197474                       # Table walker wait (enqueue to first request) latency
-system.cpu.checker.dtb.walker.walkWaitTime::0       197474    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.checker.dtb.walker.walkWaitTime::total       197474                       # Table walker wait (enqueue to first request) latency
-system.cpu.checker.dtb.walker.walksPending::samples  -1584953796                       # Table walker pending requests distribution
-system.cpu.checker.dtb.walker.walksPending::0  -1584953796    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.checker.dtb.walker.walksPending::total  -1584953796                       # Table walker pending requests distribution
-system.cpu.checker.dtb.walker.walkPageSizes::4K       153977     91.65%     91.65% # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkPageSizes::2M        14023      8.35%    100.00% # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkPageSizes::total       168000                       # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data       197474                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.cpu.checker.dtb.walker.walks            345580                       # Table walker walks requested
+system.cpu.checker.dtb.walker.walksLong        345580                       # Table walker walks initiated with long descriptors
+system.cpu.checker.dtb.walker.walkWaitTime::samples       345580                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walkWaitTime::0       345580    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walkWaitTime::total       345580                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walksPending::samples   1638693500                       # Table walker pending requests distribution
+system.cpu.checker.dtb.walker.walksPending::0   1638693500    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.checker.dtb.walker.walksPending::total   1638693500                       # Table walker pending requests distribution
+system.cpu.checker.dtb.walker.walkPageSizes::4K       271194     90.38%     90.38% # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkPageSizes::2M        28860      9.62%    100.00% # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkPageSizes::total       300054                       # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data       345580                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total       197474                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data       168000                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total       345580                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data       300054                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total       168000                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin::total       365474                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total       300054                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin::total       645634                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
 system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
-system.cpu.checker.dtb.read_hits            159568162                       # DTB read hits
-system.cpu.checker.dtb.read_misses             146947                       # DTB read misses
-system.cpu.checker.dtb.write_hits           144766301                       # DTB write hits
-system.cpu.checker.dtb.write_misses             50527                       # DTB write misses
-system.cpu.checker.dtb.flush_tlb                   20                       # Number of times complete TLB was flushed
+system.cpu.checker.dtb.read_hits            205011929                       # DTB read hits
+system.cpu.checker.dtb.read_misses             252661                       # DTB read misses
+system.cpu.checker.dtb.write_hits           188856696                       # DTB write hits
+system.cpu.checker.dtb.write_misses             92919                       # DTB write misses
+system.cpu.checker.dtb.flush_tlb                   22                       # Number of times complete TLB was flushed
 system.cpu.checker.dtb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
-system.cpu.checker.dtb.flush_tlb_mva_asid        78770                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.checker.dtb.flush_tlb_asid            2038                       # Number of times TLB was flushed by ASID
-system.cpu.checker.dtb.flush_entries            71659                       # Number of entries that have been flushed from TLB
+system.cpu.checker.dtb.flush_tlb_mva_asid       126550                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.checker.dtb.flush_tlb_asid            2406                       # Number of times TLB was flushed by ASID
+system.cpu.checker.dtb.flush_entries            84606                       # Number of entries that have been flushed from TLB
 system.cpu.checker.dtb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
-system.cpu.checker.dtb.prefetch_faults           6990                       # Number of TLB faults due to prefetch
+system.cpu.checker.dtb.prefetch_faults          10719                       # Number of TLB faults due to prefetch
 system.cpu.checker.dtb.domain_faults                0                       # Number of TLB faults due to domain restrictions
-system.cpu.checker.dtb.perms_faults             19053                       # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses        159715109                       # DTB read accesses
-system.cpu.checker.dtb.write_accesses       144816828                       # DTB write accesses
+system.cpu.checker.dtb.perms_faults             24551                       # Number of TLB faults due to permissions restrictions
+system.cpu.checker.dtb.read_accesses        205264590                       # DTB read accesses
+system.cpu.checker.dtb.write_accesses       188949615                       # DTB write accesses
 system.cpu.checker.dtb.inst_accesses                0                       # ITB inst accesses
-system.cpu.checker.dtb.hits                 304334463                       # DTB hits
-system.cpu.checker.dtb.misses                  197474                       # DTB misses
-system.cpu.checker.dtb.accesses             304531937                       # DTB accesses
-system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
+system.cpu.checker.dtb.hits                 393868625                       # DTB hits
+system.cpu.checker.dtb.misses                  345580                       # DTB misses
+system.cpu.checker.dtb.accesses             394214205                       # DTB accesses
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -464,51 +463,51 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.checker.istage2_mmu.stage2_tlb.hits            0                       # DTB hits
 system.cpu.checker.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.checker.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.cpu.checker.itb.walker.walks            119817                       # Table walker walks requested
-system.cpu.checker.itb.walker.walksLong        119817                       # Table walker walks initiated with long descriptors
-system.cpu.checker.itb.walker.walkWaitTime::samples       119817                       # Table walker wait (enqueue to first request) latency
-system.cpu.checker.itb.walker.walkWaitTime::0       119817    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.checker.itb.walker.walkWaitTime::total       119817                       # Table walker wait (enqueue to first request) latency
-system.cpu.checker.itb.walker.walksPending::samples  -1586149296                       # Table walker pending requests distribution
-system.cpu.checker.itb.walker.walksPending::0  -1586149296    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.checker.itb.walker.walksPending::total  -1586149296                       # Table walker pending requests distribution
-system.cpu.checker.itb.walker.walkPageSizes::4K       107958     98.83%     98.83% # Table walker page sizes translated
-system.cpu.checker.itb.walker.walkPageSizes::2M         1280      1.17%    100.00% # Table walker page sizes translated
-system.cpu.checker.itb.walker.walkPageSizes::total       109238                       # Table walker page sizes translated
+system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.cpu.checker.itb.walker.walks            130718                       # Table walker walks requested
+system.cpu.checker.itb.walker.walksLong        130718                       # Table walker walks initiated with long descriptors
+system.cpu.checker.itb.walker.walkWaitTime::samples       130718                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.itb.walker.walkWaitTime::0       130718    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.checker.itb.walker.walkWaitTime::total       130718                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.itb.walker.walksPending::samples   1638085000                       # Table walker pending requests distribution
+system.cpu.checker.itb.walker.walksPending::0   1638085000    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.checker.itb.walker.walksPending::total   1638085000                       # Table walker pending requests distribution
+system.cpu.checker.itb.walker.walkPageSizes::4K       116451     98.90%     98.90% # Table walker page sizes translated
+system.cpu.checker.itb.walker.walkPageSizes::2M         1296      1.10%    100.00% # Table walker page sizes translated
+system.cpu.checker.itb.walker.walkPageSizes::total       117747                       # Table walker page sizes translated
 system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst       119817                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total       119817                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst       130718                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total       130718                       # Table walker requests started/completed, data/inst
 system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst       109238                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total       109238                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin::total       229055                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.inst_hits            848636866                       # ITB inst hits
-system.cpu.checker.itb.inst_misses             119817                       # ITB inst misses
+system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst       117747                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total       117747                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin::total       248465                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.inst_hits           1107463254                       # ITB inst hits
+system.cpu.checker.itb.inst_misses             130718                       # ITB inst misses
 system.cpu.checker.itb.read_hits                    0                       # DTB read hits
 system.cpu.checker.itb.read_misses                  0                       # DTB read misses
 system.cpu.checker.itb.write_hits                   0                       # DTB write hits
 system.cpu.checker.itb.write_misses                 0                       # DTB write misses
-system.cpu.checker.itb.flush_tlb                   20                       # Number of times complete TLB was flushed
+system.cpu.checker.itb.flush_tlb                   22                       # Number of times complete TLB was flushed
 system.cpu.checker.itb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
-system.cpu.checker.itb.flush_tlb_mva_asid        78770                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.checker.itb.flush_tlb_asid            2038                       # Number of times TLB was flushed by ASID
-system.cpu.checker.itb.flush_entries            51647                       # Number of entries that have been flushed from TLB
+system.cpu.checker.itb.flush_tlb_mva_asid       126550                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.checker.itb.flush_tlb_asid            2406                       # Number of times TLB was flushed by ASID
+system.cpu.checker.itb.flush_entries            56882                       # Number of entries that have been flushed from TLB
 system.cpu.checker.itb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
 system.cpu.checker.itb.prefetch_faults              0                       # Number of TLB faults due to prefetch
 system.cpu.checker.itb.domain_faults                0                       # Number of TLB faults due to domain restrictions
 system.cpu.checker.itb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
 system.cpu.checker.itb.read_accesses                0                       # DTB read accesses
 system.cpu.checker.itb.write_accesses               0                       # DTB write accesses
-system.cpu.checker.itb.inst_accesses        848756683                       # ITB inst accesses
-system.cpu.checker.itb.hits                 848636866                       # DTB hits
-system.cpu.checker.itb.misses                  119817                       # DTB misses
-system.cpu.checker.itb.accesses             848756683                       # DTB accesses
-system.cpu.checker.pwrStateResidencyTicks::ON 51327142820000                       # Cumulative time (in ticks) in various power states
-system.cpu.checker.numCycles                997255251                       # number of cpu cycles simulated
+system.cpu.checker.itb.inst_accesses       1107593972                       # ITB inst accesses
+system.cpu.checker.itb.hits                1107463254                       # DTB hits
+system.cpu.checker.itb.misses                  130718                       # DTB misses
+system.cpu.checker.itb.accesses            1107593972                       # DTB accesses
+system.cpu.checker.pwrStateResidencyTicks::ON 51558014828000                       # Cumulative time (in ticks) in various power states
+system.cpu.checker.numCycles               1301797660                       # number of cpu cycles simulated
 system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
 system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -538,87 +537,88 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks                    948773                       # Table walker walks requested
-system.cpu.dtb.walker.walksLong                948773                       # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksLongTerminationLevel::Level2        15596                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksLongTerminationLevel::Level3       155468                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore       437937                       # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples       510836                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean  2285.186439                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev 14758.274331                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-65535       507265     99.30%     99.30% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::65536-131071         2025      0.40%     99.70% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::131072-196607         1066      0.21%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::196608-262143          211      0.04%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::262144-327679          145      0.03%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::327680-393215           26      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::393216-458751           51      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::458752-524287           43      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.walks                   1423094                       # Table walker walks requested
+system.cpu.dtb.walker.walksLong               1423094                       # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2        30587                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3       273540                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore       668841                       # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples       754253                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean  2502.822660                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev 16371.142747                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-65535       747574     99.11%     99.11% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::65536-131071         4739      0.63%     99.74% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::131072-196607          871      0.12%     99.86% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::196608-262143          433      0.06%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::262144-327679          327      0.04%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::327680-393215           64      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::393216-458751          235      0.03%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::458752-524287            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::524288-589823            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::655360-720895            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total       510836                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples       488329                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 23221.803333                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 18175.804190                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 21042.780895                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-65535       476828     97.64%     97.64% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-131071         7891      1.62%     99.26% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-196607         2533      0.52%     99.78% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-262143          229      0.05%     99.83% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-327679          568      0.12%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-393215          131      0.03%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::393216-458751          114      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::458752-524287           26      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::524288-589823            6      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total       488329                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 779668986876                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean     0.725199                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev     0.523523                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0-1  777411937376     99.71%     99.71% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::2-3    1169683000      0.15%     99.86% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::4-5     513347500      0.07%     99.93% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::6-7     208116000      0.03%     99.95% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::8-9     157188000      0.02%     99.97% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::10-11    121226500      0.02%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::12-13     32342000      0.00%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::14-15     52541000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::16-17      2605500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 779668986876                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K        155469     90.88%     90.88% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M         15596      9.12%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total       171065                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       948773                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkWaitTime::655360-720895            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total       754253                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples       795185                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 25800.017606                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 21033.129871                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 18337.040091                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-65535       776690     97.67%     97.67% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-131071        15553      1.96%     99.63% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-196607         1840      0.23%     99.86% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::196608-262143          558      0.07%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-327679          320      0.04%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::327680-393215          153      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-458751           44      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::458752-524287           19      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::524288-589823            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total       795185                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 1040609044948                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean     0.747004                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev     0.517062                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1  1036648437448     99.62%     99.62% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3    2501393000      0.24%     99.86% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5     710900000      0.07%     99.93% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7     286069000      0.03%     99.96% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9     201203000      0.02%     99.97% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::10-11    121106500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::12-13     48982500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::14-15     87667500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::16-17      3189000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::18-19        41500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::20-21        55500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total 1040609044948                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K        273541     89.94%     89.94% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M         30587     10.06%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total       304128                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data      1423094                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total       948773                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       171065                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total      1423094                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       304128                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total       171065                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total      1119838                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total       304128                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total      1727222                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                    169411407                       # DTB read hits
-system.cpu.dtb.read_misses                     675369                       # DTB read misses
-system.cpu.dtb.write_hits                   147344334                       # DTB write hits
-system.cpu.dtb.write_misses                    273404                       # DTB write misses
-system.cpu.dtb.flush_tlb                           20                       # Number of times complete TLB was flushed
+system.cpu.dtb.read_hits                    217549636                       # DTB read hits
+system.cpu.dtb.read_misses                    1002675                       # DTB read misses
+system.cpu.dtb.write_hits                   192429615                       # DTB write hits
+system.cpu.dtb.write_misses                    420419                       # DTB write misses
+system.cpu.dtb.flush_tlb                           22                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid               78770                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid                    2038                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                    71963                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                       101                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                  10047                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_tlb_mva_asid              126550                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                    2406                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                    84838                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                       110                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                  16158                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                     69388                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                170086776                       # DTB read accesses
-system.cpu.dtb.write_accesses               147617738                       # DTB write accesses
+system.cpu.dtb.perms_faults                     86326                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                218552311                       # DTB read accesses
+system.cpu.dtb.write_accesses               192850034                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                         316755741                       # DTB hits
-system.cpu.dtb.misses                          948773                       # DTB misses
-system.cpu.dtb.accesses                     317704514                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.hits                         409979251                       # DTB hits
+system.cpu.dtb.misses                         1423094                       # DTB misses
+system.cpu.dtb.accesses                     411402345                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -648,1104 +648,1098 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks                    162181                       # Table walker walks requested
-system.cpu.itb.walker.walksLong                162181                       # Table walker walks initiated with long descriptors
-system.cpu.itb.walker.walksLongTerminationLevel::Level2         1496                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksLongTerminationLevel::Level3       120027                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksSquashedBefore        17971                       # Table walks squashed before starting
-system.cpu.itb.walker.walkWaitTime::samples       144210                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::mean  1137.740101                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::stdev  9342.723838                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0-32767       143038     99.19%     99.19% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::32768-65535          619      0.43%     99.62% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::65536-98303           86      0.06%     99.68% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::98304-131071          189      0.13%     99.81% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::131072-163839          221      0.15%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::163840-196607           35      0.02%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::196608-229375            6      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::229376-262143            8      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::262144-294911            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::294912-327679            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::327680-360447            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::360448-393215            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::393216-425983            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total       144210                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples       139494                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 29066.088864                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 24052.553358                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 24213.231696                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-65535       136396     97.78%     97.78% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-131071          707      0.51%     98.29% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-196607         1985      1.42%     99.71% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::196608-262143          151      0.11%     99.82% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::262144-327679          171      0.12%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::327680-393215           34      0.02%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::393216-458751           34      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::458752-524287            9      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::524288-589823            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total       139494                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples 676589720772                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::mean     0.947980                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::stdev     0.222341                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0     35236838356      5.21%      5.21% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::1    641313182416     94.79%     99.99% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::2        39010000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::3          686000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::4            4000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total 676589720772                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K        120027     98.77%     98.77% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::2M          1496      1.23%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total       121523                       # Table walker page sizes translated
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.walks                    177767                       # Table walker walks requested
+system.cpu.itb.walker.walksLong                177767                       # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walksLongTerminationLevel::Level2         1532                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksLongTerminationLevel::Level3       128663                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksSquashedBefore        19966                       # Table walks squashed before starting
+system.cpu.itb.walker.walkWaitTime::samples       157801                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean  1393.783943                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev  9971.559116                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-32767       155663     98.65%     98.65% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::32768-65535         1042      0.66%     99.31% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::65536-98303          672      0.43%     99.73% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::98304-131071          333      0.21%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::131072-163839           30      0.02%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::163840-196607           26      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::196608-229375           15      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::229376-262143            4      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::262144-294911            4      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::294912-327679            7      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::327680-360447            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::360448-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total       157801                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples       150161                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 28501.914612                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 23015.105793                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 23459.229673                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-65535       144112     95.97%     95.97% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-131071         5152      3.43%     99.40% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-196607          475      0.32%     99.72% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::196608-262143          255      0.17%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-327679           99      0.07%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-393215           55      0.04%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::393216-458751            8      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::458752-524287            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total       150161                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples 911756921068                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean     0.951043                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev     0.216068                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0     44693483152      4.90%      4.90% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1    867007398416     95.09%     99.99% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::2        55571500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::3          466000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::4            2000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total 911756921068                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K        128663     98.82%     98.82% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M          1532      1.18%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total       130195                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       162181                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total       162181                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       177767                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total       177767                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       121523                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total       121523                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total       283704                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                    357038073                       # ITB inst hits
-system.cpu.itb.inst_misses                     162181                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       130195                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total       130195                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total       307962                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                    462600046                       # ITB inst hits
+system.cpu.itb.inst_misses                     177767                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.flush_tlb                           20                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb                           22                       # Number of times complete TLB was flushed
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid               78770                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid                    2038                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                    52848                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb_mva_asid              126550                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                    2406                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                    58185                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                    357344                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                    440221                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                357200254                       # ITB inst accesses
-system.cpu.itb.hits                         357038073                       # DTB hits
-system.cpu.itb.misses                          162181                       # DTB misses
-system.cpu.itb.accesses                     357200254                       # DTB accesses
-system.cpu.numPwrStateTransitions               32228                       # Number of power state transitions
-system.cpu.pwrStateClkGateDist::samples         16114                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::mean     3134631677.512784                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::stdev    60494120707.852806                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::underflows         6793     42.16%     42.16% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1000-5e+10         9285     57.62%     99.78% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::5e+10-1e+11            5      0.03%     99.81% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1e+11-1.5e+11            4      0.02%     99.83% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1.5e+11-2e+11            1      0.01%     99.84% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::2e+11-2.5e+11            2      0.01%     99.85% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::2.5e+11-3e+11            1      0.01%     99.86% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::3e+11-3.5e+11            2      0.01%     99.87% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::5e+11-5.5e+11            2      0.01%     99.88% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::7e+11-7.5e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
+system.cpu.itb.inst_accesses                462777813                       # ITB inst accesses
+system.cpu.itb.hits                         462600046                       # DTB hits
+system.cpu.itb.misses                          177767                       # DTB misses
+system.cpu.itb.accesses                     462777813                       # DTB accesses
+system.cpu.numPwrStateTransitions               34262                       # Number of power state transitions
+system.cpu.pwrStateClkGateDist::samples         17131                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean     2947433272.666569                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev    58590018858.186401                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::underflows         7811     45.60%     45.60% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1000-5e+10         9284     54.19%     99.79% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::5e+10-1e+11            5      0.03%     99.82% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1e+11-1.5e+11            4      0.02%     99.84% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1.5e+11-2e+11            1      0.01%     99.85% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::2e+11-2.5e+11            2      0.01%     99.86% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::2.5e+11-3e+11            1      0.01%     99.87% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::3e+11-3.5e+11            2      0.01%     99.88% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::4.5e+11-5e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::5e+11-5.5e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::9.5e+11-1e+12            1      0.01%     99.89% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::overflows           18      0.11%    100.00% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::max_value 1988780762168                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::total           16114                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateResidencyTicks::ON    815687968559                       # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::CLK_GATED 50511454851441                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                       1631385344                       # number of cpu cycles simulated
+system.cpu.pwrStateClkGateDist::total           17131                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateResidencyTicks::ON    1065535433949                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 50492479394051                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                       2131080190                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          646877625                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1002761410                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   225047911                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          133773000                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     898188451                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                26266186                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                    3841497                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                30548                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles       8722394                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles      1026877                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles         1034                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 356664988                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               6247416                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                   47904                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples         1571821519                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.747042                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.149310                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          789533395                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1294232501                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   290131106                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          174177079                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                    1253396684                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                29442936                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                    4521296                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                28032                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles      11449142                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles      1221670                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          685                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 462141962                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               6901101                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                   52491                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples         2074872372                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.731015                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.142682                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0               1014113227     64.52%     64.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                214297646     13.63%     78.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 70312417      4.47%     82.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                273098229     17.37%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0               1354023092     65.26%     65.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                279633538     13.48%     78.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 86518146      4.17%     82.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                354697596     17.09%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1571821519                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.137949                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.614669                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                526332322                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             552246914                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 434136742                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              49729183                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                9376358                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             33563941                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred               3814299                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             1086052117                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              29449193                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                9376358                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                571289803                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                66024800                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles      371545208                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 438989582                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             114595768                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1065754363                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts               6907795                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               5097238                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 334375                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 639506                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               63573833                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents            20465                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          1013430764                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1640279788                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1259572075                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           1474026                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             947250209                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 66180552                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts           26901106                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts       23243208                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 101784051                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            173837388                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           150829276                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           9883117                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          9014861                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1030729252                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded            27201158                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1045808358                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           3377405                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        61244461                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     34071399                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         308913                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1571821519                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.665348                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.919634                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total           2074872372                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.136143                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.607313                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                615922756                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             835719938                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 532432043                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              80077312                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               10720323                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             41258933                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred               4059445                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             1407827153                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              33008479                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               10720323                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                679035070                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                79966926                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles      552687037                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 549603762                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             202859254                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1383638167                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts               8109162                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               7348509                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 966276                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                1094350                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents              119568064                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents            22725                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          1333397174                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            2200696007                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1641425227                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           1433031                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps            1254726296                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 78670875                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts           43643507                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts       39180007                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 166278031                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            222554034                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           196867138                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          12635283                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         11114743                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1330840515                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded            43953891                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1360477402                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           4212137                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        73710813                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     41934009                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         368799                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    2074872372                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.655692                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.916068                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           924230442     58.80%     58.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           334342298     21.27%     80.07% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           234750151     14.93%     95.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            72048277      4.58%     99.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             6430828      0.41%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5               19523      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0          1226409345     59.11%     59.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           451307165     21.75%     80.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           291780533     14.06%     94.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            95920964      4.62%     99.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             9425546      0.45%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5               28819      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1571821519                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      2074872372                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                57691324     35.03%     35.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                 100152      0.06%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                   26730      0.02%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc              622      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               44285841     26.89%     62.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              62576075     38.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                73561900     34.17%     34.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                  90692      0.04%     34.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                   26794      0.01%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc              484      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               57931960     26.91%     61.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              83660297     38.86%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass                11      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             720343690     68.88%     68.88% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2530628      0.24%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                122776      0.01%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                 375      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               8      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp              15      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt              23      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc         119191      0.01%     69.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     69.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     69.14% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            173490543     16.59%     85.73% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           149201098     14.27%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass                57      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             939889673     69.09%     69.09% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2936613      0.22%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                130878      0.01%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 372      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               8      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp              15      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt              23      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc         112363      0.01%     69.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     69.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     69.32% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            222587367     16.36%     85.68% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           194820033     14.32%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1045808358                       # Type of FU issued
-system.cpu.iq.rate                           0.641055                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   164680744                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.157467                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         3829023509                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        1118377930                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1027460456                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             2472874                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             938610                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       909796                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1208933693                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 1555398                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          4274316                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1360477402                       # Type of FU issued
+system.cpu.iq.rate                           0.638398                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   215272127                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.158233                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         5012901497                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        1447776434                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1338315649                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             2409942                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             914537                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       885572                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1574233532                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 1515940                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          5717597                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     14173969                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        14495                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       142953                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      6059351                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     17343387                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        24124                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       187368                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      7978529                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      2526453                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       1440750                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      3596780                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       1680866                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                9376358                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 7004216                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               6913167                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1058165202                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles               10720323                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                12040487                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               4569260                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1375079942                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             173837388                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            150829276                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts           22819114                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  57849                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               6781828                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         142953                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        3462734                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      5495013                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              8957747                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1034296660                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             169399584                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          10573772                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts             222554034                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            196867138                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts           38644291                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 177419                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               4207009                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         187368                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        4048268                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      6103351                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             10151619                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1346834094                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             217554512                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          12249639                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        234792                       # number of nop insts executed
-system.cpu.iew.exec_refs                    316739180                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                196198672                       # Number of branches executed
-system.cpu.iew.exec_stores                  147339596                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.633999                       # Inst execution rate
-system.cpu.iew.wb_sent                     1029187818                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1028370252                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 437853372                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 708400240                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       0.630366                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.618088                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts        51884426                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls        26892245                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           8549021                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1559762540                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.638999                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.273827                       # Number of insts commited each cycle
+system.cpu.iew.exec_nop                        285536                       # number of nop insts executed
+system.cpu.iew.exec_refs                    409993947                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                255680172                       # Number of branches executed
+system.cpu.iew.exec_stores                  192439435                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.631996                       # Inst execution rate
+system.cpu.iew.wb_sent                     1340240150                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1339201221                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 574929948                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 943031378                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       0.628414                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.609662                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts        62850702                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls        43585092                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           9678607                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   2060674246                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.631387                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.270689                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0   1047991029     67.19%     67.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    288035307     18.47%     85.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    120100080      7.70%     93.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     36659789      2.35%     95.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     28506606      1.83%     97.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     13942789      0.89%     98.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      8651847      0.55%     98.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      4181084      0.27%     99.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     11694009      0.75%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0   1383412740     67.13%     67.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    394991247     19.17%     86.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    150433823      7.30%     93.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     44582057      2.16%     95.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     36156812      1.75%     97.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     18175173      0.88%     98.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     10964042      0.53%     98.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      5475656      0.27%     99.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     16482696      0.80%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1559762540                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            848230502                       # Number of instructions committed
-system.cpu.commit.committedOps              996685945                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total   2060674246                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts           1106923026                       # Number of instructions committed
+system.cpu.commit.committedOps             1301083589                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      304433343                       # Number of memory references committed
-system.cpu.commit.loads                     159663418                       # Number of loads committed
-system.cpu.commit.membars                     6927415                       # Number of memory barriers committed
-system.cpu.commit.branches                  189324067                       # Number of branches committed
-system.cpu.commit.fp_insts                     898712                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 915721971                       # Number of committed integer instructions.
-system.cpu.commit.function_calls             25285288                       # Number of function calls committed.
+system.cpu.commit.refs                      394099255                       # Number of memory references committed
+system.cpu.commit.loads                     205210646                       # Number of loads committed
+system.cpu.commit.membars                     9122435                       # Number of memory barriers committed
+system.cpu.commit.branches                  247396089                       # Number of branches committed
+system.cpu.commit.fp_insts                     873905                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                1189215854                       # Number of committed integer instructions.
+system.cpu.commit.function_calls             30973786                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        689893101     69.22%     69.22% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult         2149376      0.22%     69.43% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv            98151      0.01%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd              0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp              0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt              0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult             0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv              0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd               0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu               0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp               0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt               0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc              0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult              0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift             0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd            8      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp           13      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt           21      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc       111932      0.01%     69.46% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     69.46% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.46% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.46% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead       159663418     16.02%     85.47% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite      144769925     14.53%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        904226715     69.50%     69.50% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult         2546778      0.20%     69.69% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv           104952      0.01%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            8      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp           13      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt           21      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc       105847      0.01%     69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead       205210646     15.77%     85.48% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite      188888609     14.52%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         996685945                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              11694009                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   2589097882                       # The number of ROB reads
-system.cpu.rob.rob_writes                  2109106528                       # The number of ROB writes
-system.cpu.timesIdled                         8171713                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        59563825                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                 101022900419                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   848230502                       # Number of Instructions Simulated
-system.cpu.committedOps                     996685945                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.923281                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.923281                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.519945                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.519945                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1223820104                       # number of integer regfile reads
-system.cpu.int_regfile_writes               731394908                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   1462803                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   780644                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 225050166                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                225684828                       # number of cc regfile writes
-system.cpu.misc_regfile_reads              2570368432                       # number of misc regfile reads
-system.cpu.misc_regfile_writes               26931155                       # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements           9701158                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.972800                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           283187639                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9701670                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             29.189577                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        2743199500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.972800                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999947                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999947                       # Average percentage of cache occupancy
+system.cpu.commit.op_class_0::total        1301083589                       # Class of committed instruction
+system.cpu.commit.bw_lim_events              16482696                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   3398675710                       # The number of ROB reads
+system.cpu.rob.rob_writes                  2741957858                       # The number of ROB writes
+system.cpu.timesIdled                         9058128                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        56207818                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                 100984949503                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                  1106923026                       # Number of Instructions Simulated
+system.cpu.committedOps                    1301083589                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               1.925229                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.925229                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.519419                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.519419                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1599627417                       # number of integer regfile reads
+system.cpu.int_regfile_writes               942915982                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   1421408                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   762380                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 312164706                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                313034766                       # number of cc regfile writes
+system.cpu.misc_regfile_reads              3414318389                       # number of misc regfile reads
+system.cpu.misc_regfile_writes               44468731                       # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements          13662519                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.983620                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           361203380                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs          13663031                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             26.436548                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        1659288500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.983620                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999968                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999968                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           97                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          392                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           23                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           89                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          395                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           28                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1237018765                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1237018765                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data    147199934                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       147199934                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    128255410                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      128255410                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       377663                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        377663                       # number of SoftPFReq hits
-system.cpu.dcache.WriteLineReq_hits::cpu.data       323814                       # number of WriteLineReq hits
-system.cpu.dcache.WriteLineReq_hits::total       323814                       # number of WriteLineReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      3295431                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      3295431                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data      3691256                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      3691256                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     275779158                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        275779158                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    276156821                       # number of overall hits
-system.cpu.dcache.overall_hits::total       276156821                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      9580915                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       9580915                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data     11254027                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total     11254027                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data      1170464                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total      1170464                       # number of SoftPFReq misses
-system.cpu.dcache.WriteLineReq_misses::cpu.data      1233639                       # number of WriteLineReq misses
-system.cpu.dcache.WriteLineReq_misses::total      1233639                       # number of WriteLineReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data       446709                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total       446709                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data            8                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total            8                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data     22068581                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       22068581                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     23239045                       # number of overall misses
-system.cpu.dcache.overall_misses::total      23239045                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 168767240000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 168767240000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 444298934810                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 444298934810                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  52375248289                       # number of WriteLineReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::total  52375248289                       # number of WriteLineReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   6883962000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total   6883962000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       380500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       380500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 665441423099                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 665441423099                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 665441423099                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 665441423099                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    156780849                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    156780849                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    139509437                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    139509437                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data      1548127                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total      1548127                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::cpu.data      1557453                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::total      1557453                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3742140                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      3742140                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data      3691264                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      3691264                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    297847739                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    297847739                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    299395866                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    299395866                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.061110                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.061110                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.080669                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.080669                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.756052                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.756052                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.792087                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::total     0.792087                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.119373                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.119373                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.tags.tag_accesses        1599492126                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1599492126                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data    186946586                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       186946586                       # number of ReadReq hits
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+system.cpu.dcache.SoftPFReq_hits::cpu.data       463383                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        463383                       # number of SoftPFReq hits
+system.cpu.dcache.WriteLineReq_hits::cpu.data       333988                       # number of WriteLineReq hits
+system.cpu.dcache.WriteLineReq_hits::total       333988                       # number of WriteLineReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      4793284                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      4793284                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      5278947                       # number of StoreCondReq hits
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+system.cpu.dcache.demand_hits::total        350624733                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    351088116                       # number of overall hits
+system.cpu.dcache.overall_hits::total       351088116                       # number of overall hits
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+system.cpu.dcache.WriteReq_misses::cpu.data     18648516                       # number of WriteReq misses
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+system.cpu.dcache.SoftPFReq_misses::total      2041461                       # number of SoftPFReq misses
+system.cpu.dcache.WriteLineReq_misses::cpu.data      1270506                       # number of WriteLineReq misses
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+system.cpu.dcache.StoreCondReq_misses::cpu.data            9                       # number of StoreCondReq misses
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+system.cpu.dcache.demand_misses::total       32707083                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     34748544                       # number of overall misses
+system.cpu.dcache.overall_misses::total      34748544                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 205827865000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 205827865000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 1003464059741                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 1003464059741                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  29968640002                       # number of WriteLineReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::total  29968640002                       # number of WriteLineReq miss cycles
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+system.cpu.dcache.LoadLockedReq_miss_latency::total   8933513500                       # number of LoadLockedReq miss cycles
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+system.cpu.dcache.StoreCondReq_miss_latency::total       300500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 1239260564743                       # number of demand (read+write) miss cycles
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+system.cpu.dcache.overall_miss_latency::cpu.data 1239260564743                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 1239260564743                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    199734647                       # number of ReadReq accesses(hits+misses)
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+system.cpu.dcache.SoftPFReq_accesses::total      2504844                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::cpu.data      1604494                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::total      1604494                       # number of WriteLineReq accesses(hits+misses)
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+system.cpu.dcache.LoadLockedReq_accesses::total      5341653                       # number of LoadLockedReq accesses(hits+misses)
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+system.cpu.dcache.demand_accesses::cpu.data    383331816                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    383331816                       # number of demand (read+write) accesses
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+system.cpu.dcache.overall_accesses::total    385836660                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.064025                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.064025                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.102468                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.102468                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.815005                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.815005                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.791842                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::total     0.791842                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.102659                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.102659                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000002                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000002                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.074093                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.074093                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.077620                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.077620                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17614.939700                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 17614.939700                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39479.106884                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 39479.106884                       # average WriteReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 42455.895354                       # average WriteLineReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::total 42455.895354                       # average WriteLineReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15410.394686                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15410.394686                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 47562.500000                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 47562.500000                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 30153.339859                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 30153.339859                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 28634.628622                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 28634.628622                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     32224409                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.085323                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.085323                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.090060                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.090060                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16095.314606                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16095.314606                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53809.325082                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 53809.325082                       # average WriteReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 23587.956296                       # average WriteLineReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::total 23587.956296                       # average WriteLineReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16291.062223                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16291.062223                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 33388.888889                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 33388.888889                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 37889.669487                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 37889.669487                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 35663.668807                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 35663.668807                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     24419954                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs           1601607                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs           2093623                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    20.120048                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    11.663969                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks      7504086                       # number of writebacks
-system.cpu.dcache.writebacks::total           7504086                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4456599                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      4456599                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      9250788                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      9250788                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data         7056                       # number of WriteLineReq MSHR hits
-system.cpu.dcache.WriteLineReq_mshr_hits::total         7056                       # number of WriteLineReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       219268                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total       219268                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data     13714443                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total     13714443                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data     13714443                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total     13714443                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5124316                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      5124316                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2003239                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      2003239                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1163648                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total      1163648                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1226583                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::total      1226583                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       227441                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total       227441                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            8                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total            8                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      8354138                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      8354138                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      9517786                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9517786                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33678                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.ReadReq_mshr_uncacheable::total        33678                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33696                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total        33696                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67374                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total        67374                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  84959954500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  84959954500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  77558080846                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  77558080846                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  23723735000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  23723735000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  50708992789                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  50708992789                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3202218000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3202218000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       372500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       372500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 213227028135                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 213227028135                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 236950763135                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 236950763135                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6192056000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6192056000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6192056000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   6192056000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032685                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032685                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014359                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014359                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.751649                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.751649                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.787557                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.787557                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.060778                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.060778                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.writebacks::writebacks     10319802                       # number of writebacks
+system.cpu.dcache.writebacks::total          10319802                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      5736139                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      5736139                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data     15576096                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total     15576096                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data         6849                       # number of WriteLineReq MSHR hits
+system.cpu.dcache.WriteLineReq_mshr_hits::total         6849                       # number of WriteLineReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       265006                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total       265006                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data     21319084                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total     21319084                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data     21319084                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total     21319084                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7051922                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7051922                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      3072420                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      3072420                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      2034687                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total      2034687                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1263657                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::total      1263657                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       283363                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total       283363                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            9                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total            9                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data     11387999                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total     11387999                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data     13422686                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total     13422686                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33692                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.ReadReq_mshr_uncacheable::total        33692                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33703                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total        33703                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67395                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total        67395                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 110827450000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 110827450000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 147154305213                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 147154305213                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  32559356000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  32559356000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  28426038502                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  28426038502                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   4117736500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   4117736500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       291500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       291500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 286407793715                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 286407793715                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 318967149715                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 318967149715                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6225596500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6225596500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6225596500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   6225596500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.035306                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.035306                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.016882                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.016882                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.812301                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.812301                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.787574                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.787574                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.053048                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.053048                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000002                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.028048                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.028048                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.031790                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.031790                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16579.764890                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16579.764890                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38716.339311                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38716.339311                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 20387.380892                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 20387.380892                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 41341.672589                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 41341.672589                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14079.334860                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14079.334860                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 46562.500000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 46562.500000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25523.522371                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25523.522371                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24895.575834                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 24895.575834                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183860.561791                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183860.561791                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91905.720308                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91905.720308                       # average overall mshr uncacheable latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements          15134592                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.928988                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           340756209                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs          15135104                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             22.514296                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       20447572500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.928988                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.999861                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.999861                       # Average percentage of cache occupancy
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.029708                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.029708                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.034789                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.034789                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15715.921135                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15715.921135                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47895.243884                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47895.243884                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16002.144802                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16002.144802                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 22495.058787                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 22495.058787                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14531.666096                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14531.666096                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 32388.888889                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 32388.888889                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25149.966532                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25149.966532                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23763.287744                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 23763.287744                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184779.665796                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184779.665796                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92374.753320                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92374.753320                       # average overall mshr uncacheable latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements          16891256                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.956016                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           444441322                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs          16891768                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             26.311119                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       13164566500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.956016                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.999914                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.999914                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          124                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          299                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           89                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          114                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          286                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          112                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         371779021                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        371779021                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst    340756209                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       340756209                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     340756209                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        340756209                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    340756209                       # number of overall hits
-system.cpu.icache.overall_hits::total       340756209                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst     15887482                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total      15887482                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst     15887482                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total       15887482                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst     15887482                       # number of overall misses
-system.cpu.icache.overall_misses::total      15887482                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 214918228873                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 214918228873                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 214918228873                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 214918228873                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 214918228873                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 214918228873                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    356643691                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    356643691                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    356643691                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    356643691                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    356643691                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    356643691                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.044547                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.044547                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.044547                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.044547                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.044547                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.044547                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13527.519897                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13527.519897                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13527.519897                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13527.519897                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13527.519897                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13527.519897                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        24649                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses         479012658                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        479012658                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst    444441322                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       444441322                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     444441322                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        444441322                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    444441322                       # number of overall hits
+system.cpu.icache.overall_hits::total       444441322                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst     17679342                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total      17679342                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst     17679342                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total       17679342                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst     17679342                       # number of overall misses
+system.cpu.icache.overall_misses::total      17679342                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 234300237389                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 234300237389                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 234300237389                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 234300237389                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 234300237389                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 234300237389                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    462120664                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    462120664                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    462120664                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    462120664                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    462120664                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    462120664                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.038257                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.038257                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.038257                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.038257                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.038257                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.038257                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13252.769101                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13252.769101                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13252.769101                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13252.769101                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13252.769101                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13252.769101                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        16371                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              1517                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              1212                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    16.248517                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    13.507426                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks     15134592                       # number of writebacks
-system.cpu.icache.writebacks::total          15134592                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst       752151                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total       752151                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst       752151                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total       752151                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst       752151                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total       752151                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst     15135331                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total     15135331                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst     15135331                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total     15135331                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst     15135331                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total     15135331                       # number of overall MSHR misses
+system.cpu.icache.writebacks::writebacks     16891256                       # number of writebacks
+system.cpu.icache.writebacks::total          16891256                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst       787348                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total       787348                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst       787348                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total       787348                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst       787348                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total       787348                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst     16891994                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total     16891994                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst     16891994                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total     16891994                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst     16891994                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total     16891994                       # number of overall MSHR misses
 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        21294                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.ReadReq_mshr_uncacheable::total        21294                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        21294                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses::total        21294                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192625378387                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 192625378387                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192625378387                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 192625378387                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192625378387                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 192625378387                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   2684938500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   2684938500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   2684938500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total   2684938500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.042438                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.042438                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.042438                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.042438                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.042438                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.042438                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12726.869230                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12726.869230                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12726.869230                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12726.869230                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12726.869230                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12726.869230                       # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126088.968724                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126088.968724                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126088.968724                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126088.968724                       # average overall mshr uncacheable latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements          1148622                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65301.900403                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           46289210                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1211379                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            38.211996                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       4512200500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 37189.560843                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   293.778433                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   476.562000                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  7800.369043                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 19541.630085                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.567468                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004483                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.007272                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.119024                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.298182                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.996428                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023          234                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        62523                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4          234                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           67                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          564                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2712                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5162                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54018                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.003571                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.954025                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        410396361                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       410396361                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       787478                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       297374                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1084852                       # number of ReadReq hits
-system.cpu.l2cache.WritebackDirty_hits::writebacks      7504086                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      7504086                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks     15131991                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total     15131991                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data         9360                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total         9360                       # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            4                       # number of SCUpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::total            4                       # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1568311                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1568311                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     15051780                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total     15051780                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6254855                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      6254855                       # number of ReadSharedReq hits
-system.cpu.l2cache.InvalidateReq_hits::cpu.data       727039                       # number of InvalidateReq hits
-system.cpu.l2cache.InvalidateReq_hits::total       727039                       # number of InvalidateReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker       787478                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker       297374                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst     15051780                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      7823166                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total        23959798                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker       787478                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker       297374                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst     15051780                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      7823166                       # number of overall hits
-system.cpu.l2cache.overall_hits::total       23959798                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         3559                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         3326                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         6885                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data        34185                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total        34185                       # number of UpgradeReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 210691534398                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 210691534398                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 210691534398                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 210691534398                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 210691534398                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 210691534398                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   1610722500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   1610722500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   1610722500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total   1610722500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.036553                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.036553                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.036553                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.036553                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.036553                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.036553                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12472.863440                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12472.863440                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12472.863440                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12472.863440                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12472.863440                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12472.863440                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75642.082277                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75642.082277                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75642.082277                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75642.082277                       # average overall mshr uncacheable latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.replacements          2372905                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65457.290128                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           58959202                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          2435994                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            24.203345                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle       2520974000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks  9397.889077                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   196.572797                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   228.214718                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  6628.882550                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 49005.730985                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.143400                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.002999                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.003482                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.101149                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.747768                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.998799                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023          222                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        62867                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4          222                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           36                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          376                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1017                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5588                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55850                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.003387                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.959274                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        505094110                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       505094110                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker      1274032                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       302472                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1576504                       # number of ReadReq hits
+system.cpu.l2cache.WritebackDirty_hits::writebacks     10319802                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total     10319802                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks     16888637                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total     16888637                       # number of WritebackClean hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data        38922                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total        38922                       # number of UpgradeReq hits
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+system.cpu.l2cache.SCUpgradeReq_hits::total            5                       # number of SCUpgradeReq hits
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+system.cpu.l2cache.ReadExReq_hits::total      1712070                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     16794801                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total     16794801                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      8925946                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      8925946                       # number of ReadSharedReq hits
+system.cpu.l2cache.InvalidateReq_hits::cpu.data       673558                       # number of InvalidateReq hits
+system.cpu.l2cache.InvalidateReq_hits::total       673558                       # number of InvalidateReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker      1274032                       # number of demand (read+write) hits
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 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            4                       # number of SCUpgradeReq misses
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+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.028090                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005741                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.142053                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.060788                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89750.598831                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 89243.765729                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 89519.578706                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 17958.680726                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 17958.680726                       # average UpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        47750                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        47750                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92895.029595                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92895.029595                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85598.588427                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85598.588427                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 90470.035629                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 90470.035629                       # average ReadSharedReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data     0.818507                       # average InvalidateReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::total     0.818507                       # average InvalidateReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89750.598831                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 89243.765729                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85598.588427                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92305.741758                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 91930.824377                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89750.598831                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 89243.765729                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85598.588427                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92305.741758                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 91930.824377                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks       962824                       # number of writebacks
-system.cpu.l2cache.writebacks::total           962824                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.dtb.walker            1                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
+system.cpu.l2cache.writebacks::writebacks      2095825                       # number of writebacks
+system.cpu.l2cache.writebacks::total          2095825                       # number of writebacks
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           21                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::total           21                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.dtb.walker            1                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.data           21                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           22                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.dtb.walker            1                       # number of overall MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           21                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data           21                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           22                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         3558                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         3326                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         6884                       # number of ReadReq MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            1                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total            1                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        34185                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total        34185                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.overall_mshr_hits::total           21                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker        10437                       # number of ReadReq MSHR misses
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+system.cpu.l2cache.ReadReq_mshr_misses::total        19179                       # number of ReadReq MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            3                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total            3                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         4078                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         4078                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            4                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            4                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       394921                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       394921                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        83338                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        83338                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       256994                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       256994                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       499544                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::total       499544                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         3558                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         3326                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        83338                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       651915                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       742137                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         3558                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         3326                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        83338                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       651915                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       742137                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data      1333352                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total      1333352                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        96984                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        96984                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       428004                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       428004                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       590099                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::total       590099                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker        10437                       # number of demand (read+write) MSHR misses
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+system.cpu.l2cache.overall_mshr_misses::total      1877519                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        21294                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33678                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total        54972                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        33696                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33696                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33692                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::total        54986                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        33703                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33703                       # number of WriteReq MSHR uncacheable
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        21294                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67374                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total        88668                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    456305510                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    429144000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    885449510                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   2325232000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   2325232000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       277500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       277500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  51081891916                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  51081891916                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst  10406063168                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total  10406063168                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  33266030305                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  33266030305                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  34915200500                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  34915200500                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    456305510                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    429144000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  10406063168                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  84347922221                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  95639434899                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    456305510                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    429144000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  10406063168                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  84347922221                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  95639434899                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   2418763500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5770936000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   8189699500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   2418763500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5770936000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   8189699500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.004498                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.011061                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.006306                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67395                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total        88689                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    832356501                       # number of ReadReq MSHR miss cycles
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1525105501                       # number of ReadReq MSHR miss cycles
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+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     77850000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       181500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       181500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 110528159195                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 110528159195                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   7331831049                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   7331831049                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  34442081593                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  34442081593                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  12207320002                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  12207320002                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    832356501                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    692749000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   7331831049                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 144970240788                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 153827177338                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    832356501                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    692749000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   7331831049                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 144970240788                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 153827177338                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   1344547500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5804287500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   7148835000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   1344547500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5804287500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   7148835000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.008126                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.028090                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.012019                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.785050                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.785050                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.500000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.201159                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.201159                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005506                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005506                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.039465                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.039465                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.407265                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.407265                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.004498                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.011061                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005506                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.076921                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.030044                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.004498                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.011061                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005506                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.076921                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.030044                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 128247.754356                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 129027.059531                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 128624.275131                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68019.072693                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68019.072693                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        69375                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        69375                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129347.114780                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129347.114780                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124865.765533                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124865.765533                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 129442.828646                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 129442.828646                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69894.144460                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69894.144460                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 128247.754356                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 129027.059531                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124865.765533                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 129384.846523                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128870.322998                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 128247.754356                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 129027.059531                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124865.765533                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129384.846523                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128870.322998                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.968724                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171356.256310                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148979.471367                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.968724                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85655.237926                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 92363.643028                       # average overall mshr uncacheable latency
-system.cpu.toL2Bus.snoop_filter.tot_requests     50407203                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests     25570213                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3413                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         2115                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2115                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.094837                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.094837                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.444444                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.444444                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.437822                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.437822                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005741                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005741                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.045756                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.045756                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.466977                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.466977                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.008126                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.028090                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005741                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.142052                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.060787                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.008126                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.028090                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005741                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.142052                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.060787                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 79750.551020                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 79243.765729                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 79519.552688                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19090.240314                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19090.240314                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        45375                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        45375                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82894.958867                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82894.958867                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75598.356935                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75598.356935                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80471.401186                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80471.401186                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20686.901693                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20686.901693                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 79750.551020                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 79243.765729                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75598.356935                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82306.041929                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81931.089559                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 79750.551020                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 79243.765729                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75598.356935                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82306.041929                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81931.089559                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63142.082277                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172274.946575                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 130011.912123                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63142.082277                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86123.414200                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 80605.655718                       # average overall mshr uncacheable latency
+system.cpu.toL2Bus.snoop_filter.tot_requests     62084255                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests     31529230                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3455                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         2096                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2096                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadReq        1618708                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      23266675                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         33696                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        33696                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      8573574                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean     15134592                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      2391693                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq        43548                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq            8                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp        43556                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1963232                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1963232                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq     15135331                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      6520715                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq      1333247                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateResp      1226583                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     45447628                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     29327152                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       726647                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1928826                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          77430253                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1937602080                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1022907422                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2405600                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6328296                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         2969243398                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     1852603                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic              72285944                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples     27912596                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.024958                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.155996                       # Request fanout histogram
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadReq        2242102                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      28488845                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         33703                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        33703                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty     12415627                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean     16891256                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      3619797                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq        43003                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq            9                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp        43012                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      3045422                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      3045422                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq     16891994                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      9356331                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq      1295806                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateResp      1263657                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     50717623                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     41210208                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       777423                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      3005376                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          95710630                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   2162455328                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1454268658                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2489712                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side     10275752                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         3629489450                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     2999840                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic             138927432                       # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples     35281285                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.026592                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.160887                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           27215961     97.50%     97.50% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             696635      2.50%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           34343098     97.34%     97.34% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             938187      2.66%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       27912596                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    48339894491                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       35281285                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    58941748976                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy      1459384                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy      1470395                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy   22733591738                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy   25369728010                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   13401353655                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   19308156079                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy     426266814                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy     466604190                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy    1138134788                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy    1721722349                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq                40293                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40293                       # Transaction distribution
+system.iobus.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.iobus.trans_dist::ReadReq                40300                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40300                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
 system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
@@ -1762,11 +1756,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230944                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230944                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230958                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230958                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353728                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353742                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
@@ -1781,16 +1775,16 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334208                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334208                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334264                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334264                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492128                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             41884500                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7492184                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             41887500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                11500                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               345000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               337000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer3.occupancy                 9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
@@ -1798,85 +1792,85 @@ system.iobus.reqLayer4.occupancy                 9500                       # La
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy                9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer14.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer15.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               14500                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               14000                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            25117000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            25106500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer24.occupancy            36500500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           567323274                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           568968673                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147704000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147718000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements               115453                       # number of replacements
-system.iocache.tags.tagsinuse               10.423128                       # Cycle average of tags in use
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.replacements               115465                       # number of replacements
+system.iocache.tags.tagsinuse               10.450543                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115469                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115481                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13098782503000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.544201                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.878927                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.221513                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.429933                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.651446                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13091229344000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     5.877255                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     4.573288                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.367328                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.285830                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.653159                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039605                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039605                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.tag_accesses              1039668                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039668                       # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8808                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8845                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8815                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8852                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide       115472                       # number of demand (read+write) misses
-system.iocache.demand_misses::total            115512                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide       115479                       # number of demand (read+write) misses
+system.iocache.demand_misses::total            115519                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide       115472                       # number of overall misses
-system.iocache.overall_misses::total           115512                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5076000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1670063987                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1675139987                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide       115479                       # number of overall misses
+system.iocache.overall_misses::total           115519                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5086000                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1629675592                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1634761592                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  13414774287                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  13414774287                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5427000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide  15084838274                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  15090265274                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5427000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide  15084838274                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  15090265274                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  12811525081                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  12811525081                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5437000                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide  14441200673                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  14446637673                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5437000                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide  14441200673                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total  14446637673                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8808                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8845                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8815                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8852                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide       115472                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total          115512                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide       115479                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total          115519                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide       115472                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total         115512                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide       115479                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total         115519                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -1890,53 +1884,53 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137189.189189                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 189607.627952                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 189388.353533                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 184875.279864                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 184677.089019                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125766.653107                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 125766.653107                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       135675                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 130636.329794                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 130638.074607                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       135675                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 130636.329794                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 130638.074607                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         33964                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120111.050411                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 120111.050411                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet       135925                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 125054.777691                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 125058.541651                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet       135925                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 125054.777691                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 125058.541651                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         32070                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3510                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3415                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.676353                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.390922                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.writebacks::writebacks          106630                       # number of writebacks
 system.iocache.writebacks::total               106630                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8808                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8845                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8815                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8852                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide       115472                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total       115512                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide       115479                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total       115519                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide       115472                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total       115512                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3226000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1229663987                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1232889987                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide       115479                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total       115519                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3236000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1188925592                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1192161592                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8076516803                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   8076516803                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3427000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   9306180790                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   9309607790                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3427000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   9306180790                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   9309607790                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7471582182                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   7471582182                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3437000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   8660507774                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   8663944774                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3437000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   8660507774                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   8663944774                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -1950,89 +1944,95 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87189.189189                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139607.627952                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 139388.353533                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134875.279864                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 134677.089019                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75719.238009                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75719.238009                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85675                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 80592.531436                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 80594.291416                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85675                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 80592.531436                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 80594.291416                       # average overall mshr miss latency
-system.membus.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq               54972                       # Transaction distribution
-system.membus.trans_dist::ReadResp             411033                       # Transaction distribution
-system.membus.trans_dist::WriteReq              33696                       # Transaction distribution
-system.membus.trans_dist::WriteResp             33696                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1069454                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           193565                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            34895                       # Transaction distribution
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70047.834152                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70047.834152                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85925                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 74996.386997                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 75000.171175                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85925                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 74996.386997                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 75000.171175                       # average overall mshr miss latency
+system.membus.snoop_filter.tot_requests       5074419                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests      2524015                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests         3002                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
+system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadReq               54986                       # Transaction distribution
+system.membus.trans_dist::ReadResp             608005                       # Transaction distribution
+system.membus.trans_dist::WriteReq              33703                       # Transaction distribution
+system.membus.trans_dist::WriteResp             33703                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      2202455                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           284620                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4643                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              4                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               8                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            394310                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           394310                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        356061                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        606112                       # Transaction distribution
+system.membus.trans_dist::ReadExReq           1332798                       # Transaction distribution
+system.membus.trans_dist::ReadExResp          1332798                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        553019                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        696755                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6858                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3212019                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3341639                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237917                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       237917                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                3579556                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6900                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      6767333                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      6896995                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237693                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       237693                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                7134688                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          420                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13716                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    109397260                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    109567230                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7269248                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7269248                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               116836478                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             2560                       # Total snoops (count)
-system.membus.snoopTraffic                     163328                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples           2743103                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13800                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    254577484                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    254747538                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7253696                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7253696                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               262001234                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             2809                       # Total snoops (count)
+system.membus.snoopTraffic                     179264                       # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples           2675908                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.013150                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.113918                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 2743103    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 2640719     98.68%     98.68% # Request fanout histogram
+system.membus.snoop_fanout::1                   35189      1.32%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2743103                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           103939500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             2675908                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           103923000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               32500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5573000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5620000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          7172212711                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy         14223305475                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         4075256665                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy        10050154677                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           44789891                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           44814659                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
 system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
 system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
 system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
 system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
 system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
@@ -2042,11 +2042,11 @@ system.realview.ethernet.descDMAReads               0                       # Nu
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
 system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth             151                       # Total Bandwidth (bits/s)
+system.realview.ethernet.totBandwidth             150                       # Total Bandwidth (bits/s)
 system.realview.ethernet.totPackets                 3                       # Total Packets
 system.realview.ethernet.totBytes                 966                       # Total Bytes
 system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth              151                       # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txBandwidth              150                       # Transmit Bandwidth (bits/s)
 system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
 system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
 system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
@@ -2075,30 +2075,30 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
 system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    16114                       # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce                    17131                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
index df40a85e7..7c01d248f 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
@@ -1,171 +1,171 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 47.384351                       # Number of seconds simulated
-sim_ticks                                47384351300000                       # Number of ticks simulated
-final_tick                               47384351300000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 47.383918                       # Number of seconds simulated
+sim_ticks                                47383917710000                       # Number of ticks simulated
+final_tick                               47383917710000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 183431                       # Simulator instruction rate (inst/s)
-host_op_rate                                   207694                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             7126665146                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 777076                       # Number of bytes of host memory used
-host_seconds                                  6648.88                       # Real time elapsed on the host
-sim_insts                                  1219610005                       # Number of instructions simulated
-sim_ops                                    1380933056                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 126839                       # Simulator instruction rate (inst/s)
+host_op_rate                                   149150                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6559041658                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 782584                       # Number of bytes of host memory used
+host_seconds                                  7224.21                       # Real time elapsed on the host
+sim_insts                                   916315151                       # Number of instructions simulated
+sim_ops                                    1077489368                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.dtb.walker       205248                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       202880                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          4270112                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         16788488                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher     21729728                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       123968                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker        83584                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          3109600                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         10061712                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher     12393536                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        438400                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             69407256                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      4270112                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      3109600                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         7379712                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     85545984                       # Number of bytes written to this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu0.dtb.walker       217728                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker       211200                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          4242016                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         16335944                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher     21100544                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker        95616                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker        61568                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          3171760                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          9979472                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher     12170752                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        426688                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             68013288                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      4242016                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      3171760                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         7413776                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     84160640                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          85566568                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         3207                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         3170                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             82673                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            262333                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       339527                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         1937                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         1306                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             48631                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            157227                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher       193649                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6850                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1100510                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1336656                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          84181224                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         3402                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         3300                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             82234                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            255262                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       329696                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         1494                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker          962                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             49603                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            155942                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher       190168                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6667                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1078730                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1315010                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1339230                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          4332                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          4282                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               90117                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              354304                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher       458584                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          2616                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          1764                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               65625                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              212343                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       261553                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             9252                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1464772                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          90117                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          65625                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             155742                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1805364                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1317584                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          4595                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          4457                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               89524                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              344757                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher       445310                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          2018                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          1299                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               66937                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              210609                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       256854                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             9005                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1435366                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          89524                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          66937                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             156462                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1776144                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data                434                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1805798                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1805364                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         4332                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         4282                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              90117                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             354739                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher       458584                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         2616                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         1764                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              65625                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             212343                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       261553                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            9252                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3270570                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1100510                       # Number of read requests accepted
-system.physmem.writeReqs                      1339230                       # Number of write requests accepted
-system.physmem.readBursts                     1100510                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1339230                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 70408640                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     24000                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  85564992                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  69407256                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               85566568                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      375                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2249                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bw_write::total                1776578                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1776144                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         4595                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         4457                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              89524                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             345191                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher       445310                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         2018                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         1299                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              66937                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             210609                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       256854                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            9005                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3211944                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1078730                       # Number of read requests accepted
+system.physmem.writeReqs                      1317584                       # Number of write requests accepted
+system.physmem.readBursts                     1078730                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1317584                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 69010688                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     28032                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  84179968                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  68013288                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               84181224                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      438                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               70416                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               75191                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               64063                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               69912                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               59812                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               69643                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               65430                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               68144                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               61950                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               89644                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              68037                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              70586                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              61163                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              71056                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              65094                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              69994                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               85481                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               90029                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               81966                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               85433                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               77921                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               84076                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               83054                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               85039                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               78873                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               84297                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              83224                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              86586                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              79852                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              85124                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              80745                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              85253                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               67696                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               73149                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               67549                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               71981                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               66956                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               73789                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               64889                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               66635                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               57075                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               82656                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              58467                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              69413                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              60741                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              63810                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              67156                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              66330                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               82175                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               87404                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               82364                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               86039                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               82832                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               88693                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               80795                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               83065                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               76149                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               79916                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              77037                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              82986                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              77147                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              80171                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              84038                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              84501                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                       51215                       # Number of times write queue was full causing retry
-system.physmem.totGap                    47384349786500                       # Total gap between requests
+system.physmem.numWrRetry                       50212                       # Number of times write queue was full causing retry
+system.physmem.totGap                    47383916196500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
-system.physmem.readPktSize::4                   21333                       # Read request sizes (log2)
+system.physmem.readPktSize::4                   21334                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1079152                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1057371                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1336656                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    480448                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    272774                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     88894                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     67384                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                     42690                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                     36411                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                     33268                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     30721                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     27820                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      7595                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     4180                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     2606                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     1628                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                     1243                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      684                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      590                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      501                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      390                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      173                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                      105                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                       17                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        8                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        4                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1315010                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    477824                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    264556                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     85571                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     63109                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                     41587                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                     35911                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                     32865                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                     30424                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                     27932                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      7543                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     3912                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                     2354                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                     1437                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                     1085                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      609                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      513                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      445                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      357                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                      146                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       93                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                       13                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        6                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
@@ -189,136 +189,136 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    24574                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    28512                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    38198                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    43791                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    48248                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    52275                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    57744                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    62191                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    67593                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    69901                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    75312                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    79272                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    77429                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    80341                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    90816                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    80863                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    73646                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    69003                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     5131                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     3743                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     2880                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     2292                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     1969                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     1733                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     1620                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     1427                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     1318                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     1452                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     1364                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     1312                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     1279                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     1419                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     1515                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     1588                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                     1785                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                     1829                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                     1988                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                     2100                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                     2366                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                     2471                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                     2894                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                     3089                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                     3468                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                     3580                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                     3839                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                     4719                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                     6200                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                    24545                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                   120342                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1069816                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      145.794462                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      98.799028                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     192.755385                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         712470     66.60%     66.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       211048     19.73%     86.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        55044      5.15%     91.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        23596      2.21%     93.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        18557      1.73%     95.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        10547      0.99%     96.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         7452      0.70%     97.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         5550      0.52%     97.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        25552      2.39%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1069816                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         62458                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        17.613853                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev       71.325725                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511           62454     99.99%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-1023            2      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                    22527                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    26520                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    36837                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    42274                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    46464                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    50322                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    56496                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    61138                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    66561                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    68608                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    74012                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    78194                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    76215                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    79218                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    90231                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    80845                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    75138                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    70175                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     5598                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     3927                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     2866                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                     2290                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                     1845                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                     1544                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                     1368                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                     1258                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                     1266                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                     1360                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                     1411                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                     1419                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                     1282                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                     1482                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                     1488                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                     1820                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                     1958                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                     2035                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                     2146                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                     2370                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                     2522                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                     2687                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                     2917                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                     2998                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                     2934                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                     3116                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                     3382                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                     4014                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                     5428                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                    24238                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                   118579                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples      1002120                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      152.866515                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     102.517170                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     198.697434                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         641919     64.06%     64.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       209293     20.89%     84.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        56817      5.67%     90.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        24891      2.48%     93.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        19538      1.95%     95.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        11144      1.11%     96.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         7510      0.75%     96.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         6154      0.61%     97.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        24854      2.48%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1002120                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         61846                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        17.434870                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev       71.484606                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511           61843    100.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::13824-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           62458                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         62458                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        21.405633                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.660061                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev      609.107080                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-4095          62456    100.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::45056-49151            1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           61846                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         61846                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        21.267535                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.561626                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev      606.950117                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-4095          61844    100.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40960-45055            1      0.00%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::143360-147455            1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           62458                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    48895390505                       # Total ticks spent queuing
-system.physmem.totMemAccLat               69522921755                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   5500675000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       44444.90                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total           61846                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    51075620081                       # Total ticks spent queuing
+system.physmem.totMemAccLat               71293595081                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   5391460000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       47367.15                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  63194.90                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.49                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.81                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.46                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.81                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  66117.15                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.46                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.78                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.44                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.78                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.22                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        26.21                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     830166                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    537104                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   75.46                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  40.17                       # Row buffer hit rate for writes
-system.physmem.avgGap                     19421885.03                       # Average gap between requests
-system.physmem.pageHitRate                      56.10                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 4087639080                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 2230358625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                4232326800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               4361033520                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3094915112640                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1166279241240                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           27407555547000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             31683661258905                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.652499                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   45594888254330                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1582267440000                       # Time in different power states
+system.physmem.avgRdQLen                         1.18                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        23.55                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     810741                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    580742                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   75.19                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  44.15                       # Row buffer hit rate for writes
+system.physmem.avgGap                     19773667.47                       # Average gap between requests
+system.physmem.pageHitRate                      58.13                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 3929423400                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 2144030625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                4310615400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               4363418160                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3094887141840                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1164748800645                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           27408641092500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             31683024522570                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.645104                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   45596671664426                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1582253140000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    207195159170                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    204992820574                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 4000169880                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 2182632375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                4348679400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               4302421920                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3094915112640                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1168435080135                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           27405664460250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             31683848556600                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.656452                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   45591701065782                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1582267440000                       # Time in different power states
+system.physmem_1.actEnergy                 3646603800                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1989714375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                4100054400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               4159803600                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3094887141840                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1159320938310                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           27413402375250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             31681506631575                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.613070                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   45604605403923                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1582253140000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    210382633218                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    197059081077                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
 system.realview.nvmem.bytes_read::cpu0.inst          368                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst          144                       # Number of bytes read from this memory
@@ -345,30 +345,30 @@ system.realview.nvmem.bw_total::cpu0.data            1                       # T
 system.realview.nvmem.bw_total::cpu1.inst            3                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total              12                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups              199183431                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted        140489040                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          7036065                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups           156342542                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               99990575                       # Number of BTB hits
+system.cpu0.branchPred.lookups              139955722                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         92576910                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          6767718                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            98409045                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               61922323                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            63.956089                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               20013017                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect            198399                       # Number of incorrect RAS predictions.
-system.cpu0.branchPred.indirectLookups        4618183                       # Number of indirect predictor lookups.
-system.cpu0.branchPred.indirectHits           2919648                       # Number of indirect target hits.
-system.cpu0.branchPred.indirectMisses         1698535                       # Number of indirect misses.
-system.cpu0.branchPredindirectMispredicted       412858                       # Number of mispredicted indirect branches.
+system.cpu0.branchPred.BTBHitPct            62.923406                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               19026711                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect            185987                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.indirectLookups        4326684                       # Number of indirect predictor lookups.
+system.cpu0.branchPred.indirectHits           2749366                       # Number of indirect target hits.
+system.cpu0.branchPred.indirectMisses         1577318                       # Number of indirect misses.
+system.cpu0.branchPredindirectMispredicted       397214                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -398,86 +398,86 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dtb.walker.walks                   607513                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               607513                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        13877                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        97395                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore       289192                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples       318321                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean  2219.643065                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev 12711.673990                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-65535       315923     99.25%     99.25% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::65536-131071         1786      0.56%     99.81% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::131072-196607          409      0.13%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::196608-262143          127      0.04%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::262144-327679           41      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::327680-393215           31      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::393216-458751            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::589824-655359            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       318321                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples       324666                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 20482.457356                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 17703.017560                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 16938.599592                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535       320665     98.77%     98.77% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071         2783      0.86%     99.62% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607          369      0.11%     99.74% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143          625      0.19%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679          139      0.04%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215           57      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.walker.walks                   611788                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               611788                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        13108                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        98298                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore       292807                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples       318981                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean  2428.828049                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev 13543.109769                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-65535       316274     99.15%     99.15% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::65536-131071         2036      0.64%     99.79% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::131072-196607          442      0.14%     99.93% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::196608-262143          138      0.04%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::262144-327679           53      0.02%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::327680-393215           29      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::393216-458751            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::458752-524287            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::524288-589823            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::589824-655359            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       318981                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples       326187                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 22022.583671                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 18838.451550                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 17664.426007                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535       321608     98.60%     98.60% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071         3320      1.02%     99.61% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607          429      0.13%     99.75% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143          611      0.19%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679          146      0.04%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215           45      0.01%     99.99% # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walkCompletionTime::393216-458751           21      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total       324666                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 513372677252                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     0.571567                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev     0.552695                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-1 512028975252     99.74%     99.74% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::2-3    726675000      0.14%     99.88% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-5    290458500      0.06%     99.94% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::6-7    129299000      0.03%     99.96% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-9    102361000      0.02%     99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::10-11     55725500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-13     16517000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::14-15     21785000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-17       858500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::18-19        22500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 513372677252                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        97395     87.53%     87.53% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M        13877     12.47%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total       111272                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       607513                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::524288-589823            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total       326187                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples 530119453936                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.586335                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.554664                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-1 528635854936     99.72%     99.72% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::2-3    807711000      0.15%     99.87% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-5    321496500      0.06%     99.93% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::6-7    138249500      0.03%     99.96% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-9    109943500      0.02%     99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::10-11     58618500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-13     20610000      0.00%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::14-15     26013000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-17       940000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::18-19        17000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 530119453936                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        98298     88.23%     88.23% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        13108     11.77%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total       111406                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       611788                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       607513                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       111272                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       611788                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       111406                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       111272                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       718785                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       111406                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       723194                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                   141538315                       # DTB read hits
-system.cpu0.dtb.read_misses                    437252                       # DTB read misses
-system.cpu0.dtb.write_hits                   86796370                       # DTB write hits
-system.cpu0.dtb.write_misses                   170261                       # DTB write misses
+system.cpu0.dtb.read_hits                   102674478                       # DTB read hits
+system.cpu0.dtb.read_misses                    445170                       # DTB read misses
+system.cpu0.dtb.write_hits                   82832935                       # DTB write hits
+system.cpu0.dtb.write_misses                   166618                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              44490                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                   1069                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   43183                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      271                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  6902                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid              44145                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                   1062                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   42795                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      479                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  7037                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    42288                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses               141975567                       # DTB read accesses
-system.cpu0.dtb.write_accesses               86966631                       # DTB write accesses
+system.cpu0.dtb.perms_faults                    40072                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses               103119648                       # DTB read accesses
+system.cpu0.dtb.write_accesses               82999553                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        228334685                       # DTB hits
-system.cpu0.dtb.misses                         607513                       # DTB misses
-system.cpu0.dtb.accesses                    228942198                       # DTB accesses
-system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.hits                        185507413                       # DTB hits
+system.cpu0.dtb.misses                         611788                       # DTB misses
+system.cpu0.dtb.accesses                    186119201                       # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -507,1194 +507,1182 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.cpu0.itb.walker.walks                    87943                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong                87943                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2         1130                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3        62851                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore        10253                       # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples        77690                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean  1458.353713                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev 10159.922633                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-32767        76707     98.73%     98.73% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-65535          405      0.52%     99.26% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::65536-98303          337      0.43%     99.69% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::98304-131071          198      0.25%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.cpu0.itb.walker.walks                    85546                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                85546                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2         1054                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        59782                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore        10366                       # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples        75180                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean  1322.160149                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev  9414.531253                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-32767        74314     98.85%     98.85% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-65535          448      0.60%     99.44% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::65536-98303          228      0.30%     99.75% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::98304-131071          153      0.20%     99.95% # Table walker wait (enqueue to first request) latency
 system.cpu0.itb.walker.walkWaitTime::131072-163839            9      0.01%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::163840-196607           14      0.02%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::196608-229375            9      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::163840-196607           10      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::196608-229375            6      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::229376-262143            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu0.itb.walker.walkWaitTime::262144-294911            5      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::294912-327679            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::327680-360447            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::360448-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        77690                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples        74234                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 26234.178409                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 23080.051735                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 21732.027543                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535        71871     96.82%     96.82% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071         1986      2.68%     99.49% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607          153      0.21%     99.70% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143          128      0.17%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679           62      0.08%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215           21      0.03%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751            9      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkWaitTime::294912-327679            4      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::360448-393215            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        75180                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        71202                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 26797.709334                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 23346.070270                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 22372.473032                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535        68772     96.59%     96.59% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071         2000      2.81%     99.40% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607          197      0.28%     99.67% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143          144      0.20%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679           55      0.08%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215           23      0.03%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751            7      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-524287            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total        74234                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples 410290287148                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     0.846605                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev     0.360675                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0    62979367364     15.35%     15.35% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1   347270506784     84.64%     99.99% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2       38246000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3        1931000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::4         236000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 410290287148                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        62851     98.23%     98.23% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M         1130      1.77%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        63981                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkCompletionTime::total        71202                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples 422744199036                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     0.876427                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev     0.329334                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0    52271860780     12.36%     12.36% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1   370441299256     87.63%     99.99% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2       29828500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3        1210500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 422744199036                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K        59782     98.27%     98.27% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M         1054      1.73%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        60836                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        87943                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        87943                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        85546                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        85546                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        63981                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        63981                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       151924                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   282848559                       # ITB inst hits
-system.cpu0.itb.inst_misses                     87943                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        60836                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        60836                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       146382                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   220474674                       # ITB inst hits
+system.cpu0.itb.inst_misses                     85546                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              44490                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                   1069                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   30949                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              44145                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                   1062                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   31037                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                   212727                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                   205838                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               282936502                       # ITB inst accesses
-system.cpu0.itb.hits                        282848559                       # DTB hits
-system.cpu0.itb.misses                          87943                       # DTB misses
-system.cpu0.itb.accesses                    282936502                       # DTB accesses
-system.cpu0.numPwrStateTransitions              28168                       # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples        14084                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean    3333377849.836978                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev   92382687873.308472                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::underflows         4020     28.54%     28.54% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10        10033     71.24%     99.78% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::5e+10-1e+11           12      0.09%     99.87% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11            2      0.01%     99.88% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11            1      0.01%     99.90% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11            1      0.01%     99.91% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::overflows           13      0.09%    100.00% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::max_value 6914082605000                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total          14084                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON   437057662896                       # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 46947293637104                       # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles                       874125395                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               220560220                       # ITB inst accesses
+system.cpu0.itb.hits                        220474674                       # DTB hits
+system.cpu0.itb.misses                          85546                       # DTB misses
+system.cpu0.itb.accesses                    220560220                       # DTB accesses
+system.cpu0.numPwrStateTransitions              10840                       # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples         5420                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean    8671662092.472324                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev   149203914828.202179                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows         3833     70.72%     70.72% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10         1557     28.73%     99.45% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::5e+10-1e+11           11      0.20%     99.65% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11            3      0.06%     99.70% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11            1      0.02%     99.72% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11            1      0.02%     99.74% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11            1      0.02%     99.76% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::overflows           13      0.24%    100.00% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::min_value          500                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::max_value 6993554617000                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total           5420                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON   383509168800                       # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 47000408541200                       # Cumulative time (in ticks) in various power states
+system.cpu0.numCycles                       767019929                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          92275983                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     768900237                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                  199183431                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches         122923240                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                    738928784                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles               15190816                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                   2037144                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles              294842                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles      6072240                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       792344                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles       839757                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                282635522                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes              1737700                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                  28623                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         848836502                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             1.034930                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            1.208968                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          88196996                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     619911097                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                  139955722                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          83698400                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                    636708825                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles               14589342                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                   2007819                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles              289070                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles      6017581                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       759490                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles       830550                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                220269194                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes              1684756                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                  27864                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         742105002                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.977120                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            1.219124                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0               416377385     49.05%     49.05% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1               176079063     20.74%     69.80% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                66732959      7.86%     77.66% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3               189647095     22.34%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0               394679215     53.18%     53.18% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1               135211877     18.22%     71.40% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                46727804      6.30%     77.70% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3               165486106     22.30%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           848836502                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.227866                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.879622                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles               110330106                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles            381856903                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                311429263                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles             39757521                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               5462709                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved            29836532                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred              2173523                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts             791623702                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts             24444549                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               5462709                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles               147675961                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               53914284                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles     258297798                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                313275075                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             70210675                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts             773227105                       # Number of instructions processed by rename
-system.cpu0.rename.SquashedInsts              6509157                       # Number of squashed instructions processed by rename
-system.cpu0.rename.ROBFullEvents             10689754                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents                377832                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                811571                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents              32991272                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.FullRegisterEvents           11799                       # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands          742885425                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups           1169549966                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       880889153                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups           700737                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps            682115784                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                60769635                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts          16576266                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts      14423738                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 79729853                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads           141637487                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           90242008                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          9692958                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         8374311                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                 749539213                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded           16620515                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                754385019                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued          2849937                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined       57154900                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     36998097                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        294454                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    848836502                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.888728                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.088535                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           742105002                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.182467                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.808207                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles               106471358                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles            362106065                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                229306920                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles             38969186                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               5251473                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved            19951761                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred              2082457                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts             641630797                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts             23347252                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               5251473                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles               142650653                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               53065481                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles     241402745                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                231558396                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles             68176254                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts             624076980                       # Number of instructions processed by rename
+system.cpu0.rename.SquashedInsts              6229632                       # Number of squashed instructions processed by rename
+system.cpu0.rename.ROBFullEvents             10704846                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents                385160                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                931811                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents              31501280                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.FullRegisterEvents           11804                       # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands          596222700                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            963956032                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups       736577059                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups           695179                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps            537389975                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                58832686                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts          16140854                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts      14103711                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 78118251                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads           102816112                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           86124751                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          9533509                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         8142362                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                 600960924                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded           16329392                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                605893488                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued          2751703                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined       55206879                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     35882934                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        285911                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    742105002                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.816453                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.065729                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0          442949824     52.18%     52.18% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1          161566736     19.03%     71.22% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2          148384909     17.48%     88.70% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3           87697049     10.33%     99.03% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            8232602      0.97%    100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5               5382      0.00%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0          411055814     55.39%     55.39% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1          139198751     18.76%     74.15% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2          116841261     15.74%     89.89% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3           67029634      9.03%     98.92% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            7974397      1.07%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5               5145      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      848836502                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      742105002                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu               74538342     48.88%     48.88% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                 62447      0.04%     48.92% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                  15099      0.01%     48.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     48.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     48.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     48.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     48.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     48.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     48.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     48.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     48.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     48.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     48.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     48.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     48.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     48.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     48.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     48.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     48.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     48.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     48.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     48.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     48.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     48.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     48.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               9      0.00%     48.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     48.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     48.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     48.93% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead              37581602     24.64%     73.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite             40298347     26.43%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu               62807824     45.43%     45.43% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                 65216      0.05%     45.48% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                  15839      0.01%     45.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     45.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     45.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     45.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     45.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     45.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     45.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     45.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     45.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     45.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     45.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     45.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     45.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     45.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     45.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     45.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     45.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     45.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     45.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     45.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     45.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     45.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     45.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc              32      0.00%     45.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     45.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     45.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead              36880846     26.68%     72.17% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite             38467267     27.83%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass               51      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu            519755806     68.90%     68.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult             1543884      0.20%     69.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                77211      0.01%     69.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                 64      0.00%     69.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     69.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     69.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     69.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     69.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     69.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   2      0.00%     69.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                1      0.00%     69.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   1      0.00%     69.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     69.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     69.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     69.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     69.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     69.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     69.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     69.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     69.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     69.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     69.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     69.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     69.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     69.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc         42719      0.01%     69.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     69.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     69.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead           144854124     19.20%     88.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           88111156     11.68%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass               25      0.00%      0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu            414236377     68.37%     68.37% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult             1540158      0.25%     68.62% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                80647      0.01%     68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  9      0.00%     68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   1      0.00%     68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc         41778      0.01%     68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead           105913797     17.48%     86.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           84080696     13.88%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total             754385019                       # Type of FU issued
-system.cpu0.iq.rate                          0.863017                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                  152495846                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.202146                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads        2511823586                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes        823027375                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses    736101219                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads            1128735                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes            443604                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       415332                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses             906176667                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                 704147                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads         2868207                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total             605893488                       # Type of FU issued
+system.cpu0.iq.rate                          0.789932                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                  138237024                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.228154                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads        2093764115                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes        672208466                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses    588253598                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads            1116590                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes            439713                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       411739                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses             743434871                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                 695616                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads         2774549                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads     13104832                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses        17724                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation       157642                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores      5794849                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads     12838296                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses        17783                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation       152412                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores      5562268                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads      2875718                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked      4918474                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads      2788433                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked      4754457                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               5462709                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                7926079                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles              1884320                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts          766295642                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewSquashCycles               5251473                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                7932610                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles              1687524                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts          617423509                       # Number of instructions dispatched to IQ
 system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts            141637487                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            90242008                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts          14144816                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 61216                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents              1749510                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents        157642                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect       2035907                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect      3235941                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts             5271848                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts            745963336                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts            141529970                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts          7821454                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewDispLoadInsts            102816112                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            86124751                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts          13854081                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 62183                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents              1552208                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents        152412                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect       1974984                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect      3105212                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts             5080196                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts            597824194                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts            102668745                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts          7465093                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       135914                       # number of nop insts executed
-system.cpu0.iew.exec_refs                   228324326                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches               170531782                       # Number of branches executed
-system.cpu0.iew.exec_stores                  86794356                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.853383                       # Inst execution rate
-system.cpu0.iew.wb_sent                     737330155                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                    736516551                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                351214969                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                595098705                       # num instructions consuming a value
-system.cpu0.iew.wb_rate                      0.842575                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.590179                       # average fanout of values written-back
-system.cpu0.commit.commitSquashedInsts       49835507                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls       16326061                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts          4903366                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    839368834                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.844688                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.533259                       # Number of insts commited each cycle
+system.cpu0.iew.exec_nop                       133193                       # number of nop insts executed
+system.cpu0.iew.exec_refs                   185500111                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches               112433305                       # Number of branches executed
+system.cpu0.iew.exec_stores                  82831366                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.779412                       # Inst execution rate
+system.cpu0.iew.wb_sent                     589443856                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                    588665337                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                287005457                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                470602155                       # num instructions consuming a value
+system.cpu0.iew.wb_rate                      0.767471                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.609869                       # average fanout of values written-back
+system.cpu0.commit.commitSquashedInsts       48230515                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls       16043481                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts          4724520                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    732949405                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.766879                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.569816                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0    512658006     61.08%     61.08% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1    158759517     18.91%     79.99% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2     92536082     11.02%     91.02% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3     27862473      3.32%     94.33% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4     13576189      1.62%     95.95% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5      9358920      1.11%     97.07% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      6289735      0.75%     97.82% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7      3875341      0.46%     98.28% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8     14452571      1.72%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0    487135616     66.46%     66.46% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1    127506386     17.40%     83.86% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2     54345658      7.41%     91.27% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3     18167389      2.48%     93.75% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4     13030534      1.78%     95.53% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5      9013680      1.23%     96.76% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      6080548      0.83%     97.59% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7      3647046      0.50%     98.09% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8     14022548      1.91%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    839368834                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts           622433451                       # Number of instructions committed
-system.cpu0.commit.committedOps             709004821                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    732949405                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts           479057822                       # Number of instructions committed
+system.cpu0.commit.committedOps             562083399                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                     212979813                       # Number of memory references committed
-system.cpu0.commit.loads                    128532654                       # Number of loads committed
-system.cpu0.commit.membars                    3921678                       # Number of memory barriers committed
-system.cpu0.commit.branches                 164749224                       # Number of branches committed
-system.cpu0.commit.fp_insts                    407380                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                634275437                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls            14942203                       # Number of function calls committed.
+system.cpu0.commit.refs                     170540284                       # Number of memory references committed
+system.cpu0.commit.loads                     89977801                       # Number of loads committed
+system.cpu0.commit.membars                    3918882                       # Number of memory barriers committed
+system.cpu0.commit.branches                 106864519                       # Number of branches committed
+system.cpu0.commit.fp_insts                    404083                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                515735338                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls            14196925                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu       494636379     69.76%     69.76% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult        1291078      0.18%     69.95% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv           60530      0.01%     69.96% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.96% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.96% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.96% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.96% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.96% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.96% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.96% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.96% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.96% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.96% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.96% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.96% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.96% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.96% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.96% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.96% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.96% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     69.96% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.96% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     69.96% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     69.96% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.96% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc        37021      0.01%     69.96% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.96% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.96% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.96% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead      128532654     18.13%     88.09% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      84447159     11.91%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu       390151246     69.41%     69.41% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult        1292004      0.23%     69.64% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv           63609      0.01%     69.65% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.65% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.65% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.65% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.65% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.65% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.65% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.65% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.65% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.65% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.65% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.65% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.65% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.65% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.65% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.65% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.65% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.65% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     69.65% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.65% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     69.65% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     69.65% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.65% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc        36256      0.01%     69.66% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.66% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.66% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.66% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       89977801     16.01%     85.67% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      80562483     14.33%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total        709004821                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events             14452571                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                  1579278211                       # The number of ROB reads
-system.cpu0.rob.rob_writes                 1527109253                       # The number of ROB writes
-system.cpu0.timesIdled                        1033857                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                       25288893                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                 93894577230                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                  622433451                       # Number of Instructions Simulated
-system.cpu0.committedOps                    709004821                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.404368                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.404368                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.712064                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.712064                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               848778973                       # number of integer regfile reads
-system.cpu0.int_regfile_writes              506977822                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                   685984                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                  317032                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                188384037                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes               189031095                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads             1602344785                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes              16401028                       # number of misc regfile writes
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements          6409966                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          480.619482                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          199938758                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          6410478                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            31.189368                       # Average number of references to valid blocks.
+system.cpu0.commit.op_class_0::total        562083399                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events             14022548                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                  1325013729                       # The number of ROB reads
+system.cpu0.rob.rob_writes                 1229746140                       # The number of ROB writes
+system.cpu0.timesIdled                         998783                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                       24914927                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                 94000815527                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                  479057822                       # Number of Instructions Simulated
+system.cpu0.committedOps                    562083399                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.601101                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.601101                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.624570                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.624570                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads               705670279                       # number of integer regfile reads
+system.cpu0.int_regfile_writes              419695299                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                   680997                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                  310212                       # number of floating regfile writes
+system.cpu0.cc_regfile_reads                130338984                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes               131056521                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads             1328403158                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes              16107336                       # number of misc regfile writes
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.tags.replacements          6279329                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          481.718631                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          157880144                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          6279840                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            25.140791                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle       1908955000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   480.619482                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.938710                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.938710                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          100                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          395                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        439216738                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       439216738                       # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data    121629785                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total      121629785                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     73254039                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      73254039                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       225954                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       225954                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       195110                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       195110                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1865486                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      1865486                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1919454                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      1919454                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    195078934                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       195078934                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    195304888                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      195304888                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      7140435                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      7140435                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      8024708                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      8024708                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       776369                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       776369                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       838591                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total       838591                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       289464                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       289464                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data       195968                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total       195968                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data     16003734                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total      16003734                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data     16780103                       # number of overall misses
-system.cpu0.dcache.overall_misses::total     16780103                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 108528058000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 108528058000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 153779451872                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 153779451872                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  31763636892                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total  31763636892                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4317295000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   4317295000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4927286000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total   4927286000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      3123500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total      3123500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 294071146764                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 294071146764                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 294071146764                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 294071146764                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data    128770220                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total    128770220                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     81278747                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     81278747                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data      1002323                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total      1002323                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data      1033701                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total      1033701                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2154950                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      2154950                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2115422                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      2115422                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    211082668                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    211082668                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    212084991                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    212084991                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.055451                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.055451                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.098731                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.098731                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.774570                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.774570                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.811251                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.811251                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.134325                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.134325                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.092638                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.092638                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.075817                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.075817                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.079120                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.079120                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15199.082129                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 15199.082129                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19163.245799                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 19163.245799                       # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 37877.388252                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 37877.388252                       # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14914.790786                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14914.790786                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25143.319317                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25143.319317                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   481.718631                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.940857                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.940857                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          218                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          236                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           57                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses        354237308                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       354237308                       # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.ReadReq_hits::cpu0.data     83229187                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       83229187                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     69700757                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      69700757                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       201759                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       201759                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       148045                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       148045                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1863463                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      1863463                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1922512                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      1922512                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    153077989                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       153077989                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    153279748                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      153279748                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      7047364                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      7047364                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      7798246                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      7798246                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       750513                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       750513                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       796040                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total       796040                       # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       285990                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       285990                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data       189707                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total       189707                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data     15641650                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total      15641650                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data     16392163                       # number of overall misses
+system.cpu0.dcache.overall_misses::total     16392163                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 106587069500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 106587069500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 149276619912                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 149276619912                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  30060531759                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total  30060531759                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4170219500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   4170219500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4536657500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total   4536657500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      2221500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total      2221500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 285924221171                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 285924221171                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 285924221171                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 285924221171                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     90276551                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     90276551                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     77499003                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     77499003                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       952272                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       952272                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       944085                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total       944085                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2149453                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      2149453                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2112219                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      2112219                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    168719639                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    168719639                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    169671911                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    169671911                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.078064                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.078064                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.100624                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.100624                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.788129                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.788129                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.843187                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.843187                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.133052                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.133052                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.089814                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.089814                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.092708                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.092708                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.096611                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.096611                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15124.388282                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 15124.388282                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19142.332765                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 19142.332765                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 37762.589517                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 37762.589517                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14581.696912                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14581.696912                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23914.022677                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23914.022677                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 18375.158370                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 18375.158370                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17524.990566                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 17524.990566                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs      9668545                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets     23532840                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs           779892                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets         794197                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    12.397287                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    29.630986                       # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks      6410042                       # number of writebacks
-system.cpu0.dcache.writebacks::total          6410042                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3690786                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total      3690786                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      6446005                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      6446005                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         4347                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::total         4347                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       149571                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total       149571                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data     10141138                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total     10141138                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data     10141138                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total     10141138                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3449649                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      3449649                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1578703                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1578703                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       769355                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       769355                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       834244                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total       834244                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       139893                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       139893                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       195965                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total       195965                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      5862596                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      5862596                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      6631951                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      6631951                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        31285                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31285                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        30958                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        30958                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        62243                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        62243                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  50416416500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  50416416500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  33875543231                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  33875543231                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  17245260500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  17245260500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  30759768392                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  30759768392                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1918237000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1918237000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   4731380000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   4731380000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      3064500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      3064500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 115051728123                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 115051728123                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 132296988623                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 132296988623                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6062914000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6062914000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6062914000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6062914000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.026789                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.026789                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019423                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019423                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.767572                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.767572                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.807046                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.807046                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.064917                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.064917                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.092636                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.092636                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.027774                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.027774                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.031270                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.031270                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14614.940969                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14614.940969                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21457.831670                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21457.831670                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22415.218592                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22415.218592                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 36871.428973                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 36871.428973                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13712.172875                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13712.172875                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24144.005307                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24144.005307                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 18279.671337                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 18279.671337                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17442.739019                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 17442.739019                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs      9136124                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets     22955799                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs           744485                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets         773832                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    12.271737                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    29.665094                       # average number of cycles each access was blocked
+system.cpu0.dcache.writebacks::writebacks      6279393                       # number of writebacks
+system.cpu0.dcache.writebacks::total          6279393                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3627313                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total      3627313                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      6268862                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      6268862                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         4039                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::total         4039                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       145852                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total       145852                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      9900214                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      9900214                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      9900214                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      9900214                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3420051                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      3420051                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1529384                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1529384                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       743716                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       743716                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       792001                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total       792001                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       140138                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       140138                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       189707                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total       189707                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      5741436                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      5741436                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      6485152                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      6485152                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        17085                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        17085                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        18834                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        18834                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        35919                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        35919                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  49260241500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  49260241500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  32250000948                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  32250000948                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  16897998500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  16897998500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  29124405259                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  29124405259                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1866604500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1866604500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   4347004500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   4347004500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      2167500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2167500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 110634647707                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 110634647707                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 127532646207                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 127532646207                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3215151000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3215151000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3215151000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3215151000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.037884                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.037884                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019734                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019734                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.780991                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.780991                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.838909                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.838909                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.065197                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.065197                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.089814                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.089814                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.034029                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.034029                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.038222                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.038222                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14403.364599                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14403.364599                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21086.921890                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21086.921890                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22721.036659                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22721.036659                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 36773.192533                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 36773.192533                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13319.759808                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13319.759808                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22914.307327                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22914.307327                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19624.706891                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19624.706891                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19948.426733                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19948.426733                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193796.196260                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193796.196260                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 97407.162251                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 97407.162251                       # average overall mshr uncacheable latency
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements          6234341                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.962382                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          276007197                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          6234853                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            44.268437                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      12884658000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.962382                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999927                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999927                       # Average percentage of cache occupancy
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19269.508135                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19269.508135                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19665.328771                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19665.328771                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188185.601405                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 188185.601405                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 89511.150088                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 89511.150088                       # average overall mshr uncacheable latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.tags.replacements          5960489                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.962298                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          213927686                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          5961001                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            35.887880                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      13033031000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.962298                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999926                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999926                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          106                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          339                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           67                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          166                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          342                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        571449747                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       571449747                       # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst    276007197                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      276007197                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    276007197                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       276007197                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    276007197                       # number of overall hits
-system.cpu0.icache.overall_hits::total      276007197                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      6600102                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      6600102                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      6600102                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       6600102                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      6600102                       # number of overall misses
-system.cpu0.icache.overall_misses::total      6600102                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  71550800576                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  71550800576                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  71550800576                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  71550800576                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  71550800576                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  71550800576                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    282607299                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    282607299                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    282607299                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    282607299                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    282607299                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    282607299                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.023354                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.023354                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.023354                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.023354                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.023354                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.023354                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10840.862850                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 10840.862850                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10840.862850                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 10840.862850                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10840.862850                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 10840.862850                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs     10420482                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets         1138                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs           752268                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets             11                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    13.852087                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets   103.454545                       # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks      6234341                       # number of writebacks
-system.cpu0.icache.writebacks::total          6234341                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       364953                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total       364953                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst       364953                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total       364953                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst       364953                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total       364953                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6235149                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      6235149                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      6235149                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      6235149                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      6235149                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      6235149                       # number of overall MSHR misses
+system.cpu0.icache.tags.tag_accesses        446443685                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       446443685                       # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.ReadReq_hits::cpu0.inst    213927686                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      213927686                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    213927686                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       213927686                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    213927686                       # number of overall hits
+system.cpu0.icache.overall_hits::total      213927686                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      6313628                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      6313628                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      6313628                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       6313628                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      6313628                       # number of overall misses
+system.cpu0.icache.overall_misses::total      6313628                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  68941695345                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  68941695345                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  68941695345                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  68941695345                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  68941695345                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  68941695345                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    220241314                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    220241314                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    220241314                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    220241314                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    220241314                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    220241314                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.028667                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.028667                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.028667                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.028667                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.028667                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.028667                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10919.505448                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 10919.505448                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10919.505448                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 10919.505448                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10919.505448                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 10919.505448                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs     10186888                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets          465                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs           736848                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets              9                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    13.824952                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets    51.666667                       # average number of cycles each access was blocked
+system.cpu0.icache.writebacks::writebacks      5960489                       # number of writebacks
+system.cpu0.icache.writebacks::total          5960489                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       352571                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total       352571                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst       352571                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total       352571                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst       352571                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total       352571                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      5961057                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      5961057                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      5961057                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      5961057                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      5961057                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      5961057                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        21293                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total        21293                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        21293                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total        21293                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  64720811973                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  64720811973                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  64720811973                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  64720811973                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  64720811973                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  64720811973                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  62354110053                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  62354110053                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  62354110053                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  62354110053                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  62354110053                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  62354110053                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1885677498                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   1885677498                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1885677498                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total   1885677498                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.022063                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.022063                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.022063                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.022063                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.022063                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.022063                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10379.994443                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10379.994443                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10379.994443                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 10379.994443                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10379.994443                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 10379.994443                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.027066                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.027066                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.027066                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.027066                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.027066                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.027066                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10460.243888                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10460.243888                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10460.243888                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 10460.243888                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10460.243888                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 10460.243888                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88558.563753                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88558.563753                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      8818791                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      8829534                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit         9675                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      8592940                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      8600926                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit         7220                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage      1134314                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.tags.replacements         2939155                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16147.226336                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs          18219506                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs         2955258                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            6.165115                       # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle      2212473000                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 15244.220202                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    58.043386                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    62.165258                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data     0.000002                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   782.797489                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.930433                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003543                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.003794                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.000000                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.047778                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.985548                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1151                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023           81                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14871                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           14                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          189                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          576                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          372                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            2                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           48                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           14                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           17                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          128                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1385                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         6005                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         4408                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2945                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.070251                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.004944                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.907654                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses       433411639                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses      433411639                       # Number of data accesses
-system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       616680                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       198735                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total        815415                       # number of ReadReq hits
-system.cpu0.l2cache.WritebackDirty_hits::writebacks      4206029                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackDirty_hits::total      4206029                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackClean_hits::writebacks      8435953                       # number of WritebackClean hits
-system.cpu0.l2cache.WritebackClean_hits::total      8435953                       # number of WritebackClean hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data          888                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total          888                       # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data            2                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::total            2                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data      1016467                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total      1016467                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      5621992                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total      5621992                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      3255070                       # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total      3255070                       # number of ReadSharedReq hits
-system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       189931                       # number of InvalidateReq hits
-system.cpu0.l2cache.InvalidateReq_hits::total       189931                       # number of InvalidateReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       616680                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker       198735                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      5621992                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data      4271537                       # number of demand (read+write) hits
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-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       616680                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker       198735                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      5621992                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data      4271537                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total      10708944                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        13303                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker        10046                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total        23349                       # number of ReadReq misses
-system.cpu0.l2cache.WritebackDirty_misses::writebacks            5                       # number of WritebackDirty misses
-system.cpu0.l2cache.WritebackDirty_misses::total            5                       # number of WritebackDirty misses
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-system.cpu0.l2cache.WritebackClean_misses::total            1                       # number of WritebackClean misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       270883                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total       270883                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       195959                       # number of SCUpgradeReq misses
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-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            4                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::total            4                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data       300699                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total       300699                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       612692                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::total       612692                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data      1101459                       # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total      1101459                       # number of ReadSharedReq misses
-system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       642386                       # number of InvalidateReq misses
-system.cpu0.l2cache.InvalidateReq_misses::total       642386                       # number of InvalidateReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        13303                       # number of demand (read+write) misses
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-system.cpu0.l2cache.demand_misses::cpu0.inst       612692                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data      1402158                       # number of demand (read+write) misses
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-system.cpu0.l2cache.overall_misses::cpu0.inst       612692                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data      1402158                       # number of overall misses
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-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    571435000                       # number of ReadReq miss cycles
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-system.cpu0.l2cache.ReadReq_miss_latency::total   1050080000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   2108781500                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total   2108781500                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   1542924500                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   1542924500                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      2975499                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      2975499                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  16979785000                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total  16979785000                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  21306863000                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::total  21306863000                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  41322461986                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::total  41322461986                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data    313374000                       # number of InvalidateReq miss cycles
-system.cpu0.l2cache.InvalidateReq_miss_latency::total    313374000                       # number of InvalidateReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    571435000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    478645000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst  21306863000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data  58302246986                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total  80659189986                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    571435000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    478645000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst  21306863000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data  58302246986                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total  80659189986                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       629983                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       208781                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total       838764                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::writebacks      4206034                       # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::total      4206034                       # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::writebacks      8435954                       # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::total      8435954                       # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       271771                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total       271771                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       195961                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total       195961                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            4                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            4                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1317166                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total      1317166                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      6234684                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::total      6234684                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      4356529                       # number of ReadSharedReq accesses(hits+misses)
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-system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       832317                       # number of InvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.InvalidateReq_accesses::total       832317                       # number of InvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       629983                       # number of demand (read+write) accesses
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-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       629983                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       208781                       # number of overall (read+write) accesses
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-system.cpu0.l2cache.overall_accesses::cpu0.data      5673695                       # number of overall (read+write) accesses
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-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.021116                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.048117                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.027837                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks     0.000001                       # miss rate for WritebackDirty accesses
-system.cpu0.l2cache.WritebackDirty_miss_rate::total     0.000001                       # miss rate for WritebackDirty accesses
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+system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.cpu0.l2cache.tags.replacements         2719287                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       15847.951353                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs          10783985                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs         2734787                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            3.943263                       # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.warmup_cycle      2212469000                       # Cycle when the warmup percentage was hit.
+system.cpu0.l2cache.tags.occ_blocks::writebacks 15472.818870                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    33.262850                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    18.351912                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   323.517722                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.944386                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.002030                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.001120                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.019746                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.967282                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022          300                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023          111                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15089                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::0            1                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1            4                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2           95                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3           82                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          118                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::0            1                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::1           22                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           45                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           12                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           31                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          388                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         2056                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         7291                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         3067                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2287                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.018311                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.006775                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.920959                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses       426577615                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses      426577615                       # Number of data accesses
+system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       609078                       # number of ReadReq hits
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+system.cpu0.l2cache.ReadReq_hits::total        796000                       # number of ReadReq hits
+system.cpu0.l2cache.WritebackDirty_hits::writebacks      4110828                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackDirty_hits::total      4110828                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackClean_hits::writebacks      8127250                       # number of WritebackClean hits
+system.cpu0.l2cache.WritebackClean_hits::total      8127250                       # number of WritebackClean hits
+system.cpu0.l2cache.UpgradeReq_hits::cpu0.data           41                       # number of UpgradeReq hits
+system.cpu0.l2cache.UpgradeReq_hits::total           41                       # number of UpgradeReq hits
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+system.cpu0.l2cache.InvalidateReq_hits::total       179546                       # number of InvalidateReq hits
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+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       259915                       # number of UpgradeReq misses
+system.cpu0.l2cache.UpgradeReq_misses::total       259915                       # number of UpgradeReq misses
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+system.cpu0.l2cache.SCUpgradeReq_misses::total       189699                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            3                       # number of SCUpgradeFailReq misses
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+system.cpu0.l2cache.ReadCleanReq_misses::total       595762                       # number of ReadCleanReq misses
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+system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       610539                       # number of InvalidateReq misses
+system.cpu0.l2cache.InvalidateReq_misses::total       610539                       # number of InvalidateReq misses
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+system.cpu0.l2cache.overall_misses::cpu0.itb.walker        12082                       # number of overall misses
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+system.cpu0.l2cache.overall_misses::cpu0.data      1338057                       # number of overall misses
+system.cpu0.l2cache.overall_misses::total      1969568                       # number of overall misses
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    824553000                       # number of ReadReq miss cycles
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+system.cpu0.l2cache.ReadReq_miss_latency::total   1358923500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    956036000                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::total    956036000                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    288541500                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    288541500                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      2086500                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      2086500                       # number of SCUpgradeFailReq miss cycles
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+system.cpu0.l2cache.ReadExReq_miss_latency::total  16444485496                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  20913606500                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::total  20913606500                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  39888753486                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::total  39888753486                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data    293901000                       # number of InvalidateReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::total    293901000                       # number of InvalidateReq miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    824553000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    534370500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.inst  20913606500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.data  56333238982                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::total  78605768982                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    824553000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    534370500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst  20913606500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.data  56333238982                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::total  78605768982                       # number of overall miss cycles
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       632745                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       199004                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total       831749                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::writebacks      4110828                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::total      4110828                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::writebacks      8127252                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::total      8127252                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       259956                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total       259956                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       189704                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total       189704                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            3                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            3                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1278423                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total      1278423                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      5961024                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::total      5961024                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      4301636                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::total      4301636                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       790085                       # number of InvalidateReq accesses(hits+misses)
+system.cpu0.l2cache.InvalidateReq_accesses::total       790085                       # number of InvalidateReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       632745                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       199004                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.inst      5961024                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.data      5580059                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::total     12372832                       # number of demand (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       632745                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       199004                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst      5961024                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data      5580059                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total     12372832                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.037404                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.060712                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.042981                       # miss rate for ReadReq accesses
 system.cpu0.l2cache.WritebackClean_miss_rate::writebacks     0.000000                       # miss rate for WritebackClean accesses
 system.cpu0.l2cache.WritebackClean_miss_rate::total     0.000000                       # miss rate for WritebackClean accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.996733                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.996733                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.999990                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.999990                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.999842                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.999842                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.999974                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.999974                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.228292                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.228292                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.098272                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.098272                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.252829                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.252829                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.771804                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.771804                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.021116                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.048117                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.098272                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.247133                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.159895                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.021116                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.048117                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.098272                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.247133                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.159895                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 42955.348418                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 47645.331475                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 44973.232258                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  7784.842533                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  7784.842533                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  7873.710827                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  7873.710827                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 743874.750000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 743874.750000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 56467.713561                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 56467.713561                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 34775.813949                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 34775.813949                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 37516.114523                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 37516.114523                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data   487.828191                       # average InvalidateReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total   487.828191                       # average InvalidateReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 42955.348418                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 47645.331475                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34775.813949                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 41580.368964                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 39573.756040                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 42955.348418                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 47645.331475                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34775.813949                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 41580.368964                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 39573.756040                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs          834                       # number of cycles access was blocked
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.224481                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.224481                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.099943                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.099943                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.244343                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.244343                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.772751                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.772751                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.037404                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.060712                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.099943                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.239793                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.159185                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.037404                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.060712                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.099943                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.239793                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.159185                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34839.776905                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 44228.645920                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 38012.909452                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  3678.264048                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  3678.264048                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  1521.049136                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  1521.049136                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       695500                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       695500                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 57301.452690                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 57301.452690                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 35103.961817                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 35103.961817                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 37950.435017                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 37950.435017                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data   481.379568                       # average InvalidateReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total   481.379568                       # average InvalidateReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34839.776905                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 44228.645920                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 35103.961817                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42100.776710                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 39910.157447                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34839.776905                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 44228.645920                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 35103.961817                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42100.776710                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 39910.157447                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs         1132                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs              18                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs              30                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    46.333333                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    37.733333                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.l2cache.unused_prefetches           51227                       # number of HardPF blocks evicted w/o reference
-system.cpu0.l2cache.writebacks::writebacks      1850658                       # number of writebacks
-system.cpu0.l2cache.writebacks::total         1850658                       # number of writebacks
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            4                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker            8                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::total           12                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data        18696                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total        18696                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst            3                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::total            3                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data         5802                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total         5802                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data           11                       # number of InvalidateReq MSHR hits
-system.cpu0.l2cache.InvalidateReq_mshr_hits::total           11                       # number of InvalidateReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            4                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker            8                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst            3                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data        24498                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total        24513                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker            4                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker            8                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.inst            3                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data        24498                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total        24513                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        13299                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker        10038                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total        23337                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks            5                       # number of WritebackDirty MSHR misses
-system.cpu0.l2cache.WritebackDirty_mshr_misses::total            5                       # number of WritebackDirty MSHR misses
-system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks            1                       # number of WritebackClean MSHR misses
-system.cpu0.l2cache.WritebackClean_mshr_misses::total            1                       # number of WritebackClean MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       927770                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       927770                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       270883                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total       270883                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       195959                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       195959                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            4                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            4                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       282003                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total       282003                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       612689                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       612689                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data      1095657                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total      1095657                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       642375                       # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::total       642375                       # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        13299                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker        10038                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       612689                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1377660                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total      2013686                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        13299                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker        10038                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       612689                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1377660                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       927770                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total      2941456                       # number of overall MSHR misses
+system.cpu0.l2cache.unused_prefetches           48307                       # number of HardPF blocks evicted w/o reference
+system.cpu0.l2cache.writebacks::writebacks      1757363                       # number of writebacks
+system.cpu0.l2cache.writebacks::total         1757363                       # number of writebacks
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker          134                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker          356                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_hits::total          490                       # number of ReadReq MSHR hits
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+system.cpu0.l2cache.ReadExReq_mshr_hits::total        18633                       # number of ReadExReq MSHR hits
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+system.cpu0.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data         5210                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::total         5210                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data            3                       # number of InvalidateReq MSHR hits
+system.cpu0.l2cache.InvalidateReq_mshr_hits::total            3                       # number of InvalidateReq MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker          134                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker          356                       # number of demand (read+write) MSHR hits
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+system.cpu0.l2cache.demand_mshr_hits::cpu0.data        23843                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::total        24334                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker          134                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker          356                       # number of overall MSHR hits
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+system.cpu0.l2cache.overall_mshr_hits::cpu0.data        23843                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::total        24334                       # number of overall MSHR hits
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+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker        11726                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::total        35259                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks            2                       # number of WritebackClean MSHR misses
+system.cpu0.l2cache.WritebackClean_mshr_misses::total            2                       # number of WritebackClean MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       887638                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::total       887638                       # number of HardPFReq MSHR misses
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+system.cpu0.l2cache.UpgradeReq_mshr_misses::total       259915                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       189699                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       189699                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            3                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            3                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       268349                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::total       268349                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       595761                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       595761                       # number of ReadCleanReq MSHR misses
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+system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       610536                       # number of InvalidateReq MSHR misses
+system.cpu0.l2cache.InvalidateReq_mshr_misses::total       610536                       # number of InvalidateReq MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        23533                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker        11726                       # number of demand (read+write) MSHR misses
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+system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1314214                       # number of demand (read+write) MSHR misses
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+system.cpu0.l2cache.overall_mshr_misses::total      2832872                       # number of overall MSHR misses
 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        21293                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        31285                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        52578                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        30958                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        30958                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        17085                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        38378                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        18834                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        18834                       # number of WriteReq MSHR uncacheable
 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        21293                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        62243                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        83536                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    491572000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    418271000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    909843000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  52503366783                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  52503366783                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   5568283996                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   5568283996                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   3258361996                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   3258361996                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      2621499                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2621499                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  12639099000                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  12639099000                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  17630608000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  17630608000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  34375466986                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  34375466986                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  23514926497                       # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  23514926497                       # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    491572000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    418271000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  17630608000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  47014565986                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total  65555016986                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    491572000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    418271000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  17630608000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  47014565986                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  52503366783                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total 118058383769                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        35919                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        57212                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    680641500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    457877000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total   1138518500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  52792392844                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  52792392844                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   4817060992                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   4817060992                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   2920885493                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   2920885493                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1762500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1762500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  12110424498                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  12110424498                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  17339026500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  17339026500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  33290154486                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  33290154486                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  22238992991                       # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  22238992991                       # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    680641500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    457877000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  17339026500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  45400578984                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total  63878123984                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    680641500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    457877000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  17339026500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  45400578984                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  52792392844                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total 116670516828                       # number of overall MSHR miss cycles
 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1725979000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5812178000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   7538157000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   3078004000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   4803983000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   1725979000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   5812178000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   7538157000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.021110                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.048079                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.027823                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks     0.000001                       # mshr miss rate for WritebackDirty accesses
-system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total     0.000001                       # mshr miss rate for WritebackDirty accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   3078004000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   4803983000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.037192                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.058923                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.042391                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for WritebackClean accesses
 system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total     0.000000                       # mshr miss rate for WritebackClean accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.996733                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.996733                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.999990                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.999990                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.999842                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.999842                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.999974                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.999974                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.214098                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.214098                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.098271                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.098271                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.251498                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.251498                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.771791                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.771791                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.021110                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.048079                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.098271                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.242815                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.157972                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.021110                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.048079                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.098271                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.242815                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.209906                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.209906                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.099943                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.099943                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.243132                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.243132                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.772747                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.772747                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.037192                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.058923                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.099943                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.235520                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.157218                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.037192                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.058923                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.099943                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.235520                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.230754                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 36963.079931                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 41668.758717                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38987.144877                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56590.929630                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56590.929630                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20556.048168                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20556.048168                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16627.774157                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16627.774157                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 655374.750000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 655374.750000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 44819.023202                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 44819.023202                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 28775.786737                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28775.786737                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31374.295958                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31374.295958                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 36606.229223                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 36606.229223                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 36963.079931                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 41668.758717                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 28775.786737                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34126.392569                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32554.736432                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 36963.079931                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 41668.758717                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 28775.786737                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34126.392569                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56590.929630                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 40136.035953                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.228959                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28922.853015                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 39048.012963                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 32290.152869                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59475.138338                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 59475.138338                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18533.216598                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18533.216598                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15397.474383                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15397.474383                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       587500                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       587500                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 45129.381880                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 45129.381880                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 29103.997241                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29103.997241                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31830.259628                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31830.259628                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 36425.359014                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 36425.359014                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28922.853015                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 39048.012963                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 29103.997241                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34545.803791                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32838.272405                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28922.853015                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 39048.012963                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 29103.997241                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34545.803791                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59475.138338                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 41184.535280                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81058.516883                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185781.620585                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 143370.934611                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180158.267486                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 125175.439054                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81058.516883                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 93378.821715                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 90238.424152                       # average overall mshr uncacheable latency
-system.cpu0.toL2Bus.snoop_filter.tot_requests     26220064                       # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests     13479100                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         2657                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops      2182451                       # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops      2181920                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops          531                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.cpu0.toL2Bus.trans_dist::ReadReq        979416                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp     11666319                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        30958                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        30958                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty      6060800                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean      8438347                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict      2860883                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq      1184490                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFResp            1                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq       488552                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       348527                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       533031                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           69                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          124                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq      1347603                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp      1325056                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      6235149                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq      5307790                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq       891051                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateResp       832317                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     18746760                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     20650560                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       436622                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1328978                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total         41162920                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    798358288                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    780155262                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1670248                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      5039864                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total        1585223662                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    7567060                       # Total snoops (count)
-system.cpu0.toL2Bus.snoopTraffic            126041936                       # Total snoop traffic (bytes)
-system.cpu0.toL2Bus.snoop_fanout::samples     21529267                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       0.118569                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.323357                       # Request fanout histogram
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 85692.920182                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 83968.101098                       # average overall mshr uncacheable latency
+system.cpu0.toL2Bus.snoop_filter.tot_requests     25397703                       # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests     13066663                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         1795                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops       671473                       # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       671468                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops            5                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.cpu0.toL2Bus.trans_dist::ReadReq        963728                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp     11315166                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate            2                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        18834                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        18834                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty      5872564                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean      8129050                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict      1348327                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq      1122615                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFResp           22                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq       466810                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       338240                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       510310                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           74                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          125                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq      1307620                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp      1285212                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      5961057                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq      5219350                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq       843100                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateResp       790085                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     17925156                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     20147173                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       419117                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1337980                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total         39829426                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    763317520                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    765224037                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1592032                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      5061960                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total        1535195549                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    5838031                       # Total snoops (count)
+system.cpu0.toL2Bus.snoopTraffic            119621704                       # Total snoop traffic (bytes)
+system.cpu0.toL2Bus.snoop_fanout::samples     19351504                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       0.054273                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.226556                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0          18977100     88.15%     88.15% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1           2551636     11.85%    100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2               531      0.00%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0          18301249     94.57%     94.57% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1           1050250      5.43%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2                 5      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total      21529267                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy   26091722433                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total      19351504                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy   25250991712                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    187623310                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    173970437                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   9380939070                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   8969219750                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   9216328089                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   9025116687                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy    228203766                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy    220608496                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy    699632706                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy    706093257                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups              194671556                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted        153305610                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect          6254288                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups           157865267                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               88709282                       # Number of BTB hits
+system.cpu1.branchPred.lookups              128968222                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         85282466                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect          6518355                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            89675287                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               55364340                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            56.193033                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS               16475486                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect            172497                       # Number of incorrect RAS predictions.
-system.cpu1.branchPred.indirectLookups        3896881                       # Number of indirect predictor lookups.
-system.cpu1.branchPred.indirectHits           2381021                       # Number of indirect target hits.
-system.cpu1.branchPred.indirectMisses         1515860                       # Number of indirect misses.
-system.cpu1.branchPredindirectMispredicted       389837                       # Number of mispredicted indirect branches.
-system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
+system.cpu1.branchPred.BTBHitPct            61.738682                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS               17439644                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect            182879                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.indirectLookups        4134289                       # Number of indirect predictor lookups.
+system.cpu1.branchPred.indirectHits           2557852                       # Number of indirect target hits.
+system.cpu1.branchPred.indirectMisses         1576437                       # Number of indirect misses.
+system.cpu1.branchPredindirectMispredicted       401535                       # Number of mispredicted indirect branches.
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1724,93 +1712,96 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dtb.walker.walks                   533309                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong               533309                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        10503                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        81680                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore       248509                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples       284800                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean  2470.932233                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 13518.648671                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-32767       279405     98.11%     98.11% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::32768-65535         3083      1.08%     99.19% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::65536-98303          908      0.32%     99.51% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::98304-131071          713      0.25%     99.76% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::131072-163839          284      0.10%     99.86% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::163840-196607          163      0.06%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::196608-229375          124      0.04%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::229376-262143           32      0.01%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::262144-294911           13      0.00%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::294912-327679           40      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::327680-360447           32      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.walker.walks                   531460                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               531460                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        10155                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        82594                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore       244261                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples       287199                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean  2189.199823                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 12408.912934                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-32767       282304     98.30%     98.30% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::32768-65535         2996      1.04%     99.34% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::65536-98303          743      0.26%     99.60% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::98304-131071          602      0.21%     99.81% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::131072-163839          197      0.07%     99.88% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::163840-196607          152      0.05%     99.93% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::196608-229375          103      0.04%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::229376-262143           33      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::262144-294911           16      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::294912-327679           35      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::327680-360447           11      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::360448-393215            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::425984-458751            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total       284800                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples       268382                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 19517.668845                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 17136.373439                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 13227.910444                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-32767       250971     93.51%     93.51% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-65535        15361      5.72%     99.24% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-98303          757      0.28%     99.52% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::98304-131071          835      0.31%     99.83% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-163839           87      0.03%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::163840-196607          116      0.04%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-229375          116      0.04%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::229376-262143           51      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-294911           29      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::294912-327679           31      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-360447            7      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::360448-393215           15      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkWaitTime::458752-491519            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total       287199                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples       267684                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 20635.114538                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 18133.747768                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 11911.787641                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-32767       239914     89.63%     89.63% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-65535        26330      9.84%     99.46% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-98303          756      0.28%     99.74% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::98304-131071          476      0.18%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-163839           73      0.03%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::163840-196607           24      0.01%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-229375           55      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::229376-262143           22      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-294911            9      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::294912-327679            8      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-360447            3      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::360448-393215            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu1.dtb.walker.walkCompletionTime::393216-425983            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::491520-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total       268382                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 466126532996                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.617043                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.546089                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0-1 464998520496     99.76%     99.76% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::2-3    569195000      0.12%     99.88% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4-5    249472000      0.05%     99.93% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::6-7    122508000      0.03%     99.96% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8-9     91886000      0.02%     99.98% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::10-11     55274500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12-13     15901500      0.00%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::14-15     23390500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::16-17       385000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 466126532996                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        81681     88.61%     88.61% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M        10503     11.39%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total        92184                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       533309                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkCompletionTime::425984-458751            6      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total       267684                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 465694213496                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.593113                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.550788                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0-1 464589649996     99.76%     99.76% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::2-3    559093500      0.12%     99.88% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4-5    239052500      0.05%     99.93% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::6-7    120378000      0.03%     99.96% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8-9     87009500      0.02%     99.98% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::10-11     57335500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12-13     14978500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::14-15     26310000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::16-17       396500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::18-19         9500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 465694213496                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        82595     89.05%     89.05% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M        10155     10.95%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total        92750                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       531460                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       533309                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        92184                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       531460                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        92750                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        92184                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total       625493                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        92750                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total       624210                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                   161844710                       # DTB read hits
-system.cpu1.dtb.read_misses                    366883                       # DTB read misses
-system.cpu1.dtb.write_hits                   74184112                       # DTB write hits
-system.cpu1.dtb.write_misses                   166426                       # DTB write misses
+system.cpu1.dtb.read_hits                    93944307                       # DTB read hits
+system.cpu1.dtb.read_misses                    364370                       # DTB read misses
+system.cpu1.dtb.write_hits                   78170381                       # DTB write hits
+system.cpu1.dtb.write_misses                   167090                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              44490                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                   1069                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   34599                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      386                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  6272                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid              44145                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                   1062                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   34720                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      381                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  5735                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    37354                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses               162211593                       # DTB read accesses
-system.cpu1.dtb.write_accesses               74350538                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    39000                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                94308677                       # DTB read accesses
+system.cpu1.dtb.write_accesses               78337471                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        236028822                       # DTB hits
-system.cpu1.dtb.misses                         533309                       # DTB misses
-system.cpu1.dtb.accesses                    236562131                       # DTB accesses
-system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.hits                        172114688                       # DTB hits
+system.cpu1.dtb.misses                         531460                       # DTB misses
+system.cpu1.dtb.accesses                    172646148                       # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1840,1178 +1831,1180 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.cpu1.itb.walker.walks                    80718                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong                80718                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2          768                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        57037                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore        10137                       # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples        70581                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean   996.309205                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev  6981.449622                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-32767        70036     99.23%     99.23% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::32768-65535          380      0.54%     99.77% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::65536-98303           60      0.09%     99.85% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::98304-131071           83      0.12%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.cpu1.itb.walker.walks                    82381                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                82381                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2         1018                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        59631                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore         9853                       # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples        72528                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean   882.590172                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev  6870.472006                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-32767        72114     99.43%     99.43% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::32768-65535          279      0.38%     99.81% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::65536-98303           39      0.05%     99.87% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::98304-131071           75      0.10%     99.97% # Table walker wait (enqueue to first request) latency
 system.cpu1.itb.walker.walkWaitTime::131072-163839            6      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::163840-196607            8      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::196608-229375            5      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::229376-262143            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::262144-294911            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        70581                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        67942                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 24162.219246                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 22142.693859                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 15015.121608                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535        66991     98.60%     98.60% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071          778      1.15%     99.75% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607          100      0.15%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143           45      0.07%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679           20      0.03%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        67942                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 397380257260                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean     0.877039                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev     0.328570                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0    48883602860     12.30%     12.30% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1   348476867900     87.69%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2       18158500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::3        1572000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::4          56000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 397380257260                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        57037     98.67%     98.67% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M          768      1.33%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        57805                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkWaitTime::163840-196607            6      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::229376-262143            3      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::262144-294911            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::294912-327679            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::327680-360447            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::491520-524287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        72528                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        70502                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 24022.878784                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 22243.496704                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 12757.621468                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-32767        63844     90.56%     90.56% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-65535         6070      8.61%     99.17% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-98303           93      0.13%     99.30% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::98304-131071          382      0.54%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-163839           44      0.06%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::163840-196607           19      0.03%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-229375           18      0.03%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::229376-262143            8      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-294911            6      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::294912-327679            8      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-360447            5      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::360448-393215            1      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-425983            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::425984-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        70502                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 379792000076                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean     0.874646                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev     0.331269                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0    47625596788     12.54%     12.54% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1   332150851288     87.46%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2       14331500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::3         990000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::4         230500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 379792000076                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K        59631     98.32%     98.32% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M         1018      1.68%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        60649                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        80718                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total        80718                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        82381                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        82381                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        57805                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        57805                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       138523                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   264777096                       # ITB inst hits
-system.cpu1.itb.inst_misses                     80718                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        60649                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        60649                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       143030                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   201934152                       # ITB inst hits
+system.cpu1.itb.inst_misses                     82381                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              44490                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                   1069                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   24684                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              44145                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                   1062                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   24569                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                   195163                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                   202631                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               264857814                       # ITB inst accesses
-system.cpu1.itb.hits                        264777096                       # DTB hits
-system.cpu1.itb.misses                          80718                       # DTB misses
-system.cpu1.itb.accesses                    264857814                       # DTB accesses
-system.cpu1.numPwrStateTransitions               9670                       # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples         4835                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean    9724953244.725336                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev   147881742434.863098                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::underflows         3183     65.83%     65.83% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1000-5e+10         1626     33.63%     99.46% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::5e+10-1e+11            2      0.04%     99.50% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11            5      0.10%     99.61% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11            2      0.04%     99.65% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11            1      0.02%     99.67% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11            1      0.02%     99.69% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12            1      0.02%     99.71% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::overflows           14      0.29%    100.00% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::min_value          500                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::max_value 7390881470984                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total           4835                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON   364202361753                       # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 47020148938247                       # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles                       728406370                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               202016533                       # ITB inst accesses
+system.cpu1.itb.hits                        201934152                       # DTB hits
+system.cpu1.itb.misses                          82381                       # DTB misses
+system.cpu1.itb.accesses                    202016533                       # DTB accesses
+system.cpu1.numPwrStateTransitions              26784                       # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples        13392                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean    3512583180.059961                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev   88770415671.353104                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows         3351     25.02%     25.02% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10        10014     74.78%     99.80% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5e+10-1e+11            1      0.01%     99.81% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11            1      0.01%     99.81% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11            1      0.01%     99.82% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11            4      0.03%     99.85% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::3.5e+11-4e+11            2      0.01%     99.87% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11            1      0.01%     99.87% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::6e+11-6.5e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11            1      0.01%     99.90% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::overflows           14      0.10%    100.00% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::max_value 7430623145540                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total          13392                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON   343403762637                       # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 47040513947363                       # Cumulative time (in ticks) in various power states
+system.cpu1.numCycles                       686817572                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles          83192103                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                     724269312                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                  194671556                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches         107565789                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                    610871186                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles               13439122                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                   1719504                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles              273339                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles      5608482                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       704978                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles       774415                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                264561727                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes              1602178                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                  26700                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         709863568                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.153991                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            1.257090                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles          87491536                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                     569150585                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                  128968222                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches          75361836                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                    564504137                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles               14030828                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                   1743458                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles              273069                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles      5670150                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       713565                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles       783781                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                201710843                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes              1678338                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                  26867                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         668195110                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.000138                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            1.225435                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0               331851103     46.75%     46.75% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1               119648081     16.86%     63.60% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                75565351     10.65%     74.25% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3               182799033     25.75%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0               348421230     52.14%     52.14% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1               124504424     18.63%     70.78% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                42025261      6.29%     77.07% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3               153244195     22.93%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           709863568                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.267257                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.994320                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                98062054                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles            297890044                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                275618841                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles             33512378                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               4780251                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved            17247911                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred              1977266                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts             743961992                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts             21656856                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               4780251                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles               130238128                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles               40363481                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles     204147620                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                276602035                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles             53732053                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts             728176206                       # Number of instructions processed by rename
-system.cpu1.rename.SquashedInsts              5626727                       # Number of squashed instructions processed by rename
-system.cpu1.rename.ROBFullEvents              9082967                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                240191                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                268836                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents              22296515                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.FullRegisterEvents           11543                       # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands          630286495                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups           1024905330                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups       827525539                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups           801877                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps            577128327                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                53158158                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts          14384532                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts      12638476                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                 67737488                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads           162372694                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores           77181222                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads          8520193                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores         7294637                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                 707349171                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded           14663402                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                711466322                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued          2509310                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined       50084332                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     32217686                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        252969                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    709863568                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        1.002258                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.141899                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total           668195110                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.187777                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.828678                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles               102161242                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles            311763510                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                215198558                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles             34078749                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               4993051                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved            18208977                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred              2060516                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts             590405276                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts             22672761                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               4993051                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles               135354794                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles               41008219                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles     216515907                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                215714387                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles             54608752                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts             573925738                       # Number of instructions processed by rename
+system.cpu1.rename.SquashedInsts              5865325                       # Number of squashed instructions processed by rename
+system.cpu1.rename.ROBFullEvents              9111156                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                235226                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                246551                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents              22706071                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.FullRegisterEvents           10845                       # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands          544713354                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            881414288                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups       677140554                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups           799785                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps            489645115                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                55068233                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts          14685141                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts      12835902                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                 68922736                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads            94552173                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores           81340147                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads          8760661                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores         7542596                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                 552653279                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded           14818656                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                556478216                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued          2578197                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined       52065959                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     33349277                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        259122                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    668195110                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.832808                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.070079                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0          346424684     48.80%     48.80% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1          123916139     17.46%     66.26% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2          138092978     19.45%     85.71% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3           94358537     13.29%     99.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4            7067534      1.00%    100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5               3696      0.00%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0          364178661     54.50%     54.50% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1          127786531     19.12%     73.63% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2          107346035     16.07%     89.69% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3           61539810      9.21%     98.90% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4            7340180      1.10%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5               3893      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      709863568                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      668195110                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu               53419887     27.72%     27.72% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                 53191      0.03%     27.75% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                  19037      0.01%     27.76% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     27.76% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     27.76% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     27.76% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     27.76% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     27.76% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     27.76% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     27.76% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     27.76% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     27.76% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     27.76% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     27.76% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     27.76% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     27.76% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     27.76% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     27.76% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     27.76% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     27.76% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     27.76% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     27.76% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     27.76% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     27.76% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     27.76% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc              15      0.00%     27.76% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     27.76% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     27.76% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     27.76% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead             103986379     53.96%     81.72% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite             35231745     18.28%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu               55774345     44.07%     44.07% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                 53478      0.04%     44.12% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                  18362      0.01%     44.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     44.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     44.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     44.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%     44.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     44.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     44.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     44.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     44.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     44.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     44.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     44.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     44.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%     44.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     44.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%     44.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     44.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     44.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     44.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     44.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     44.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     44.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     44.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc              15      0.00%     44.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     44.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     44.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     44.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead              33579431     26.53%     70.66% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite             37124892     29.34%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass               25      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu            469996066     66.06%     66.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult             1210560      0.17%     66.23% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                70927      0.01%     66.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     66.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     66.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     66.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     66.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     66.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     66.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     66.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     66.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     66.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     66.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     66.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     66.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     66.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     66.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     66.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     66.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              8      0.00%     66.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp             15      0.00%     66.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt             25      0.00%     66.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc         81598      0.01%     66.25% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     66.25% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.25% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.25% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead           164776620     23.16%     89.41% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite           75330478     10.59%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass               35      0.00%      0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu            378772554     68.07%     68.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult             1203453      0.22%     68.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                69506      0.01%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt             25      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.29% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc         82169      0.01%     68.31% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.31% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.31% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.31% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead            96967073     17.43%     85.73% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite           79383378     14.27%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total             711466322                       # Type of FU issued
-system.cpu1.iq.rate                          0.976744                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                  192710254                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.270863                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads        2326678945                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes        771690256                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses    695698465                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads            1336829                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes            536159                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses       497637                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses             903350253                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                 826298                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads         2394067                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total             556478216                       # Type of FU issued
+system.cpu1.iq.rate                          0.810227                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                  126550523                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.227413                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads        1908944024                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes        619142753                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses    540109020                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads            1336236                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes            533681                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses       496559                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses             682200972                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                 827732                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads         2535076                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads     11654320                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses        15948                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation       130447                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores      5130974                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads     12050927                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses        15964                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation       139670                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores      5367770                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads      2399995                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked      3738162                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads      2479862                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked      3811174                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               4780251                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                5901245                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles              1355404                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts          722138785                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewSquashCycles               4993051                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                6066595                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles              1484920                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts          567600146                       # Number of instructions dispatched to IQ
 system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts            162372694                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts            77181222                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts          12419825                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                 58724                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents              1239916                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents        130447                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect       1767111                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect      2862185                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts             4629296                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts            704121990                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts            161840669                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts          6820718                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewDispLoadInsts             94552173                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts            81340147                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts          12593166                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                 61012                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents              1366008                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents        139670                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect       1864288                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect      2962654                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts             4826942                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts            548760252                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts             93936954                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts          7198002                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       126212                       # number of nop insts executed
-system.cpu1.iew.exec_refs                   236024480                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches               169760384                       # Number of branches executed
-system.cpu1.iew.exec_stores                  74183811                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.966661                       # Inst execution rate
-system.cpu1.iew.wb_sent                     696881354                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                    696196102                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                357262878                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                517340824                       # num instructions consuming a value
-system.cpu1.iew.wb_rate                      0.955780                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.690575                       # average fanout of values written-back
-system.cpu1.commit.commitSquashedInsts       43732145                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls       14410433                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts          4314978                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    701540457                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.957790                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.589997                       # Number of insts commited each cycle
+system.cpu1.iew.exec_nop                       128211                       # number of nop insts executed
+system.cpu1.iew.exec_refs                   172107181                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches               103045741                       # Number of branches executed
+system.cpu1.iew.exec_stores                  78170227                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.798990                       # Inst execution rate
+system.cpu1.iew.wb_sent                     541337937                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                    540605579                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                260784878                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                427489689                       # num instructions consuming a value
+system.cpu1.iew.wb_rate                      0.787117                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.610038                       # average fanout of values written-back
+system.cpu1.commit.commitSquashedInsts       45375845                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls       14559534                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts          4495992                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    659550921                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.781450                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.574730                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0    413092247     58.88%     58.88% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1    113176092     16.13%     75.02% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2     83530992     11.91%     86.92% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3     51841229      7.39%     94.31% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4     11508500      1.64%     95.95% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5      7726725      1.10%     97.05% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6      5343630      0.76%     97.82% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7      3131269      0.45%     98.26% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8     12189773      1.74%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0    433210493     65.68%     65.68% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1    117319741     17.79%     83.47% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2     50366969      7.64%     91.11% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3     16989740      2.58%     93.68% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4     12025543      1.82%     95.51% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5      8091474      1.23%     96.73% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6      5593324      0.85%     97.58% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7      3365512      0.51%     98.09% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8     12588125      1.91%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    701540457                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts           597176554                       # Number of instructions committed
-system.cpu1.commit.committedOps             671928235                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    659550921                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts           437257329                       # Number of instructions committed
+system.cpu1.commit.committedOps             515405969                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                     222768619                       # Number of memory references committed
-system.cpu1.commit.loads                    150718371                       # Number of loads committed
-system.cpu1.commit.membars                   39196572                       # Number of memory barriers committed
-system.cpu1.commit.branches                 164739467                       # Number of branches committed
-system.cpu1.commit.fp_insts                    488627                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                631392614                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls            12167965                       # Number of function calls committed.
+system.cpu1.commit.refs                     158473622                       # Number of memory references committed
+system.cpu1.commit.loads                     82501245                       # Number of loads committed
+system.cpu1.commit.membars                    3568741                       # Number of memory barriers committed
+system.cpu1.commit.branches                  97797753                       # Number of branches committed
+system.cpu1.commit.fp_insts                    487077                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                473223690                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls            12865392                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu       448043617     66.68%     66.68% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult         985154      0.15%     66.83% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv           56630      0.01%     66.84% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     66.84% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     66.84% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     66.84% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     66.84% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     66.84% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     66.84% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     66.84% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     66.84% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     66.84% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     66.84% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     66.84% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     66.84% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     66.84% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     66.84% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     66.84% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     66.84% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     66.84% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            8      0.00%     66.84% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     66.84% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp           13      0.00%     66.84% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt           21      0.00%     66.84% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     66.84% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc        74173      0.01%     66.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     66.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.85% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead      150718371     22.43%     89.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite      72050248     10.72%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu       355828768     69.04%     69.04% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult         973462      0.19%     69.23% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv           55201      0.01%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            8      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp           13      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt           21      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc        74874      0.01%     69.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead       82501245     16.01%     85.26% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite      75972377     14.74%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total        671928235                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events             12189773                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                  1401264531                       # The number of ROB reads
-system.cpu1.rob.rob_writes                 1439606443                       # The number of ROB writes
-system.cpu1.timesIdled                         902579                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                       18542802                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                 94040296263                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                  597176554                       # Number of Instructions Simulated
-system.cpu1.committedOps                    671928235                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.219750                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.219750                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.819840                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.819840                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads               799341399                       # number of integer regfile reads
-system.cpu1.int_regfile_writes              475575163                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                   787030                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                  454812                       # number of floating regfile writes
-system.cpu1.cc_regfile_reads                112918659                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes               113685571                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads             1436513215                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes              14489141                       # number of misc regfile writes
-system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.tags.replacements          5047432                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          457.905792                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs          212666270                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs          5047943                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            42.129293                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     8477400492000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   457.905792                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.894347                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.894347                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0          149                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          323                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           39                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses        457080025                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses       457080025                       # Number of data accesses
-system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.ReadReq_hits::cpu1.data    145190780                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total      145190780                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data     62993534                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total      62993534                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data       167629                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total       167629                       # number of SoftPFReq hits
-system.cpu1.dcache.WriteLineReq_hits::cpu1.data       116242                       # number of WriteLineReq hits
-system.cpu1.dcache.WriteLineReq_hits::total       116242                       # number of WriteLineReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1721505                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total      1721505                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1728884                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total      1728884                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data    208300556                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total       208300556                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data    208468185                       # number of overall hits
-system.cpu1.dcache.overall_hits::total      208468185                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data      5993321                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total      5993321                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data      6604202                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      6604202                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data       607895                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total       607895                       # number of SoftPFReq misses
-system.cpu1.dcache.WriteLineReq_misses::cpu1.data       421696                       # number of WriteLineReq misses
-system.cpu1.dcache.WriteLineReq_misses::total       421696                       # number of WriteLineReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       237246                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total       237246                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data       187668                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total       187668                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data     13019219                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total      13019219                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data     13627114                       # number of overall misses
-system.cpu1.dcache.overall_misses::total     13627114                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  89379669000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total  89379669000                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 119695443135                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 119695443135                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  10488678921                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::total  10488678921                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   3322992000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total   3322992000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4669078500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total   4669078500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      3521000                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      3521000                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 219563791056                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 219563791056                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 219563791056                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 219563791056                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data    151184101                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total    151184101                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data     69597736                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total     69597736                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       775524                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total       775524                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       537938                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::total       537938                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1958751                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total      1958751                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1916552                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total      1916552                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data    221319775                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total    221319775                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data    222095299                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total    222095299                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.039643                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.039643                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.094891                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.094891                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.783851                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.783851                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.783912                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::total     0.783912                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.121121                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.121121                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.097920                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.097920                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.058825                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.058825                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.061357                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.061357                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14913.212391                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14913.212391                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18124.134170                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 18124.134170                       # average WriteReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24872.607094                       # average WriteLineReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24872.607094                       # average WriteLineReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14006.524873                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14006.524873                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24879.460004                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24879.460004                       # average StoreCondReq miss latency
+system.cpu1.commit.op_class_0::total        515405969                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events             12588125                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                  1203797977                       # The number of ROB reads
+system.cpu1.rob.rob_writes                 1130170940                       # The number of ROB writes
+system.cpu1.timesIdled                         922689                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                       18622462                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                 94081017888                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                  437257329                       # Number of Instructions Simulated
+system.cpu1.committedOps                    515405969                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              1.570740                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.570740                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.636643                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.636643                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads               647634757                       # number of integer regfile reads
+system.cpu1.int_regfile_writes              384292228                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                   785728                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                  454696                       # number of floating regfile writes
+system.cpu1.cc_regfile_reads                117471222                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes               118161265                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads             1199366647                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes              14671382                       # number of misc regfile writes
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.tags.replacements          5153619                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          456.044406                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs          148207895                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs          5154131                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            28.755166                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     8517415326000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   456.044406                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.890712                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.890712                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          390                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           19                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses        328622817                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses       328622817                       # Number of data accesses
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.ReadReq_hits::cpu1.data     76967758                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       76967758                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data     66682281                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total      66682281                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data       189501                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total       189501                       # number of SoftPFReq hits
+system.cpu1.dcache.WriteLineReq_hits::cpu1.data       166829                       # number of WriteLineReq hits
+system.cpu1.dcache.WriteLineReq_hits::total       166829                       # number of WriteLineReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1726427                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total      1726427                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1743769                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total      1743769                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data    143816868                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total       143816868                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data    144006369                       # number of overall hits
+system.cpu1.dcache.overall_hits::total      144006369                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data      5978399                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total      5978399                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      6727643                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      6727643                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data       625948                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total       625948                       # number of SoftPFReq misses
+system.cpu1.dcache.WriteLineReq_misses::cpu1.data       458256                       # number of WriteLineReq misses
+system.cpu1.dcache.WriteLineReq_misses::total       458256                       # number of WriteLineReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       242959                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total       242959                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data       183921                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total       183921                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data     13164298                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total      13164298                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data     13790246                       # number of overall misses
+system.cpu1.dcache.overall_misses::total     13790246                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  87383841500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total  87383841500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 119886339095                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total 119886339095                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  11324190656                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::total  11324190656                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   3328957500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total   3328957500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4379371000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total   4379371000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      2907500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      2907500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 218594371251                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 218594371251                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 218594371251                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 218594371251                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data     82946157                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total     82946157                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data     73409924                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total     73409924                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       815449                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total       815449                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       625085                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::total       625085                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1969386                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total      1969386                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1927690                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total      1927690                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data    156981166                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total    156981166                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data    157796615                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total    157796615                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.072076                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.072076                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.091645                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.091645                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.767611                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.767611                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.733110                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::total     0.733110                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.123368                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.123368                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.095410                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.095410                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.083859                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.083859                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.087393                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.087393                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14616.595764                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14616.595764                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17819.961478                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 17819.961478                       # average WriteReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24711.494571                       # average WriteLineReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24711.494571                       # average WriteLineReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13701.725394                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13701.725394                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23811.152614                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23811.152614                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16864.590038                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 16864.590038                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16112.273740                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 16112.273740                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs      2706631                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets     18960106                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs           351175                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets         660083                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs     7.707357                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets    28.723821                       # average number of cycles each access was blocked
-system.cpu1.dcache.writebacks::writebacks      5047462                       # number of writebacks
-system.cpu1.dcache.writebacks::total          5047462                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data      3052290                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total      3052290                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      5325465                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total      5325465                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data         3276                       # number of WriteLineReq MSHR hits
-system.cpu1.dcache.WriteLineReq_mshr_hits::total         3276                       # number of WriteLineReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data       122610                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total       122610                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data      8381031                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total      8381031                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data      8381031                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total      8381031                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2941031                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total      2941031                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1278737                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total      1278737                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       607807                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total       607807                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       418420                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::total       418420                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       114636                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total       114636                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       187667                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total       187667                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data      4638188                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total      4638188                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data      5245995                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total      5245995                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         7218                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total         7218                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         7480                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total         7480                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        14698                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total        14698                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  39704145500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total  39704145500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  24666220214                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total  24666220214                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  14600377000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  14600377000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data   9957787421                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total   9957787421                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1521960000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1521960000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   4481476500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   4481476500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      3456000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      3456000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  74328153135                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total  74328153135                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  88928530135                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total  88928530135                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    880126000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    880126000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    880126000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total    880126000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.019453                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.019453                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018373                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018373                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.783737                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.783737                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.777822                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.777822                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.058525                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.058525                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.097919                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.097919                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.020957                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.020957                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.023620                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.023620                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13500.077184                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13500.077184                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19289.517871                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19289.517871                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24021.403176                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24021.403176                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23798.545531                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23798.545531                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13276.457657                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13276.457657                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23879.938934                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23879.938934                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16605.091381                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 16605.091381                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15851.375766                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 15851.375766                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs      2917967                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets     18895353                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs           374678                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets         668758                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs     7.787933                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets    28.254395                       # average number of cycles each access was blocked
+system.cpu1.dcache.writebacks::writebacks      5153631                       # number of writebacks
+system.cpu1.dcache.writebacks::total          5153631                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data      3023211                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total      3023211                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      5427179                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total      5427179                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data         3743                       # number of WriteLineReq MSHR hits
+system.cpu1.dcache.WriteLineReq_mshr_hits::total         3743                       # number of WriteLineReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data       127495                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total       127495                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data      8454133                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total      8454133                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data      8454133                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total      8454133                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2955188                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total      2955188                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1300464                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total      1300464                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       625861                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total       625861                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       454513                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::total       454513                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       115464                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total       115464                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       183920                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total       183920                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data      4710165                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total      4710165                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data      5336026                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total      5336026                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        21232                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total        21232                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        19410                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total        19410                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        40642                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total        40642                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  40128990000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total  40128990000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  24368462066                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total  24368462066                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  13718666000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  13718666000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  10741056156                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  10741056156                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1514532000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1514532000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   4195522000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   4195522000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      2836500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      2836500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  75238508222                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total  75238508222                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  88957174222                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total  88957174222                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3718611500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   3718611500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   3718611500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   3718611500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035628                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035628                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.017715                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.017715                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.767505                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.767505                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.727122                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.727122                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.058629                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.058629                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.095410                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.095410                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.030005                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.030005                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.033816                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.033816                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13579.166537                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13579.166537                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18738.282694                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18738.282694                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21919.669064                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21919.669064                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23632.010869                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23632.010869                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13116.919559                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13116.919559                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22811.668117                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22811.668117                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16025.256659                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16025.256659                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16951.699370                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16951.699370                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 121934.885010                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 121934.885010                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 59880.664036                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 59880.664036                       # average overall mshr uncacheable latency
-system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.cpu1.icache.tags.replacements          5706197                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          501.707809                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs          258521982                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs          5706709                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            45.301413                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     8517122288000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   501.707809                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.979898                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.979898                       # Average percentage of cache occupancy
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15973.645981                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15973.645981                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16671.053369                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16671.053369                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 175141.837792                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 175141.837792                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 91496.764431                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 91496.764431                       # average overall mshr uncacheable latency
+system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.cpu1.icache.tags.replacements          6014648                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          501.532915                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs          195349774                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs          6015160                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            32.476239                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     8517720712000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   501.532915                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.979556                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.979556                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0          307                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1           84                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          121                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0          124                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          341                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2           47                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses        534817167                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses       534817167                       # Number of data accesses
-system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.cpu1.icache.ReadReq_hits::cpu1.inst    258521982                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total      258521982                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst    258521982                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total       258521982                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst    258521982                       # number of overall hits
-system.cpu1.icache.overall_hits::total      258521982                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst      6033199                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total      6033199                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst      6033199                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total       6033199                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst      6033199                       # number of overall misses
-system.cpu1.icache.overall_misses::total      6033199                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  64071626251                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total  64071626251                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst  64071626251                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total  64071626251                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst  64071626251                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total  64071626251                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst    264555181                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total    264555181                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst    264555181                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total    264555181                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst    264555181                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total    264555181                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.022805                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.022805                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.022805                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.022805                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.022805                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.022805                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10619.843014                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 10619.843014                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10619.843014                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 10619.843014                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10619.843014                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 10619.843014                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs      9429094                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets          244                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs           708482                       # number of cycles access was blocked
+system.cpu1.icache.tags.tag_accesses        409423979                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses       409423979                       # Number of data accesses
+system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.cpu1.icache.ReadReq_hits::cpu1.inst    195349774                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total      195349774                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst    195349774                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total       195349774                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst    195349774                       # number of overall hits
+system.cpu1.icache.overall_hits::total      195349774                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst      6354622                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total      6354622                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst      6354622                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total       6354622                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst      6354622                       # number of overall misses
+system.cpu1.icache.overall_misses::total      6354622                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  66668444908                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total  66668444908                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst  66668444908                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total  66668444908                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst  66668444908                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total  66668444908                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst    201704396                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total    201704396                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst    201704396                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total    201704396                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst    201704396                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total    201704396                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.031505                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.031505                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.031505                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.031505                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.031505                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.031505                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10491.331335                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 10491.331335                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10491.331335                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 10491.331335                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10491.331335                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 10491.331335                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs      9555681                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets          472                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs           727552                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              4                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs    13.308869                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets           61                       # average number of cycles each access was blocked
-system.cpu1.icache.writebacks::writebacks      5706197                       # number of writebacks
-system.cpu1.icache.writebacks::total          5706197                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst       326394                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total       326394                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst       326394                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total       326394                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst       326394                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total       326394                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      5706805                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total      5706805                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst      5706805                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total      5706805                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst      5706805                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total      5706805                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
-system.cpu1.icache.ReadReq_mshr_uncacheable::total           67                       # number of ReadReq MSHR uncacheable
-system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.overall_mshr_uncacheable_misses::total           67                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  58058775330                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total  58058775330                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  58058775330                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total  58058775330                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  58058775330                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total  58058775330                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      6679498                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      6679498                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      6679498                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total      6679498                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.021571                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.021571                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.021571                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.021571                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.021571                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.021571                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10173.604202                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10173.604202                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10173.604202                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 10173.604202                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10173.604202                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 10173.604202                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst        99694                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total        99694                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst        99694                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total        99694                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.prefetcher.num_hwpf_issued      6901811                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified      6907587                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit         5314                       # number of redundant prefetches already in prefetch queue
+system.cpu1.icache.avg_blocked_cycles::no_mshrs    13.134018                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets          118                       # average number of cycles each access was blocked
+system.cpu1.icache.writebacks::writebacks      6014648                       # number of writebacks
+system.cpu1.icache.writebacks::total          6014648                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst       339435                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total       339435                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst       339435                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total       339435                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst       339435                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total       339435                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      6015187                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total      6015187                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst      6015187                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total      6015187                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst      6015187                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total      6015187                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst           68                       # number of ReadReq MSHR uncacheable
+system.cpu1.icache.ReadReq_mshr_uncacheable::total           68                       # number of ReadReq MSHR uncacheable
+system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst           68                       # number of overall MSHR uncacheable misses
+system.cpu1.icache.overall_mshr_uncacheable_misses::total           68                       # number of overall MSHR uncacheable misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  60428904539                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total  60428904539                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  60428904539                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total  60428904539                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  60428904539                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total  60428904539                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      6183499                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      6183499                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      6183499                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total      6183499                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.029822                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.029822                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.029822                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.029822                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.029822                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.029822                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10046.055848                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10046.055848                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10046.055848                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 10046.055848                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10046.055848                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 10046.055848                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90933.808824                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90933.808824                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90933.808824                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90933.808824                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.cpu1.l2cache.prefetcher.num_hwpf_issued      6826847                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified      6833838                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit         6347                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage       821749                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.tags.replacements         2026075                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       13356.542127                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs          16274118                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs         2041771                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs            7.970589                       # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle    9992426830500                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 12440.422172                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    43.172118                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    33.879322                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data     0.000015                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   839.068499                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.759303                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.002635                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.002068                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.000000                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.051213                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.815219                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1386                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           96                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14214                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           75                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          230                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          627                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          454                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            2                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           79                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            7                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            8                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          211                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          797                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         4633                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4798                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3775                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.084595                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005859                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.867554                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses       369100514                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses      369100514                       # Number of data accesses
-system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       546957                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       179929                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total        726886                       # number of ReadReq hits
-system.cpu1.l2cache.WritebackDirty_hits::writebacks      3170558                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackDirty_hits::total      3170558                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackClean_hits::writebacks      7581614                       # number of WritebackClean hits
-system.cpu1.l2cache.WritebackClean_hits::total      7581614                       # number of WritebackClean hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data          544                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total          544                       # number of UpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data            2                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::total            2                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data       815108                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total       815108                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      5173102                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total      5173102                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2742764                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total      2742764                       # number of ReadSharedReq hits
-system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       184198                       # number of InvalidateReq hits
-system.cpu1.l2cache.InvalidateReq_hits::total       184198                       # number of InvalidateReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       546957                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker       179929                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst      5173102                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data      3557872                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total        9457860                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       546957                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker       179929                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst      5173102                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data      3557872                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total       9457860                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        11826                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         8080                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total        19906                       # number of ReadReq misses
-system.cpu1.l2cache.WritebackDirty_misses::writebacks            4                       # number of WritebackDirty misses
-system.cpu1.l2cache.WritebackDirty_misses::total            4                       # number of WritebackDirty misses
+system.cpu1.l2cache.prefetcher.pfSpanPage       835722                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.cpu1.l2cache.tags.replacements         1955228                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       12896.405710                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs          10261646                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs         1970971                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs            5.206391                       # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
+system.cpu1.l2cache.tags.occ_blocks::writebacks 12598.365224                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    35.187602                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    26.957161                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   235.895723                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.768943                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.002148                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.001645                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.014398                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.787134                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022          398                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           66                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        15279                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::0            9                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           11                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          186                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3           92                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          100                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            3                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           49                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            8                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            6                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          231                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         2171                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         6847                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4119                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         1911                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.024292                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.004028                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.932556                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses       388828691                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses      388828691                       # Number of data accesses
+system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
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+system.cpu1.l2cache.ReadReq_hits::total        721353                       # number of ReadReq hits
+system.cpu1.l2cache.WritebackDirty_hits::writebacks      3280399                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackDirty_hits::total      3280399                       # number of WritebackDirty hits
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+system.cpu1.l2cache.WritebackClean_hits::total      7886275                       # number of WritebackClean hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.data           44                       # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::total           44                       # number of UpgradeReq hits
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+system.cpu1.l2cache.ReadExReq_hits::total       841994                       # number of ReadExReq hits
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+system.cpu1.l2cache.ReadCleanReq_hits::total      5485264                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2792582                       # number of ReadSharedReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::total      2792582                       # number of ReadSharedReq hits
+system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       201829                       # number of InvalidateReq hits
+system.cpu1.l2cache.InvalidateReq_hits::total       201829                       # number of InvalidateReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       536780                       # number of demand (read+write) hits
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 system.cpu1.l2cache.WritebackClean_misses::writebacks            1                       # number of WritebackClean misses
 system.cpu1.l2cache.WritebackClean_misses::total            1                       # number of WritebackClean misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       224180                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total       224180                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       187653                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total       187653                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data           12                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::total           12                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data       246832                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total       246832                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       533612                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total       533612                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       917456                       # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total       917456                       # number of ReadSharedReq misses
-system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       232409                       # number of InvalidateReq misses
-system.cpu1.l2cache.InvalidateReq_misses::total       232409                       # number of InvalidateReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        11826                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker         8080                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst       533612                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data      1164288                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total      1717806                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        11826                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker         8080                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst       533612                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data      1164288                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total      1717806                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    438373000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    291991000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total    730364000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   2034074000                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total   2034074000                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   1455556000                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   1455556000                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      3356498                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      3356498                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  10810838997                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total  10810838997                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  18150969000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::total  18150969000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  32024307483                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total  32024307483                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data    362347000                       # number of InvalidateReq miss cycles
-system.cpu1.l2cache.InvalidateReq_miss_latency::total    362347000                       # number of InvalidateReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    438373000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    291991000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst  18150969000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data  42835146480                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total  61716479480                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    438373000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    291991000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst  18150969000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data  42835146480                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total  61716479480                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       558783                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       188009                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total       746792                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::writebacks      3170562                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::total      3170562                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::writebacks      7581615                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::total      7581615                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       224724                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total       224724                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       187655                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total       187655                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data           12                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::total           12                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1061940                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total      1061940                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      5706714                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total      5706714                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3660220                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total      3660220                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       416607                       # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.InvalidateReq_accesses::total       416607                       # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       558783                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       188009                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst      5706714                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data      4722160                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total     11175666                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       558783                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       188009                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst      5706714                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data      4722160                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total     11175666                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.021164                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.042977                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.026655                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks     0.000001                       # miss rate for WritebackDirty accesses
-system.cpu1.l2cache.WritebackDirty_miss_rate::total     0.000001                       # miss rate for WritebackDirty accesses
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+system.cpu1.l2cache.UpgradeReq_misses::total       218938                       # number of UpgradeReq misses
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+system.cpu1.l2cache.SCUpgradeFailReq_misses::total            4                       # number of SCUpgradeFailReq misses
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data       248462                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadExReq_misses::total       248462                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       529890                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::total       529890                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       900142                       # number of ReadSharedReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::total       900142                       # number of ReadSharedReq misses
+system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       250350                       # number of InvalidateReq misses
+system.cpu1.l2cache.InvalidateReq_misses::total       250350                       # number of InvalidateReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        18586                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker         8726                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.inst       529890                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.data      1148604                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::total      1705806                       # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        18586                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker         8726                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst       529890                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data      1148604                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total      1705806                       # number of overall misses
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    561198500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    279280000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::total    840478500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    939555000                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total    939555000                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    281624500                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    281624500                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      2725499                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      2725499                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  10972899994                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::total  10972899994                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  18159407000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::total  18159407000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  31177890486                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::total  31177890486                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data    362314500                       # number of InvalidateReq miss cycles
+system.cpu1.l2cache.InvalidateReq_miss_latency::total    362314500                       # number of InvalidateReq miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    561198500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    279280000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.inst  18159407000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.data  42150790480                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::total  61150675980                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    561198500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    279280000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst  18159407000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.data  42150790480                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total  61150675980                       # number of overall miss cycles
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       555366                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       193299                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total       748665                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::writebacks      3280399                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::total      3280399                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::writebacks      7886276                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::total      7886276                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       218982                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total       218982                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       183916                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total       183916                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            4                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            4                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1090456                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total      1090456                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      6015154                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::total      6015154                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3692724                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::total      3692724                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       452179                       # number of InvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.InvalidateReq_accesses::total       452179                       # number of InvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       555366                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       193299                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst      6015154                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data      4783180                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total     11546999                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       555366                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       193299                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst      6015154                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data      4783180                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total     11546999                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.033466                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.045142                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.036481                       # miss rate for ReadReq accesses
 system.cpu1.l2cache.WritebackClean_miss_rate::writebacks     0.000000                       # miss rate for WritebackClean accesses
 system.cpu1.l2cache.WritebackClean_miss_rate::total     0.000000                       # miss rate for WritebackClean accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.997579                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.997579                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.999989                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.999989                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.999799                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.999799                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.232435                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.232435                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.093506                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.093506                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.250656                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.250656                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.557861                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.557861                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.021164                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.042977                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.093506                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.246558                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.153709                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.021164                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.042977                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.093506                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.246558                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.153709                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 37068.577710                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 36137.500000                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 36690.646036                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  9073.396378                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  9073.396378                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  7756.635918                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  7756.635918                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 279708.166667                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 279708.166667                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43798.368919                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43798.368919                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 34015.293884                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 34015.293884                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 34905.551310                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 34905.551310                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data  1559.091946                       # average InvalidateReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total  1559.091946                       # average InvalidateReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 37068.577710                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 36137.500000                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34015.293884                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 36790.851130                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 35927.502570                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 37068.577710                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 36137.500000                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34015.293884                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 36790.851130                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 35927.502570                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs          264                       # number of cycles access was blocked
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.227851                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.227851                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.088093                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.088093                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.243761                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.243761                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.553652                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.553652                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.033466                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.045142                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.088093                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.240134                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.147727                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.033466                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.045142                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.088093                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.240134                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.147727                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 30194.689551                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 32005.500802                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 30773.231547                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  4291.420402                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  4291.420402                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  1531.266991                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  1531.266991                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 681374.750000                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 681374.750000                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44163.292552                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44163.292552                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 34270.144747                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 34270.144747                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 34636.635649                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 34636.635649                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data  1447.231875                       # average InvalidateReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total  1447.231875                       # average InvalidateReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 30194.689551                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 32005.500802                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34270.144747                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 36697.408750                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 35848.552520                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 30194.689551                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 32005.500802                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34270.144747                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 36697.408750                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 35848.552520                       # average overall miss latency
+system.cpu1.l2cache.blocked_cycles::no_mshrs          288                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_mshrs               5                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    52.800000                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    57.600000                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.l2cache.unused_prefetches           40814                       # number of HardPF blocks evicted w/o reference
-system.cpu1.l2cache.writebacks::writebacks      1038265                       # number of writebacks
-system.cpu1.l2cache.writebacks::total         1038265                       # number of writebacks
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker            3                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker            8                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::total           11                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         9551                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total         9551                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            1                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data         4369                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total         4369                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker            3                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker            8                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            1                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data        13920                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total        13932                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker            3                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker            8                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            1                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data        13920                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total        13932                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        11823                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         8072                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total        19895                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks            4                       # number of WritebackDirty MSHR misses
-system.cpu1.l2cache.WritebackDirty_mshr_misses::total            4                       # number of WritebackDirty MSHR misses
+system.cpu1.l2cache.unused_prefetches           40502                       # number of HardPF blocks evicted w/o reference
+system.cpu1.l2cache.writebacks::writebacks      1084478                       # number of writebacks
+system.cpu1.l2cache.writebacks::total         1084478                       # number of writebacks
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker           75                       # number of ReadReq MSHR hits
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+system.cpu1.l2cache.ReadExReq_mshr_hits::total        10775                       # number of ReadExReq MSHR hits
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+system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
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+system.cpu1.l2cache.ReadSharedReq_mshr_hits::total         4833                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data            2                       # number of InvalidateReq MSHR hits
+system.cpu1.l2cache.InvalidateReq_mshr_hits::total            2                       # number of InvalidateReq MSHR hits
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+system.cpu1.l2cache.demand_mshr_hits::cpu1.data        15608                       # number of demand (read+write) MSHR hits
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 system.cpu1.l2cache.WritebackClean_mshr_misses::writebacks            1                       # number of WritebackClean MSHR misses
 system.cpu1.l2cache.WritebackClean_mshr_misses::total            1                       # number of WritebackClean MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       718321                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total       718321                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       224180                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total       224180                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       187653                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       187653                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data           12                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total           12                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       237281                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total       237281                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       533611                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       533611                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       913087                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       913087                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       232409                       # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::total       232409                       # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        11823                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         8072                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       533611                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1150368                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total      1703874                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        11823                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         8072                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       533611                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1150368                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       718321                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total      2422195                       # number of overall MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         7218                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         7285                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         7480                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         7480                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        14698                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        14765                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    367372500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    243371500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    610744000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  32165766903                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  32165766903                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   4735558998                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   4735558998                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   3071141498                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   3071141498                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      2966498                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2966498                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   8013535997                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   8013535997                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  14949290000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  14949290000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  26287930983                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  26287930983                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data   6248930499                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total   6248930499                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    367372500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    243371500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  14949290000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  34301466980                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total  49861500980                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    367372500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    243371500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  14949290000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  34301466980                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  32165766903                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total  82027267883                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      6176000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    822175500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    828351500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      6176000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    822175500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    828351500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.021158                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.042934                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.026641                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks     0.000001                       # mshr miss rate for WritebackDirty accesses
-system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total     0.000001                       # mshr miss rate for WritebackDirty accesses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       693628                       # number of HardPFReq MSHR misses
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+system.cpu1.l2cache.UpgradeReq_mshr_misses::total       218938                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       183916                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       183916                       # number of SCUpgradeReq MSHR misses
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+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            4                       # number of SCUpgradeFailReq MSHR misses
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+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       529888                       # number of ReadCleanReq MSHR misses
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+system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       250348                       # number of InvalidateReq MSHR misses
+system.cpu1.l2cache.InvalidateReq_mshr_misses::total       250348                       # number of InvalidateReq MSHR misses
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+system.cpu1.l2cache.overall_mshr_misses::total      2383558                       # number of overall MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst           68                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        21232                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        21300                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        19410                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        19410                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst           68                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        40642                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        40710                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    448702000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    224952500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    673654500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  32672970024                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  32672970024                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   4113980492                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   4113980492                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2813333996                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2813333996                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      2299499                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2299499                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   7950875496                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   7950875496                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  14980050000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  14980050000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  25503490486                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  25503490486                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data   6724179499                       # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total   6724179499                       # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    448702000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    224952500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  14980050000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  33454365982                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total  49108070482                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    448702000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    224952500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  14980050000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  33454365982                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  32672970024                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total  81781040506                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      5673000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   3548566000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   3554239000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      5673000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   3548566000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   3554239000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.033331                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.044154                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.036126                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for WritebackClean accesses
 system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total     0.000000                       # mshr miss rate for WritebackClean accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.997579                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.997579                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.999989                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.999989                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.999799                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.999799                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.223441                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.223441                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.093506                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.093506                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.249462                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.249462                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.557861                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.557861                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.021158                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.042934                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.093506                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.243611                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.152463                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.021158                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.042934                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.093506                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.243611                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.217970                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.217970                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.088092                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.088092                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.242452                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.242452                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.553648                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.553648                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.033331                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.044154                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.088092                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.236871                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.146352                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.033331                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.044154                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.088092                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.236871                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.216738                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31072.697285                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 30150.086720                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30698.366424                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44779.098624                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 44779.098624                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21123.913810                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21123.913810                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16366.066612                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16366.066612                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 247208.166667                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 247208.166667                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33772.345856                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33772.345856                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 28015.333267                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28015.333267                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28790.171126                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28790.171126                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26887.644192                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26887.644192                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31072.697285                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 30150.086720                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28015.333267                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 29817.820889                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29263.608095                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31072.697285                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 30150.086720                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28015.333267                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 29817.820889                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44779.098624                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33864.848983                       # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92179.104478                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 113906.275977                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 113706.451613                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92179.104478                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 55937.916723                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 56102.370471                       # average overall mshr uncacheable latency
-system.cpu1.toL2Bus.snoop_filter.tot_requests     22350657                       # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests     11505244                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         1543                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops      1883368                       # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops      1883027                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops          341                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.cpu1.toL2Bus.trans_dist::ReadReq        842183                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp     10302833                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq         7480                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp         7480                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty      4215889                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean      7583095                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict      2514473                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq       909607                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFResp            6                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq       430035                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       341692                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp       476439                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           71                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          124                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq      1090279                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp      1068076                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq      5706805                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4656106                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq       474602                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateResp       416607                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     17119850                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16343111                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       395526                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1186164                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total         35044651                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    730427376                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    631688689                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1504072                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4470264                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total        1368090401                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                    6163170                       # Total snoops (count)
-system.cpu1.toL2Bus.snoopTraffic             73999248                       # Total snoop traffic (bytes)
-system.cpu1.toL2Bus.snoop_fanout::samples     18018661                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       0.123449                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.329009                       # Request fanout histogram
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.206422                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24239.749338                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 26356.473345                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 24907.731273                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 47104.456602                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 47104.456602                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18790.618769                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18790.618769                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15296.842015                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15296.842015                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 574874.750000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 574874.750000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33451.032223                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33451.032223                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 28270.219367                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28270.219367                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28485.685373                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28485.685373                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26859.329809                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26859.329809                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24239.749338                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 26356.473345                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28270.219367                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 29527.346947                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29059.233508                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24239.749338                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 26356.473345                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28270.219367                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 29527.346947                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 47104.456602                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34310.488986                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 83426.470588                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 167132.912585                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 166865.680751                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 83426.470588                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 87312.779883                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 87306.288381                       # average overall mshr uncacheable latency
+system.cpu1.toL2Bus.snoop_filter.tot_requests     23161545                       # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests     11911126                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         1586                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops       559932                       # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       559928                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops            4                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.cpu1.toL2Bus.trans_dist::ReadReq        858463                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp     10650090                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq        19410                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp        19410                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty      4372034                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean      7887876                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict      1202832                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq       877539                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFResp           29                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq       412195                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       333118                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp       458356                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           58                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          125                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq      1116808                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp      1095312                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq      6015187                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4685876                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq       509592                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateResp       452179                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     18045125                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16655613                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       406321                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1179507                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total         36286566                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    769908416                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    641765745                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1546392                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4442928                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total        1417663481                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                    4824103                       # Total snoops (count)
+system.cpu1.toL2Bus.snoopTraffic             76247568                       # Total snoop traffic (bytes)
+system.cpu1.toL2Bus.snoop_fanout::samples     17122714                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       0.052642                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.223318                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0          15794619     87.66%     87.66% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1           2223701     12.34%    100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2               341      0.00%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0          16221347     94.74%     94.74% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1            901363      5.26%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2                 4      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total      18018661                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy   22188055468                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total      17122714                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy   23027796506                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy    182014003                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy    160947650                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy   8566090793                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy   9028759604                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy   7517136176                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy   7641863842                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy    207825380                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy    213393747                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy    628033176                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy    624968323                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq                40328                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40328                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136631                       # Transaction distribution
-system.iobus.trans_dist::WriteResp             136631                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47646                       # Packet count per connected master and slave (bytes)
+system.iobus.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.iobus.trans_dist::ReadReq                40315                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40315                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136630                       # Transaction distribution
+system.iobus.trans_dist::WriteResp             136630                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47698                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
@@ -3022,15 +3015,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122580                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231258                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231258                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231230                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231230                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353918                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47666                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353890                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47718                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -3041,19 +3034,19 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       155687                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7339048                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7339048                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       155710                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338936                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7338936                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7496821                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             36938002                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7496732                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             36996503                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               332000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               325000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer3.occupancy                10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
@@ -3061,85 +3054,85 @@ system.iobus.reqLayer4.occupancy                10500                       # La
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy               10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer14.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer15.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               13500                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               13000                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            24205503                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            24232502                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            36443500                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            36410001                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           569408550                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           568919799                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            92680000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            92681000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147954000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147926000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements               115626                       # number of replacements
-system.iocache.tags.tagsinuse               11.305309                       # Cycle average of tags in use
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.replacements               115610                       # number of replacements
+system.iocache.tags.tagsinuse               11.211324                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115642                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115626                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         9115830406000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     7.413187                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     3.892123                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.463324                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.243258                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.706582                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         9155814843000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     7.413268                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     3.798056                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.463329                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.237379                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.700708                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1041018                       # Number of tag accesses
-system.iocache.tags.data_accesses             1041018                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.tag_accesses              1040892                       # Number of tag accesses
+system.iocache.tags.data_accesses             1040892                       # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8901                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8938                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8887                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8924                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide       115629                       # number of demand (read+write) misses
-system.iocache.demand_misses::total            115669                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide       115615                       # number of demand (read+write) misses
+system.iocache.demand_misses::total            115655                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide       115629                       # number of overall misses
-system.iocache.overall_misses::total           115669                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5198500                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1667264523                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1672463023                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide       115615                       # number of overall misses
+system.iocache.overall_misses::total           115655                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5200000                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1677259553                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1682459553                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  12925157527                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  12925157527                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5567500                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide  14592422050                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  14597989550                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5567500                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide  14592422050                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  14597989550                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  12947566246                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  12947566246                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5569000                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide  14624825799                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  14630394799                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5569000                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide  14624825799                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total  14630394799                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8901                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8938                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8887                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8924                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide       115629                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total          115669                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide       115615                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total          115655                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide       115629                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total         115669                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide       115615                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total         115655                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -3153,53 +3146,53 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet       140500                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 187312.046175                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 187118.261692                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140540.540541                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 188731.805221                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 188531.998319                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 121103.717178                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 121103.717178                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet 139187.500000                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 126200.365393                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 126204.856530                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet 139187.500000                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 126200.365393                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 126204.856530                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         33241                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 121313.678191                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 121313.678191                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet       139225                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 126495.920071                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 126500.322502                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet       139225                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 126495.920071                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 126500.322502                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         33395                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3524                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3494                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.432747                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.557813                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks          106695                       # number of writebacks
-system.iocache.writebacks::total               106695                       # number of writebacks
+system.iocache.writebacks::writebacks          106693                       # number of writebacks
+system.iocache.writebacks::total               106693                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8901                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8938                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8887                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8924                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide       115629                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total       115669                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide       115615                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total       115655                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide       115629                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total       115669                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3348500                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1222214523                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1225563023                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide       115615                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total       115655                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3350000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1232909553                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1236259553                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7580015931                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   7580015931                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3567500                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   8802230454                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   8805797954                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3567500                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   8802230454                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   8805797954                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7602399187                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   7602399187                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3569000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   8835308740                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   8838877740                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3569000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   8835308740                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   8838877740                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -3213,664 +3206,665 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet        90500                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137312.046175                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 137118.261692                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90540.540541                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138731.805221                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 138531.998319                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 71021.811811                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 71021.811811                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89187.500000                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 76124.765016                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 76129.282297                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89187.500000                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 76124.765016                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 76129.282297                       # average overall mshr miss latency
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements                  1557710                       # number of replacements
-system.l2c.tags.tagsinuse                63573.891854                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    6243665                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1617388                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     3.860338                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle               3022937500                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   21119.731437                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   317.083055                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   501.157048                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4189.705266                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data    12756.928607                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 18825.078792                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker    29.382680                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker    33.853586                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     2676.679680                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     1884.367858                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  1239.923843                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.322262                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.004838                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.007647                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.063930                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.194655                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.287248                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000448                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.000517                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.040843                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.028753                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.018920                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.970061                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        11464                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023          277                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        47937                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::1            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2         1377                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3          337                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4         9749                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::2            5                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          272                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          349                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         3074                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5518                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        38948                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.174927                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.004227                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.731461                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 79574133                       # Number of tag accesses
-system.l2c.tags.data_accesses                79574133                       # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.l2c.WritebackDirty_hits::writebacks      2888931                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total         2888931                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks            1                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total               1                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data          180891                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data          129539                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total              310430                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data         43976                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data         36797                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total             80773                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            55787                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            50048                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               105835                       # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         6797                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker         4576                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst       551177                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       671308                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       325157                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         6401                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4256                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst       484948                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       535287                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       285618                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total          2875525                       # number of ReadSharedReq hits
-system.l2c.InvalidateReq_hits::cpu0.data       132882                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::cpu1.data       123273                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::total           256155                       # number of InvalidateReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          6797                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          4576                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              551177                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              727095                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher       325157                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          6401                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          4256                       # number of demand (read+write) hits
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-system.l2c.demand_hits::cpu1.data              585335                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher       285618                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2981360                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         6797                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         4576                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             551177                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             727095                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher       325157                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         6401                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         4256                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             484948                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             585335                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher       285618                       # number of overall hits
-system.l2c.overall_hits::total                2981360                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data         62870                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         65353                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total            128223                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data        13472                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data        11956                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total           25428                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          91907                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          48160                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             140067                       # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         3207                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.itb.walker         3170                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.inst        61507                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       173115                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       339604                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         1937                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.itb.walker         1306                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.inst        48662                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data       111561                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       193805                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         937874                       # number of ReadSharedReq misses
-system.l2c.InvalidateReq_misses::cpu0.data       497642                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::cpu1.data        96113                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::total         593755                       # number of InvalidateReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         3207                       # number of demand (read+write) misses
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-system.l2c.demand_misses::cpu1.dtb.walker         1937                       # number of demand (read+write) misses
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-system.l2c.demand_misses::cpu1.data            159721                       # number of demand (read+write) misses
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-system.l2c.demand_misses::total               1077941                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         3207                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         3170                       # number of overall misses
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-system.l2c.overall_misses::cpu0.data           265022                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       339604                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker         1937                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker         1306                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            48662                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           159721                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher       193805                       # number of overall misses
-system.l2c.overall_misses::total              1077941                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data    420802000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data    429972500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total    850774500                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data     88078000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data     80352500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total    168430500                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   8572942990                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   4240159498                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  12813102488                       # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    292674000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    283861500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.inst   5444535999                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data  16594648743                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  46635334107                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    183709500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    124471000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.inst   4269928000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data  11202968996                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  26909035721                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total 111941167566                       # number of ReadSharedReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu0.data     55164500                       # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu1.data     62218500                       # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::total    117383000                       # number of InvalidateReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker    292674000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker    283861500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   5444535999                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  25167591733                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  46635334107                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker    183709500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker    124471000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst   4269928000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data  15443128494                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  26909035721                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total    124754270054                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker    292674000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker    283861500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   5444535999                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  25167591733                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  46635334107                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker    183709500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker    124471000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst   4269928000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data  15443128494                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  26909035721                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total   124754270054                       # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks      2888931                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total      2888931                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackClean_accesses::writebacks            1                       # number of WritebackClean accesses(hits+misses)
-system.l2c.WritebackClean_accesses::total            1                       # number of WritebackClean accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data       243761                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data       194892                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total          438653                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data        57448                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data        48753                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total        106201                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       147694                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        98208                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           245902                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker        10004                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         7746                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.inst       612684                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data       844423                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       664761                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         8338                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         5562                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.inst       533610                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data       646848                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       479423                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      3813399                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu0.data       630524                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu1.data       219386                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::total       849910                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker        10004                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         7746                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          612684                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          992117                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher       664761                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         8338                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         5562                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          533610                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          745056                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher       479423                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             4059301                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker        10004                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         7746                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         612684                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         992117                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       664761                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         8338                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         5562                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         533610                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         745056                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher       479423                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            4059301                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.257917                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.335329                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.292311                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.234508                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.245236                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.239433                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.622280                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.490388                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.569605                       # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.320572                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.409243                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.100389                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.205010                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.510866                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.232310                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.234808                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.091194                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.172469                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.404246                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.245942                       # miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu0.data     0.789251                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu1.data     0.438100                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::total     0.698609                       # miss rate for InvalidateReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.320572                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.409243                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.100389                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.267128                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.510866                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.232310                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.234808                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.091194                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.214374                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.404246                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.265548                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.320572                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.409243                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.100389                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.267128                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.510866                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.232310                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.234808                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.091194                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.214374                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.404246                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.265548                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  6693.208207                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  6579.231252                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  6635.116165                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  6537.856295                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  6720.684175                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  6623.820198                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 93278.455286                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 88043.178945                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 91478.381689                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 91260.991581                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 89546.214511                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 88518.965305                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 95859.103735                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 137322.687916                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 94842.281879                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 95307.044410                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 87746.660639                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 100420.119899                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 138845.931328                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 119356.296865                       # average ReadSharedReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu0.data   110.851777                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu1.data   647.347393                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::total   197.696019                       # average InvalidateReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 91260.991581                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 89546.214511                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 88518.965305                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 94964.160458                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 137322.687916                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 94842.281879                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 95307.044410                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 87746.660639                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 96688.153054                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 138845.931328                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 115733.857469                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 91260.991581                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 89546.214511                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 88518.965305                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 94964.160458                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 137322.687916                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 94842.281879                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 95307.044410                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 87746.660639                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 96688.153054                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 138845.931328                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 115733.857469                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs              7857                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 71231.534246                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 71231.534246                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        89225                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 76420.090300                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 76424.518957                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        89225                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 76420.090300                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 76424.518957                       # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.l2c.tags.replacements                  1575605                       # number of replacements
+system.l2c.tags.tagsinuse                65208.311267                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    6750580                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1636875                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     4.124066                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle               3024712500                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks    9648.504654                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker   430.210636                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   509.722466                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     4113.935017                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data    22579.924066                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 21373.967512                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker    14.667516                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker    13.437669                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     2580.265558                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     2788.873436                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  1154.802739                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.147224                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.006564                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.007778                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.062774                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.344542                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.326141                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000224                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.000205                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.039372                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.042555                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.017621                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.995000                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022        10940                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023          249                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        50081                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::0            8                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::1            2                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2          103                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3          404                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4        10423                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::1            5                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          244                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          256                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         2182                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         3614                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        44004                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.166931                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.003799                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.764175                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 76956529                       # Number of tag accesses
+system.l2c.tags.data_accesses                76956529                       # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.l2c.WritebackDirty_hits::writebacks      2841841                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total         2841841                       # number of WritebackDirty hits
+system.l2c.WritebackClean_hits::writebacks            3                       # number of WritebackClean hits
+system.l2c.WritebackClean_hits::total               3                       # number of WritebackClean hits
+system.l2c.UpgradeReq_hits::cpu0.data          208782                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data          171973                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total              380755                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data         54097                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data         47819                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total            101916                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            54890                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            53294                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               108184                       # number of ReadExReq hits
+system.l2c.ReadSharedReq_hits::cpu0.dtb.walker        12794                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.itb.walker         5104                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.inst       534660                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data       628574                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       294599                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.dtb.walker        11629                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.itb.walker         5041                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.inst       480238                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data       542860                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       283154                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total          2798653                       # number of ReadSharedReq hits
+system.l2c.InvalidateReq_hits::cpu0.data       134880                       # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::cpu1.data       130480                       # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::total           265360                       # number of InvalidateReq hits
+system.l2c.demand_hits::cpu0.dtb.walker         12794                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          5104                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              534660                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              683464                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.l2cache.prefetcher       294599                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker         11629                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          5041                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              480238                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              596154                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.l2cache.prefetcher       283154                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2906837                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker        12794                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         5104                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             534660                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             683464                       # number of overall hits
+system.l2c.overall_hits::cpu0.l2cache.prefetcher       294599                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker        11629                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         5041                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             480238                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             596154                       # number of overall hits
+system.l2c.overall_hits::cpu1.l2cache.prefetcher       283154                       # number of overall hits
+system.l2c.overall_hits::total                2906837                       # number of overall hits
+system.l2c.UpgradeReq_misses::cpu0.data         24185                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data         25856                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             50041                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data          906                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data          988                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total            1894                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          87757                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          47516                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             135273                       # number of ReadExReq misses
+system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         3402                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.itb.walker         3300                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.inst        61095                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data       168033                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       329831                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         1494                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.itb.walker          962                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.inst        49649                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data       109122                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       190278                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total         917166                       # number of ReadSharedReq misses
+system.l2c.InvalidateReq_misses::cpu0.data       463890                       # number of InvalidateReq misses
+system.l2c.InvalidateReq_misses::cpu1.data       106177                       # number of InvalidateReq misses
+system.l2c.InvalidateReq_misses::total         570067                       # number of InvalidateReq misses
+system.l2c.demand_misses::cpu0.dtb.walker         3402                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.itb.walker         3300                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst             61095                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            255790                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.l2cache.prefetcher       329831                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker         1494                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.itb.walker          962                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst             49649                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data            156638                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.l2cache.prefetcher       190278                       # number of demand (read+write) misses
+system.l2c.demand_misses::total               1052439                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker         3402                       # number of overall misses
+system.l2c.overall_misses::cpu0.itb.walker         3300                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst            61095                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           255790                       # number of overall misses
+system.l2c.overall_misses::cpu0.l2cache.prefetcher       329831                       # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker         1494                       # number of overall misses
+system.l2c.overall_misses::cpu1.itb.walker          962                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst            49649                       # number of overall misses
+system.l2c.overall_misses::cpu1.data           156638                       # number of overall misses
+system.l2c.overall_misses::cpu1.l2cache.prefetcher       190278                       # number of overall misses
+system.l2c.overall_misses::total              1052439                       # number of overall misses
+system.l2c.UpgradeReq_miss_latency::cpu0.data    155584500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data    165207000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total    320791500                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data     10231000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data      8907000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total     19138000                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   8384405997                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   4313472997                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total  12697878994                       # number of ReadExReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    311169000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    297359500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.inst   5460514000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.data  16355884996                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  47369049298                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    141229500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker     92798500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.inst   4383525500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data  10640360000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  27539015255                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total 112590905549                       # number of ReadSharedReq miss cycles
+system.l2c.InvalidateReq_miss_latency::cpu0.data     36778500                       # number of InvalidateReq miss cycles
+system.l2c.InvalidateReq_miss_latency::cpu1.data     35261000                       # number of InvalidateReq miss cycles
+system.l2c.InvalidateReq_miss_latency::total     72039500                       # number of InvalidateReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker    311169000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.itb.walker    297359500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst   5460514000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data  24740290993                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  47369049298                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker    141229500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.itb.walker     92798500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst   4383525500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data  14953832997                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  27539015255                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total    125288784543                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker    311169000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.itb.walker    297359500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst   5460514000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data  24740290993                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  47369049298                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker    141229500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.itb.walker     92798500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst   4383525500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data  14953832997                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  27539015255                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total   125288784543                       # number of overall miss cycles
+system.l2c.WritebackDirty_accesses::writebacks      2841841                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total      2841841                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackClean_accesses::writebacks            3                       # number of WritebackClean accesses(hits+misses)
+system.l2c.WritebackClean_accesses::total            3                       # number of WritebackClean accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data       232967                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data       197829                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total          430796                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data        55003                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data        48807                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total        103810                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       142647                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       100810                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           243457                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker        16196                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         8404                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.inst       595755                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data       796607                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       624430                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker        13123                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         6003                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.inst       529887                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data       651982                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       473432                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total      3715819                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu0.data       598770                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu1.data       236657                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::total       835427                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker        16196                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         8404                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          595755                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          939254                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.l2cache.prefetcher       624430                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker        13123                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         6003                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          529887                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          752792                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher       473432                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             3959276                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker        16196                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         8404                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         595755                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         939254                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       624430                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker        13123                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         6003                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         529887                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         752792                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher       473432                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            3959276                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.103813                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.130699                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.116159                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.016472                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.020243                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.018245                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.615204                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.471342                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.555634                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.210052                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.392670                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.102551                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.210936                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.528211                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.113846                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.160253                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.093697                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.167370                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.401912                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.246827                       # miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu0.data     0.774738                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu1.data     0.448654                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::total     0.682366                       # miss rate for InvalidateReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.210052                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.392670                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.102551                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.272333                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.528211                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.113846                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.160253                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.093697                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.208076                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.401912                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.265816                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.210052                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.392670                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.102551                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.272333                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.528211                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.113846                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.160253                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.093697                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.208076                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.401912                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.265816                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  6433.099028                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  6389.503403                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  6410.573330                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 11292.494481                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  9015.182186                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total 10104.540655                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 95541.164773                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 90779.379514                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 93868.539871                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 91466.490300                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 90108.939394                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 89377.428595                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 97337.338475                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 143616.122493                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 94531.124498                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 96464.137214                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 88290.307962                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 97508.843313                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 144730.422093                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 122759.571930                       # average ReadSharedReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu0.data    79.282804                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu1.data   332.096405                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::total   126.370234                       # average InvalidateReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 91466.490300                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 90108.939394                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 89377.428595                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 96721.103221                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 143616.122493                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 94531.124498                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 96464.137214                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 88290.307962                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 95467.466368                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 144730.422093                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 119046.124804                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 91466.490300                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 90108.939394                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 89377.428595                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 96721.103221                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 143616.122493                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 94531.124498                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 96464.137214                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 88290.307962                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 95467.466368                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 144730.422093                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 119046.124804                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs              7554                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                       97                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                       86                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs            81                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs     87.837209                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.writebacks::writebacks             1229961                       # number of writebacks
-system.l2c.writebacks::total                  1229961                       # number of writebacks
-system.l2c.ReadSharedReq_mshr_hits::cpu0.inst           90                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu0.data           20                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.inst           89                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.data           22                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total          221                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst             90                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data             20                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst             89                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data             22                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                221                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst            90                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data            20                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst            89                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data            22                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total               221                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks        60565                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total        60565                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data        62870                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data        65353                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total       128223                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data        13472                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data        11956                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total        25428                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        91907                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        48160                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        140067                       # number of ReadExReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         3207                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         3170                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        61417                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data       173095                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       339604                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         1937                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         1306                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        48573                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data       111539                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       193805                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total       937653                       # number of ReadSharedReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu0.data       497642                       # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu1.data        96113                       # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::total       593755                       # number of InvalidateReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker         3207                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker         3170                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        61417                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       265002                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       339604                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker         1937                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker         1306                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst        48573                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data       159699                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       193805                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total          1077720                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker         3207                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker         3170                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        61417                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       265002                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       339604                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker         1937                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.itb.walker         1306                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst        48573                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data       159699                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       193805                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total         1077720                       # number of overall MSHR misses
+system.l2c.writebacks::writebacks             1208317                       # number of writebacks
+system.l2c.writebacks::total                  1208317                       # number of writebacks
+system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          117                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu0.data           19                       # number of ReadSharedReq MSHR hits
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+system.l2c.ReadSharedReq_mshr_hits::cpu1.data           30                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total          271                       # number of ReadSharedReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst            117                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.data             19                       # number of demand (read+write) MSHR hits
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+system.l2c.overall_mshr_hits::total               271                       # number of overall MSHR hits
+system.l2c.CleanEvict_mshr_misses::writebacks        63698                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total        63698                       # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data        24185                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data        25856                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        50041                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          906                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          988                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total         1894                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data        87757                       # number of ReadExReq MSHR misses
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+system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         3402                       # number of ReadSharedReq MSHR misses
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+system.l2c.ReadSharedReq_mshr_misses::total       916895                       # number of ReadSharedReq MSHR misses
+system.l2c.InvalidateReq_mshr_misses::cpu0.data       463890                       # number of InvalidateReq MSHR misses
+system.l2c.InvalidateReq_mshr_misses::cpu1.data       106177                       # number of InvalidateReq MSHR misses
+system.l2c.InvalidateReq_mshr_misses::total       570067                       # number of InvalidateReq MSHR misses
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+system.l2c.demand_mshr_misses::total          1052168                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.dtb.walker         3402                       # number of overall MSHR misses
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 system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        21293                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data        31285                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data         7216                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total        59861                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0.data        30958                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data         7480                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        38438                       # number of WriteReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu0.data        17085                       # number of ReadReq MSHR uncacheable
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+system.l2c.ReadReq_mshr_uncacheable::cpu1.data        21230                       # number of ReadReq MSHR uncacheable
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+system.l2c.WriteReq_mshr_uncacheable::cpu0.data        18834                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data        19410                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total        38244                       # number of WriteReq MSHR uncacheable
 system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        21293                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu0.data        62243                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data        14696                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total        98299                       # number of overall MSHR uncacheable misses
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data   1354983996                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data   1420163498                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total   2775147494                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data    332136996                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data    293140999                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total    625277995                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   7653704832                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3758420781                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total  11412125613                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker    260603501                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker    252160502                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   4822941587                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  14861591064                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  43239056127                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    164338502                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    111409004                       # number of ReadSharedReq MSHR miss cycles
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-system.l2c.ReadSharedReq_mshr_miss_latency::total 102545337083                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data  12306862586                       # number of InvalidateReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   2041559000                       # number of InvalidateReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::total  14348421586                       # number of InvalidateReq MSHR miss cycles
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-system.l2c.overall_mshr_miss_latency::total 113957462696                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_uncacheable_misses::cpu0.data        35919                       # number of overall MSHR uncacheable misses
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+system.l2c.overall_mshr_uncacheable_misses::cpu1.data        40640                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total        97920                       # number of overall MSHR uncacheable misses
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+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    540970500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total   1024844998                       # number of UpgradeReq MSHR miss cycles
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+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     24045000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total     46212999                       # number of SCUpgradeReq MSHR miss cycles
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+system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   2199719000                       # number of InvalidateReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::total  13748705121                       # number of InvalidateReq MSHR miss cycles
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+system.l2c.demand_mshr_miss_latency::total 114745290371                       # number of demand (read+write) MSHR miss cycles
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+system.l2c.overall_mshr_miss_latency::total 114745290371                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   1342704500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5248860501                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      4969000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    692108006                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   7288642007                       # number of ReadReq MSHR uncacheable cycles
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+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      4446500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   3166216503                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   7283646006                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1342704500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5248860501                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      4969000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    692108006                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   7288642007                       # number of overall MSHR uncacheable cycles
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+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   3166216503                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   7283646006                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.257917                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.335329                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.292311                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.234508                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.245236                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.239433                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.622280                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.490388                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.569605                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.320572                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.409243                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.100243                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.204986                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.510866                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.232310                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.234808                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.091027                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.172435                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.404246                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.245884                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.789251                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.438100                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::total     0.698609                       # mshr miss rate for InvalidateReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.320572                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.409243                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.100243                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.267108                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.510866                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.232310                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.234808                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.091027                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.214345                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.404246                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.265494                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.320572                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.409243                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.100243                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.267108                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.510866                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.232310                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.234808                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.091027                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.214345                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.404246                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.265494                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21552.155177                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21730.655027                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21643.133400                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24653.874406                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24518.317079                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24590.136660                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 83276.625632                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 78040.298609                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 81476.190773                       # average ReadExReq mshr miss latency
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-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 79545.899685                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 78527.795024                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 85858.003201                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 127321.987159                       # average ReadSharedReq mshr miss latency
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-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 85305.516080                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 77758.231343                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 90422.003810                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 128844.489781                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 109363.844709                       # average ReadSharedReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 24730.353519                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 21241.236877                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::total 24165.559172                       # average InvalidateReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 81260.835984                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79545.899685                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 78527.795024                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 84962.739511                       # average overall mshr miss latency
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-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 84841.766649                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 85305.516080                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 77758.231343                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 86688.086112                       # average overall mshr miss latency
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-system.l2c.demand_avg_mshr_miss_latency::total 105739.396778                       # average overall mshr miss latency
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-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 78527.795024                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 84962.739511                       # average overall mshr miss latency
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-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 85305.516080                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 77758.231343                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 86688.086112                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 128844.489781                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 105739.396778                       # average overall mshr miss latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.103813                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.130699                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.116159                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.016472                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.020243                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.018245                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.615204                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.471342                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.555634                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.210052                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.392670                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.102354                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.210912                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.528211                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.113846                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.160253                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.093499                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.167324                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.401912                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.246754                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.774738                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.448654                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::total     0.682366                       # mshr miss rate for InvalidateReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.210052                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.392670                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.102354                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.272313                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.528211                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.113846                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.160253                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.093499                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.208036                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.401912                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.265748                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.210052                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.392670                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.102354                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.272313                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.528211                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.113846                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.160253                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.093499                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.208036                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.401912                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.265748                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20007.215133                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20922.435798                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20480.106273                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24467.990066                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24337.044534                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24399.682682                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 85540.175428                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 80775.672510                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 83866.595921                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 81466.490300                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80108.939394                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 79397.611466                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 87340.145476                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133615.676277                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 84530.456493                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 86464.137214                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 78311.895891                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 87513.582380                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134729.425703                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 112772.350532                       # average ReadSharedReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 24895.958354                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20717.471769                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::total 24117.700412                       # average InvalidateReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 81466.490300                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80108.939394                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 79397.611466                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 86722.561889                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133615.676277                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 84530.456493                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 86464.137214                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 78311.895891                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 85469.251788                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134729.425703                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 109056.054139                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 81466.490300                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80108.939394                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 79397.611466                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 86722.561889                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133615.676277                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 84530.456493                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 86464.137214                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 78311.895891                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 85469.251788                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134729.425703                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 109056.054139                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63058.493402                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167775.627329                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 74164.179104                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 95912.972007                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 121759.442826                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 162146.824876                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 65389.705882                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 149138.789590                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 122053.187311                       # average ReadReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63058.493402                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 84328.526919                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 74164.179104                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 47094.992243                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 74147.671970                       # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests       4190264                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests      2528993                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests         3019                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 77125.713494                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 65389.705882                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 77908.870645                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 74383.639767                       # average overall mshr uncacheable latency
+system.membus.snoop_filter.tot_requests       3980803                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests      2353726                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests         3243                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq               59861                       # Transaction distribution
-system.membus.trans_dist::ReadResp            1006452                       # Transaction distribution
-system.membus.trans_dist::WriteReq              38438                       # Transaction distribution
-system.membus.trans_dist::WriteResp             38438                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1336656                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           266935                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           438975                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq         302731                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp              22                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq            3                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            150471                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           135365                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        946591                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        696687                       # Transaction distribution
+system.membus.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadReq               59676                       # Transaction distribution
+system.membus.trans_dist::ReadResp             985495                       # Transaction distribution
+system.membus.trans_dist::WriteReq              38244                       # Transaction distribution
+system.membus.trans_dist::WriteResp             38244                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1315010                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           256715                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           339680                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq         271581                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp              24                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            147332                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           134542                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        925819                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        674453                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122580                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           76                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        26078                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5027920                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      5176654                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       238145                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       238145                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5414799                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155687                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        25318                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4797896                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4945870                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237932                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       237932                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5183802                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155710                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          556                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        52156                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    147706944                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    147915343                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7266880                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7266880                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               155182223                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           597489                       # Total snoops (count)
-system.membus.snoopTraffic                     179456                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples           2633759                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.013061                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.113535                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        50636                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    144939472                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    145146374                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7255040                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7255040                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               152401414                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           572055                       # Total snoops (count)
+system.membus.snoopTraffic                     191360                       # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples           2456788                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.015156                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.122173                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 2599360     98.69%     98.69% # Request fanout histogram
-system.membus.snoop_fanout::1                   34399      1.31%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 2419553     98.48%     98.48% # Request fanout histogram
+system.membus.snoop_fanout::1                   37235      1.52%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2633759                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            98019495                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             2456788                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            98064494                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               52000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            21931994                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            21142497                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          9377704107                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          9055699898                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         5794716587                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         5680392120                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           45616715                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           45554532                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
 system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
 system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
 system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
 system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
 system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
@@ -3913,83 +3907,83 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
 system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests     12205642                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      6628070                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests      1941255                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops         157740                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops       142803                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops        14937                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384351300000                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadReq              59863                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           4654836                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             38438                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            38438                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty      4118892                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean            2                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         2762121                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          740907                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq        383504                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp        1124411                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq          124                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp          124                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           298356                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          298356                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      4595571                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq       881263                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp       849910                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     10458732                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7383011                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              17841743                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    265418110                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    179948433                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              445366543                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         3005080                       # Total snoops (count)
-system.toL2Bus.snoopTraffic                 132103248                       # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples          8556754                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.351410                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.481053                       # Request fanout histogram
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.snoop_filter.tot_requests     11893981                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      6468498                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests      1904661                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops         211231                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops       193743                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops        17488                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47383917710000                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.trans_dist::ReadReq              59678                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           4527289                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             38244                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            38244                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty      4050158                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean            3                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         2718586                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          717362                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq        373497                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp        1090859                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq          125                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp          125                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           293033                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          293033                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      4468431                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq       869390                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp       835427                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      9945746                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7459601                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              17405347                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    252717925                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    183230753                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              435948678                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         2969827                       # Total snoops (count)
+system.toL2Bus.snoopTraffic                 128627856                       # Total snoop traffic (bytes)
+system.toL2Bus.snoop_fanout::samples          8396274                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.355668                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.483046                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                5564766     65.03%     65.03% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                2977051     34.79%     99.83% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                  14937      0.17%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                5427479     64.64%     64.64% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                2951307     35.15%     99.79% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                  17488      0.21%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            8556754                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         9506782087                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            8396274                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         9289434840                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          2628899                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          2606647                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        4728944566                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        4518737086                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        3692981173                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        3678115853                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   14084                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                    5420                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    4835                       # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce                   13392                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
index 7e1388539..7623e0029 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
@@ -1,140 +1,140 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.327143                       # Number of seconds simulated
-sim_ticks                                51327142820000                       # Number of ticks simulated
-final_tick                               51327142820000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.558015                       # Number of seconds simulated
+sim_ticks                                51558014828000                       # Number of ticks simulated
+final_tick                               51558014828000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 161850                       # Simulator instruction rate (inst/s)
-host_op_rate                                   190176                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             9793667461                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 681320                       # Number of bytes of host memory used
-host_seconds                                  5240.85                       # Real time elapsed on the host
-sim_insts                                   848230502                       # Number of instructions simulated
-sim_ops                                     996685945                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 133865                       # Simulator instruction rate (inst/s)
+host_op_rate                                   157345                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6235119796                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 696436                       # Number of bytes of host memory used
+host_seconds                                  8268.97                       # Real time elapsed on the host
+sim_insts                                  1106923026                       # Number of instructions simulated
+sim_ops                                    1301083589                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.dtb.walker       227712                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker       212864                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           5673056                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          41642312                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        444928                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             48200872                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      5673056                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5673056                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     68445056                       # Number of bytes written to this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.dtb.walker       667968                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker       559488                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           6546400                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         112650248                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        429376                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            120853480                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      6546400                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         6546400                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks    140957120                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          68465636                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker         3558                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker         3326                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             104594                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             650674                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6952                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                769104                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1069454                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total         140977700                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker        10437                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker         8742                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             118240                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1760173                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6709                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1904301                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         2202455                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1072027                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker           4436                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker           4147                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               110527                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               811312                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8668                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                  939091                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          110527                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             110527                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1333506                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data                 401                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1333907                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1333506                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          4436                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker          4147                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              110527                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              811713                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8668                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2272998                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        769104                       # Number of read requests accepted
-system.physmem.writeReqs                      1072027                       # Number of write requests accepted
-system.physmem.readBursts                      769104                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1072027                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 49176064                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     46592                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  68464384                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  48200872                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               68465636                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      728                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2250                       # Number of DRAM write bursts merged with an existing one
+system.physmem.num_writes::total              2205028                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker          12956                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker          10852                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               126972                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2184922                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8328                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2344029                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          126972                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             126972                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2733952                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data                 399                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2734351                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2733952                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker         12956                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker         10852                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              126972                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2185321                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8328                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                5078380                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1904301                       # Number of read requests accepted
+system.physmem.writeReqs                      2205028                       # Number of write requests accepted
+system.physmem.readBursts                     1904301                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    2205028                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                121838144                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     37120                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                 140976896                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 120853480                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys              140977700                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      580                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               44564                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               52315                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               47721                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               44538                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               44659                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               50872                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               46439                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               47959                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               44018                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               71274                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              43972                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              51692                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              45026                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              46672                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              42515                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              44140                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               64758                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               69412                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               67623                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               66442                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               66817                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               69740                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               65132                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               69008                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               65482                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               70623                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              64235                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              70444                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              64965                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              66804                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              64273                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              63998                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              114327                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              123692                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              118245                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              117057                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              115229                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              125268                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              115683                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              119593                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              115543                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              144676                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             112600                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             120122                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             113965                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             118266                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             113146                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             116309                       # Per bank write bursts
+system.physmem.perBankWrBursts::0              135142                       # Per bank write bursts
+system.physmem.perBankWrBursts::1              141643                       # Per bank write bursts
+system.physmem.perBankWrBursts::2              136917                       # Per bank write bursts
+system.physmem.perBankWrBursts::3              137997                       # Per bank write bursts
+system.physmem.perBankWrBursts::4              135684                       # Per bank write bursts
+system.physmem.perBankWrBursts::5              143871                       # Per bank write bursts
+system.physmem.perBankWrBursts::6              135153                       # Per bank write bursts
+system.physmem.perBankWrBursts::7              138864                       # Per bank write bursts
+system.physmem.perBankWrBursts::8              135935                       # Per bank write bursts
+system.physmem.perBankWrBursts::9              142790                       # Per bank write bursts
+system.physmem.perBankWrBursts::10             134947                       # Per bank write bursts
+system.physmem.perBankWrBursts::11             140191                       # Per bank write bursts
+system.physmem.perBankWrBursts::12             134987                       # Per bank write bursts
+system.physmem.perBankWrBursts::13             137976                       # Per bank write bursts
+system.physmem.perBankWrBursts::14             134592                       # Per bank write bursts
+system.physmem.perBankWrBursts::15             136075                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          34                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51327141408500                       # Total gap between requests
+system.physmem.numWrRetry                         125                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51558013451500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                   21272                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  747819                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1883016                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1069454                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    515353                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    203905                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     30484                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     12938                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       574                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       579                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::7                      1284                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       806                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       364                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::13                      141                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      125                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      125                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      111                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      106                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       94                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       69                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        9                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                2202455                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1140639                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    689076                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     48103                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     20384                       # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::9                       388                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      416                       # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::18                       90                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       64                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        8                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
@@ -160,171 +160,170 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    26806                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    32475                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    49254                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::21                    61838                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::24                    69842                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    64006                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    76985                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::30                    60500                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    59306                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    57192                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     3147                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     1524                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1240                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      919                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::41                      591                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::44                      314                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      359                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      262                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      302                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      251                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      241                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      318                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      215                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      262                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      145                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      182                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      155                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      131                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      121                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      143                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      131                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      126                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       82                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       74                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       471870                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      249.306089                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     149.569568                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     290.567780                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         207742     44.03%     44.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       122462     25.95%     69.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        42886      9.09%     79.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        22733      4.82%     83.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        14982      3.18%     87.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         9606      2.04%     89.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         7566      1.60%     90.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         6003      1.27%     91.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        37890      8.03%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         471870                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         54238                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        14.166341                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev       76.651597                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511           54233     99.99%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-1023            2      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-1535            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                    30482                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::61                      477                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                      312                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                      365                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       933198                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      281.628105                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     167.352526                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     309.404332                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         371108     39.77%     39.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       233427     25.01%     64.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        88383      9.47%     74.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        51664      5.54%     79.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        37413      4.01%     83.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        26389      2.83%     86.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895        21045      2.26%     88.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023        17945      1.92%     90.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        85824      9.20%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         933198                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples        116229                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        16.379053                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev       52.340079                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511          116223     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023            4      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::13824-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           54238                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         54238                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        19.723367                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.775784                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        8.950161                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           40620     74.89%     74.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23            4585      8.45%     83.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27            5200      9.59%     92.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31            1381      2.55%     95.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             413      0.76%     96.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             235      0.43%     96.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             311      0.57%     97.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47             127      0.23%     97.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             390      0.72%     98.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55             127      0.23%     98.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              50      0.09%     98.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              65      0.12%     98.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             327      0.60%     99.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              36      0.07%     99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              29      0.05%     99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79             111      0.20%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83             166      0.31%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               3      0.01%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               3      0.01%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.00%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               1      0.00%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.00%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.00%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             2      0.00%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             2      0.00%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.00%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             5      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            17      0.03%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.00%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147            12      0.02%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             5      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::212-215             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           54238                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    15209667379                       # Total ticks spent queuing
-system.physmem.totMemAccLat               29616717379                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   3841880000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       19794.56                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total          116229                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples        116228                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        18.951965                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.478061                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       17.079115                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-31          111884     96.26%     96.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-47            1770      1.52%     97.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-63             397      0.34%     98.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-79             626      0.54%     98.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-95             488      0.42%     99.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-111            246      0.21%     99.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-127           362      0.31%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-143           120      0.10%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-159            64      0.06%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-175            59      0.05%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-191            51      0.04%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-207            11      0.01%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-223            17      0.01%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-239            10      0.01%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-255            37      0.03%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-271            24      0.02%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-287            14      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::288-303             3      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::304-319             2      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::320-335             1      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::336-351             2      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::352-367             6      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::368-383             5      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::384-399             4      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::400-415             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::416-431             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::480-495             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::496-511             3      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::512-527             4      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::528-543             3      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::544-559             2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::608-623             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::624-639             2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::640-655             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::752-767             2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::768-783             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::976-991             2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total          116228                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    42075497859                       # Total ticks spent queuing
+system.physmem.totMemAccLat               77770266609                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   9518605000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       22101.71                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  38544.56                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           0.96                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.33                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        0.94                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.33                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  40851.71                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.36                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.73                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.34                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.73                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.49                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     580662                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    785598                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   75.57                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.44                       # Row buffer hit rate for writes
-system.physmem.avgGap                     27878049.64                       # Average gap between requests
-system.physmem.pageHitRate                      74.33                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 1803657240                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  984138375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                2956722600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3492279360                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3352439216880                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1235640856320                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29712388110000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34309704980775                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.451533                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49429181288166                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1713925980000                       # Time in different power states
+system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        26.62                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1533744                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                   1639539                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   80.57                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  74.43                       # Row buffer hit rate for writes
+system.physmem.avgGap                     12546577.18                       # Average gap between requests
+system.physmem.pageHitRate                      77.27                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 3530119320                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1926156375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                7402894200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               7162084800                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3367518529440                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1313077918185                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29782982922000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34483600624320                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.831109                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49545451951432                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1721635240000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    184032075584                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    290927248568                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 1763679960                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  962325375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                3036563400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3439739520                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3352439216880                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1235034526230                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29712919978500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34309596029865                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.449411                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49430060847495                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1713925980000                       # Time in different power states
+system.physmem_1.actEnergy                 3524804640                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1923256500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                7446082800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               7111728720                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3367518529440                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1314046606680                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29782133195250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34483704204030                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.833118                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49544014933949                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1721635240000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    183155359005                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    292364518051                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
 system.realview.nvmem.bytes_read::cpu.inst          384                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           420                       # Number of bytes read from this memory
@@ -341,30 +340,30 @@ system.realview.nvmem.bw_inst_read::total            7                       # I
 system.realview.nvmem.bw_total::cpu.inst            7                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups               225047911                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         149825196                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          12305756                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            158986930                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                98148773                       # Number of BTB hits
+system.cpu.branchPred.lookups               290131106                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         198353835                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          13679752                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            208494226                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               130534623                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             61.733863                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                30878370                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             343644                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups         6734089                       # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits            4745857                       # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses          1988232                       # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted       765703                       # Number of mispredicted indirect branches.
+system.cpu.branchPred.BTBHitPct             62.608268                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                37597374                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             402079                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         8125236                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits            6045082                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses          2080154                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted       800698                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -394,87 +393,88 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks                    948773                       # Table walker walks requested
-system.cpu.dtb.walker.walksLong                948773                       # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksLongTerminationLevel::Level2        15596                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksLongTerminationLevel::Level3       155468                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore       437937                       # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples       510836                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean  2285.186439                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev 14758.274331                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-65535       507265     99.30%     99.30% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::65536-131071         2025      0.40%     99.70% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::131072-196607         1066      0.21%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::196608-262143          211      0.04%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::262144-327679          145      0.03%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::327680-393215           26      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::393216-458751           51      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::458752-524287           43      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.walks                   1423094                       # Table walker walks requested
+system.cpu.dtb.walker.walksLong               1423094                       # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2        30587                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3       273540                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore       668841                       # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples       754253                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean  2502.822660                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev 16371.142747                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-65535       747574     99.11%     99.11% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::65536-131071         4739      0.63%     99.74% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::131072-196607          871      0.12%     99.86% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::196608-262143          433      0.06%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::262144-327679          327      0.04%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::327680-393215           64      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::393216-458751          235      0.03%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::458752-524287            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::524288-589823            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::655360-720895            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total       510836                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples       488329                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 23221.803333                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 18175.804190                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 21042.780895                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-65535       476828     97.64%     97.64% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-131071         7891      1.62%     99.26% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-196607         2533      0.52%     99.78% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-262143          229      0.05%     99.83% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-327679          568      0.12%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-393215          131      0.03%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::393216-458751          114      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::458752-524287           26      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::524288-589823            6      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total       488329                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 779668986876                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean     0.725199                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev     0.523523                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0-1  777411937376     99.71%     99.71% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::2-3    1169683000      0.15%     99.86% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::4-5     513347500      0.07%     99.93% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::6-7     208116000      0.03%     99.95% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::8-9     157188000      0.02%     99.97% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::10-11    121226500      0.02%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::12-13     32342000      0.00%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::14-15     52541000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::16-17      2605500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 779668986876                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K        155469     90.88%     90.88% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M         15596      9.12%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total       171065                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       948773                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkWaitTime::655360-720895            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total       754253                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples       795185                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 25800.017606                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 21033.129871                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 18337.040091                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-65535       776690     97.67%     97.67% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-131071        15553      1.96%     99.63% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-196607         1840      0.23%     99.86% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::196608-262143          558      0.07%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-327679          320      0.04%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::327680-393215          153      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-458751           44      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::458752-524287           19      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::524288-589823            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total       795185                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 1040609044948                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean     0.747004                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev     0.517062                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1  1036648437448     99.62%     99.62% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3    2501393000      0.24%     99.86% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5     710900000      0.07%     99.93% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7     286069000      0.03%     99.96% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9     201203000      0.02%     99.97% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::10-11    121106500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::12-13     48982500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::14-15     87667500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::16-17      3189000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::18-19        41500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::20-21        55500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total 1040609044948                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K        273541     89.94%     89.94% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M         30587     10.06%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total       304128                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data      1423094                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total       948773                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       171065                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total      1423094                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       304128                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total       171065                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total      1119838                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total       304128                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total      1727222                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                    169411407                       # DTB read hits
-system.cpu.dtb.read_misses                     675369                       # DTB read misses
-system.cpu.dtb.write_hits                   147344334                       # DTB write hits
-system.cpu.dtb.write_misses                    273404                       # DTB write misses
-system.cpu.dtb.flush_tlb                           10                       # Number of times complete TLB was flushed
+system.cpu.dtb.read_hits                    217549636                       # DTB read hits
+system.cpu.dtb.read_misses                    1002675                       # DTB read misses
+system.cpu.dtb.write_hits                   192429615                       # DTB write hits
+system.cpu.dtb.write_misses                    420419                       # DTB write misses
+system.cpu.dtb.flush_tlb                           11                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid               39385                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid                    1019                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                    71963                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                       101                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                  10047                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_tlb_mva_asid               63275                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                    1203                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                    84838                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                       110                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                  16158                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                     69388                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                170086776                       # DTB read accesses
-system.cpu.dtb.write_accesses               147617738                       # DTB write accesses
+system.cpu.dtb.perms_faults                     86326                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                218552311                       # DTB read accesses
+system.cpu.dtb.write_accesses               192850034                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                         316755741                       # DTB hits
-system.cpu.dtb.misses                          948773                       # DTB misses
-system.cpu.dtb.accesses                     317704514                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.hits                         409979251                       # DTB hits
+system.cpu.dtb.misses                         1423094                       # DTB misses
+system.cpu.dtb.accesses                     411402345                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -504,1104 +504,1098 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks                    162181                       # Table walker walks requested
-system.cpu.itb.walker.walksLong                162181                       # Table walker walks initiated with long descriptors
-system.cpu.itb.walker.walksLongTerminationLevel::Level2         1496                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksLongTerminationLevel::Level3       120027                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksSquashedBefore        17971                       # Table walks squashed before starting
-system.cpu.itb.walker.walkWaitTime::samples       144210                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::mean  1137.740101                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::stdev  9342.723838                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0-32767       143038     99.19%     99.19% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::32768-65535          619      0.43%     99.62% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::65536-98303           86      0.06%     99.68% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::98304-131071          189      0.13%     99.81% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::131072-163839          221      0.15%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::163840-196607           35      0.02%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::196608-229375            6      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::229376-262143            8      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::262144-294911            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::294912-327679            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::327680-360447            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::360448-393215            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::393216-425983            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total       144210                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples       139494                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 29066.088864                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 24052.553358                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 24213.231696                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-65535       136396     97.78%     97.78% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-131071          707      0.51%     98.29% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-196607         1985      1.42%     99.71% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::196608-262143          151      0.11%     99.82% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::262144-327679          171      0.12%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::327680-393215           34      0.02%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::393216-458751           34      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::458752-524287            9      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::524288-589823            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total       139494                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples 676589720772                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::mean     0.947980                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::stdev     0.222341                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0     35236838356      5.21%      5.21% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::1    641313182416     94.79%     99.99% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::2        39010000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::3          686000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::4            4000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total 676589720772                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K        120027     98.77%     98.77% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::2M          1496      1.23%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total       121523                       # Table walker page sizes translated
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.walks                    177767                       # Table walker walks requested
+system.cpu.itb.walker.walksLong                177767                       # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walksLongTerminationLevel::Level2         1532                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksLongTerminationLevel::Level3       128663                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksSquashedBefore        19966                       # Table walks squashed before starting
+system.cpu.itb.walker.walkWaitTime::samples       157801                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean  1393.783943                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev  9971.559116                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-32767       155663     98.65%     98.65% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::32768-65535         1042      0.66%     99.31% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::65536-98303          672      0.43%     99.73% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::98304-131071          333      0.21%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::131072-163839           30      0.02%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::163840-196607           26      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::196608-229375           15      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::229376-262143            4      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::262144-294911            4      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::294912-327679            7      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::327680-360447            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::360448-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total       157801                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples       150161                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 28501.914612                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 23015.105793                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 23459.229673                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-65535       144112     95.97%     95.97% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-131071         5152      3.43%     99.40% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-196607          475      0.32%     99.72% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::196608-262143          255      0.17%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-327679           99      0.07%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-393215           55      0.04%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::393216-458751            8      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::458752-524287            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total       150161                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples 911756921068                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean     0.951043                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev     0.216068                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0     44693483152      4.90%      4.90% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1    867007398416     95.09%     99.99% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::2        55571500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::3          466000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::4            2000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total 911756921068                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K        128663     98.82%     98.82% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M          1532      1.18%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total       130195                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       162181                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total       162181                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       177767                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total       177767                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       121523                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total       121523                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total       283704                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                    357038073                       # ITB inst hits
-system.cpu.itb.inst_misses                     162181                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       130195                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total       130195                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total       307962                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                    462600046                       # ITB inst hits
+system.cpu.itb.inst_misses                     177767                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.itb.flush_tlb                           10                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb                           11                       # Number of times complete TLB was flushed
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid               39385                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid                    1019                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                    52848                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb_mva_asid               63275                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                    1203                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                    58185                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                    357344                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                    440221                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                357200254                       # ITB inst accesses
-system.cpu.itb.hits                         357038073                       # DTB hits
-system.cpu.itb.misses                          162181                       # DTB misses
-system.cpu.itb.accesses                     357200254                       # DTB accesses
-system.cpu.numPwrStateTransitions               32228                       # Number of power state transitions
-system.cpu.pwrStateClkGateDist::samples         16114                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::mean     3134631677.512784                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::stdev    60494120707.852806                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::underflows         6793     42.16%     42.16% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1000-5e+10         9285     57.62%     99.78% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::5e+10-1e+11            5      0.03%     99.81% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1e+11-1.5e+11            4      0.02%     99.83% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1.5e+11-2e+11            1      0.01%     99.84% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::2e+11-2.5e+11            2      0.01%     99.85% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::2.5e+11-3e+11            1      0.01%     99.86% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::3e+11-3.5e+11            2      0.01%     99.87% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::5e+11-5.5e+11            2      0.01%     99.88% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::7e+11-7.5e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
+system.cpu.itb.inst_accesses                462777813                       # ITB inst accesses
+system.cpu.itb.hits                         462600046                       # DTB hits
+system.cpu.itb.misses                          177767                       # DTB misses
+system.cpu.itb.accesses                     462777813                       # DTB accesses
+system.cpu.numPwrStateTransitions               34262                       # Number of power state transitions
+system.cpu.pwrStateClkGateDist::samples         17131                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean     2947433272.666569                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev    58590018858.186401                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::underflows         7811     45.60%     45.60% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1000-5e+10         9284     54.19%     99.79% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::5e+10-1e+11            5      0.03%     99.82% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1e+11-1.5e+11            4      0.02%     99.84% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1.5e+11-2e+11            1      0.01%     99.85% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::2e+11-2.5e+11            2      0.01%     99.86% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::2.5e+11-3e+11            1      0.01%     99.87% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::3e+11-3.5e+11            2      0.01%     99.88% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::4.5e+11-5e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::5e+11-5.5e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::9.5e+11-1e+12            1      0.01%     99.89% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::overflows           18      0.11%    100.00% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::max_value 1988780762168                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::total           16114                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateResidencyTicks::ON    815687968559                       # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::CLK_GATED 50511454851441                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                       1631385344                       # number of cpu cycles simulated
+system.cpu.pwrStateClkGateDist::total           17131                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateResidencyTicks::ON    1065535433949                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 50492479394051                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                       2131080190                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          646877625                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1002761410                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   225047911                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          133773000                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     898188451                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                26266186                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                    3841497                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                30548                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles       8722394                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles      1026877                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles         1034                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 356664988                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               6247416                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                   47904                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples         1571821519                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.747042                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.149310                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          789533395                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1294232501                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   290131106                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          174177079                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                    1253396684                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                29442936                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                    4521296                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                28032                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles      11449142                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles      1221670                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          685                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 462141962                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               6901101                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                   52491                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples         2074872372                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.731015                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.142682                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0               1014113227     64.52%     64.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                214297646     13.63%     78.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 70312417      4.47%     82.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                273098229     17.37%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0               1354023092     65.26%     65.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                279633538     13.48%     78.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 86518146      4.17%     82.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                354697596     17.09%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1571821519                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.137949                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.614669                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                526332322                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             552246914                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 434136742                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              49729183                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                9376358                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             33563941                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred               3814299                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             1086052117                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              29449193                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                9376358                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                571289803                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                66024800                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles      371545208                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 438989582                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             114595768                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1065754363                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts               6907795                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               5097238                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 334375                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 639506                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               63573833                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents            20465                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          1013430764                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1640279788                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1259572075                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           1474026                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             947250209                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 66180552                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts           26901106                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts       23243208                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 101784051                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            173837388                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           150829276                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           9883117                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          9014861                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1030729252                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded            27201158                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1045808358                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           3377405                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        61244461                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     34071399                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         308913                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1571821519                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.665348                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.919634                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total           2074872372                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.136143                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.607313                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                615922756                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             835719938                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 532432043                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              80077312                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               10720323                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             41258933                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred               4059445                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             1407827153                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              33008479                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               10720323                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                679035070                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                79966926                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles      552687037                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 549603762                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             202859254                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1383638167                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts               8109162                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               7348509                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 966276                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                1094350                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents              119568064                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents            22725                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          1333397174                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            2200696007                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1641425227                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           1433031                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps            1254726296                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 78670875                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts           43643507                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts       39180007                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 166278031                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            222554034                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           196867138                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          12635283                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         11114743                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1330840515                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded            43953891                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1360477402                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           4212137                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        73710813                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     41934009                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         368799                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    2074872372                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.655692                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.916068                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           924230442     58.80%     58.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           334342298     21.27%     80.07% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           234750151     14.93%     95.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            72048277      4.58%     99.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             6430828      0.41%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5               19523      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0          1226409345     59.11%     59.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           451307165     21.75%     80.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           291780533     14.06%     94.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            95920964      4.62%     99.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             9425546      0.45%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5               28819      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1571821519                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      2074872372                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                57691324     35.03%     35.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                 100152      0.06%     35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                   26730      0.02%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc              622      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               44285841     26.89%     62.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              62576075     38.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                73561900     34.17%     34.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                  90692      0.04%     34.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                   26794      0.01%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc              484      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     34.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               57931960     26.91%     61.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              83660297     38.86%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass                11      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             720343690     68.88%     68.88% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2530628      0.24%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                122776      0.01%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                 375      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               8      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp              15      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt              23      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc         119191      0.01%     69.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     69.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     69.14% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            173490543     16.59%     85.73% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           149201098     14.27%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass                57      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             939889673     69.09%     69.09% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2936613      0.22%     69.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                130878      0.01%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 372      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               8      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp              15      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt              23      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     69.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc         112363      0.01%     69.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     69.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     69.32% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            222587367     16.36%     85.68% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           194820033     14.32%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1045808358                       # Type of FU issued
-system.cpu.iq.rate                           0.641055                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   164680744                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.157467                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         3829023509                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        1118377930                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1027460456                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             2472874                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             938610                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       909796                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1208933693                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 1555398                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          4274316                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1360477402                       # Type of FU issued
+system.cpu.iq.rate                           0.638398                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   215272127                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.158233                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         5012901497                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        1447776434                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1338315649                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             2409942                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             914537                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       885572                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1574233532                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 1515940                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          5717597                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     14173969                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        14495                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       142953                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      6059351                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     17343387                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        24124                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       187368                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      7978529                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      2526453                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       1440750                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      3596780                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       1680866                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                9376358                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 7004216                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               6913167                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1058165202                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles               10720323                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                12040487                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               4569260                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1375079942                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             173837388                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            150829276                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts           22819114                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  57849                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               6781828                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         142953                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        3462734                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      5495013                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              8957747                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1034296660                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             169399584                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          10573772                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts             222554034                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            196867138                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts           38644291                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 177419                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               4207009                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         187368                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        4048268                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      6103351                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             10151619                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1346834094                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             217554512                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          12249639                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        234792                       # number of nop insts executed
-system.cpu.iew.exec_refs                    316739180                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                196198672                       # Number of branches executed
-system.cpu.iew.exec_stores                  147339596                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.633999                       # Inst execution rate
-system.cpu.iew.wb_sent                     1029187818                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1028370252                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 437853372                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 708400240                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       0.630366                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.618088                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts        51884426                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls        26892245                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           8549021                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1559762540                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.638999                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.273827                       # Number of insts commited each cycle
+system.cpu.iew.exec_nop                        285536                       # number of nop insts executed
+system.cpu.iew.exec_refs                    409993947                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                255680172                       # Number of branches executed
+system.cpu.iew.exec_stores                  192439435                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.631996                       # Inst execution rate
+system.cpu.iew.wb_sent                     1340240150                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1339201221                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 574929948                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 943031378                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       0.628414                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.609662                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts        62850702                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls        43585092                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           9678607                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   2060674246                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.631387                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.270689                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0   1047991029     67.19%     67.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    288035307     18.47%     85.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    120100080      7.70%     93.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     36659789      2.35%     95.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     28506606      1.83%     97.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     13942789      0.89%     98.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      8651847      0.55%     98.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      4181084      0.27%     99.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     11694009      0.75%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0   1383412740     67.13%     67.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    394991247     19.17%     86.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    150433823      7.30%     93.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     44582057      2.16%     95.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     36156812      1.75%     97.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     18175173      0.88%     98.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     10964042      0.53%     98.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      5475656      0.27%     99.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     16482696      0.80%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1559762540                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            848230502                       # Number of instructions committed
-system.cpu.commit.committedOps              996685945                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total   2060674246                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts           1106923026                       # Number of instructions committed
+system.cpu.commit.committedOps             1301083589                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      304433343                       # Number of memory references committed
-system.cpu.commit.loads                     159663418                       # Number of loads committed
-system.cpu.commit.membars                     6927415                       # Number of memory barriers committed
-system.cpu.commit.branches                  189324067                       # Number of branches committed
-system.cpu.commit.fp_insts                     898712                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 915721971                       # Number of committed integer instructions.
-system.cpu.commit.function_calls             25285288                       # Number of function calls committed.
+system.cpu.commit.refs                      394099255                       # Number of memory references committed
+system.cpu.commit.loads                     205210646                       # Number of loads committed
+system.cpu.commit.membars                     9122435                       # Number of memory barriers committed
+system.cpu.commit.branches                  247396089                       # Number of branches committed
+system.cpu.commit.fp_insts                     873905                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                1189215854                       # Number of committed integer instructions.
+system.cpu.commit.function_calls             30973786                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        689893101     69.22%     69.22% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult         2149376      0.22%     69.43% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv            98151      0.01%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd              0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp              0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt              0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult             0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv              0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd               0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu               0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp               0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt               0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc              0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult              0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift             0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd            8      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp           13      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt           21      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc       111932      0.01%     69.46% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     69.46% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.46% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.46% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead       159663418     16.02%     85.47% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite      144769925     14.53%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        904226715     69.50%     69.50% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult         2546778      0.20%     69.69% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv           104952      0.01%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            8      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp           13      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt           21      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     69.70% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc       105847      0.01%     69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.71% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead       205210646     15.77%     85.48% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite      188888609     14.52%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         996685945                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              11694009                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   2589097882                       # The number of ROB reads
-system.cpu.rob.rob_writes                  2109106528                       # The number of ROB writes
-system.cpu.timesIdled                         8171713                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        59563825                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                 101022900419                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   848230502                       # Number of Instructions Simulated
-system.cpu.committedOps                     996685945                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.923281                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.923281                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.519945                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.519945                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1223820104                       # number of integer regfile reads
-system.cpu.int_regfile_writes               731394790                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   1462803                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   780644                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 225050166                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                225684828                       # number of cc regfile writes
-system.cpu.misc_regfile_reads              2570368432                       # number of misc regfile reads
-system.cpu.misc_regfile_writes               26931155                       # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements           9701158                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.972800                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           283187639                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9701670                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             29.189577                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        2743199500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.972800                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999947                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999947                       # Average percentage of cache occupancy
+system.cpu.commit.op_class_0::total        1301083589                       # Class of committed instruction
+system.cpu.commit.bw_lim_events              16482696                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   3398675710                       # The number of ROB reads
+system.cpu.rob.rob_writes                  2741957858                       # The number of ROB writes
+system.cpu.timesIdled                         9058128                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        56207818                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                 100984949503                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                  1106923026                       # Number of Instructions Simulated
+system.cpu.committedOps                    1301083589                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               1.925229                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.925229                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.519419                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.519419                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1599627417                       # number of integer regfile reads
+system.cpu.int_regfile_writes               942915680                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   1421408                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   762380                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 312164706                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                313034766                       # number of cc regfile writes
+system.cpu.misc_regfile_reads              3414318389                       # number of misc regfile reads
+system.cpu.misc_regfile_writes               44468731                       # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements          13662519                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.983620                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           361203380                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs          13663031                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             26.436548                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        1659288500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.983620                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999968                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999968                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           97                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          392                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           23                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           89                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          395                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           28                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1237018765                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1237018765                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data    147199934                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       147199934                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    128255410                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      128255410                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       377663                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        377663                       # number of SoftPFReq hits
-system.cpu.dcache.WriteLineReq_hits::cpu.data       323814                       # number of WriteLineReq hits
-system.cpu.dcache.WriteLineReq_hits::total       323814                       # number of WriteLineReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      3295431                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      3295431                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data      3691256                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      3691256                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     275779158                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        275779158                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    276156821                       # number of overall hits
-system.cpu.dcache.overall_hits::total       276156821                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      9580915                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       9580915                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data     11254027                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total     11254027                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data      1170464                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total      1170464                       # number of SoftPFReq misses
-system.cpu.dcache.WriteLineReq_misses::cpu.data      1233639                       # number of WriteLineReq misses
-system.cpu.dcache.WriteLineReq_misses::total      1233639                       # number of WriteLineReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data       446709                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total       446709                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data            8                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total            8                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data     22068581                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       22068581                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     23239045                       # number of overall misses
-system.cpu.dcache.overall_misses::total      23239045                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 168767240000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 168767240000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 444298934810                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 444298934810                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  52375248289                       # number of WriteLineReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::total  52375248289                       # number of WriteLineReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   6883962000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total   6883962000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       380500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       380500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 665441423099                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 665441423099                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 665441423099                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 665441423099                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    156780849                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    156780849                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    139509437                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    139509437                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data      1548127                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total      1548127                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::cpu.data      1557453                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::total      1557453                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3742140                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      3742140                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data      3691264                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      3691264                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    297847739                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    297847739                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    299395866                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    299395866                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.061110                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.061110                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.080669                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.080669                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.756052                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.756052                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.792087                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::total     0.792087                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.119373                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.119373                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.tags.tag_accesses        1599492126                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1599492126                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data    186946586                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       186946586                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    163344159                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      163344159                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       463383                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        463383                       # number of SoftPFReq hits
+system.cpu.dcache.WriteLineReq_hits::cpu.data       333988                       # number of WriteLineReq hits
+system.cpu.dcache.WriteLineReq_hits::total       333988                       # number of WriteLineReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      4793284                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      4793284                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      5278947                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      5278947                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     350624733                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        350624733                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    351088116                       # number of overall hits
+system.cpu.dcache.overall_hits::total       351088116                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data     12788061                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total      12788061                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data     18648516                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total     18648516                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data      2041461                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total      2041461                       # number of SoftPFReq misses
+system.cpu.dcache.WriteLineReq_misses::cpu.data      1270506                       # number of WriteLineReq misses
+system.cpu.dcache.WriteLineReq_misses::total      1270506                       # number of WriteLineReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data       548369                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total       548369                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data            9                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total            9                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data     32707083                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       32707083                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     34748544                       # number of overall misses
+system.cpu.dcache.overall_misses::total      34748544                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 205827865000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 205827865000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 1003464059741                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 1003464059741                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  29968640002                       # number of WriteLineReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::total  29968640002                       # number of WriteLineReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   8933513500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total   8933513500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       300500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       300500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 1239260564743                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 1239260564743                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 1239260564743                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 1239260564743                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    199734647                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    199734647                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    181992675                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    181992675                       # number of WriteReq accesses(hits+misses)
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+system.cpu.dcache.SoftPFReq_accesses::total      2504844                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::cpu.data      1604494                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::total      1604494                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      5341653                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      5341653                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data      5278956                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      5278956                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    383331816                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    383331816                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    385836660                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    385836660                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.064025                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.064025                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.102468                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.102468                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.815005                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.815005                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.791842                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::total     0.791842                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.102659                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.102659                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000002                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000002                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.074093                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.074093                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.077620                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.077620                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17614.939700                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 17614.939700                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39479.106884                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 39479.106884                       # average WriteReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 42455.895354                       # average WriteLineReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::total 42455.895354                       # average WriteLineReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15410.394686                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15410.394686                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 47562.500000                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 47562.500000                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 30153.339859                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 30153.339859                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 28634.628622                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 28634.628622                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     32224409                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.085323                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.085323                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.090060                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.090060                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16095.314606                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16095.314606                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53809.325082                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 53809.325082                       # average WriteReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 23587.956296                       # average WriteLineReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::total 23587.956296                       # average WriteLineReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16291.062223                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16291.062223                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 33388.888889                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 33388.888889                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 37889.669487                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 37889.669487                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 35663.668807                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 35663.668807                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     24419954                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs           1601607                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs           2093623                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    20.120048                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    11.663969                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks      7504086                       # number of writebacks
-system.cpu.dcache.writebacks::total           7504086                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4456599                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      4456599                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      9250788                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      9250788                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data         7056                       # number of WriteLineReq MSHR hits
-system.cpu.dcache.WriteLineReq_mshr_hits::total         7056                       # number of WriteLineReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       219268                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total       219268                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data     13714443                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total     13714443                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data     13714443                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total     13714443                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5124316                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      5124316                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2003239                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      2003239                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1163648                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total      1163648                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1226583                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::total      1226583                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       227441                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total       227441                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            8                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total            8                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      8354138                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      8354138                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      9517786                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9517786                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33678                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.ReadReq_mshr_uncacheable::total        33678                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33696                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total        33696                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67374                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total        67374                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  84959954500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  84959954500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  77558080846                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  77558080846                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  23723735000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  23723735000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  50708992789                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  50708992789                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3202218000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3202218000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       372500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       372500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 213227028135                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 213227028135                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 236950763135                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 236950763135                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6192056000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6192056000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6192056000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   6192056000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032685                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032685                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014359                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014359                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.751649                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.751649                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.787557                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.787557                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.060778                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.060778                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.writebacks::writebacks     10319802                       # number of writebacks
+system.cpu.dcache.writebacks::total          10319802                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      5736139                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      5736139                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data     15576096                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total     15576096                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data         6849                       # number of WriteLineReq MSHR hits
+system.cpu.dcache.WriteLineReq_mshr_hits::total         6849                       # number of WriteLineReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       265006                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total       265006                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data     21319084                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total     21319084                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data     21319084                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total     21319084                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7051922                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7051922                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      3072420                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      3072420                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      2034687                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total      2034687                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1263657                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::total      1263657                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       283363                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total       283363                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            9                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total            9                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data     11387999                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total     11387999                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data     13422686                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total     13422686                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33692                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.ReadReq_mshr_uncacheable::total        33692                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33703                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total        33703                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67395                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total        67395                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 110827450000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 110827450000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 147154305213                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 147154305213                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  32559356000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  32559356000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  28426038502                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  28426038502                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   4117736500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   4117736500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       291500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       291500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 286407793715                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 286407793715                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 318967149715                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 318967149715                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6225596500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6225596500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6225596500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   6225596500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.035306                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.035306                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.016882                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.016882                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.812301                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.812301                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.787574                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.787574                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.053048                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.053048                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000002                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.028048                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.028048                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.031790                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.031790                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16579.764890                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16579.764890                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38716.339311                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38716.339311                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 20387.380892                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 20387.380892                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 41341.672589                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 41341.672589                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14079.334860                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14079.334860                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 46562.500000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 46562.500000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25523.522371                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25523.522371                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24895.575834                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 24895.575834                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183860.561791                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183860.561791                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91905.720308                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91905.720308                       # average overall mshr uncacheable latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements          15134592                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.928988                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           340756209                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs          15135104                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             22.514296                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       20447572500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.928988                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.999861                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.999861                       # Average percentage of cache occupancy
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.029708                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.029708                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.034789                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.034789                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15715.921135                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15715.921135                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47895.243884                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47895.243884                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16002.144802                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16002.144802                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 22495.058787                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 22495.058787                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14531.666096                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14531.666096                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 32388.888889                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 32388.888889                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25149.966532                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25149.966532                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23763.287744                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 23763.287744                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184779.665796                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184779.665796                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92374.753320                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92374.753320                       # average overall mshr uncacheable latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements          16891256                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.956016                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           444441322                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs          16891768                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             26.311119                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       13164566500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.956016                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.999914                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.999914                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          124                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          299                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           89                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          114                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          286                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          112                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         371779021                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        371779021                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst    340756209                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       340756209                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     340756209                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        340756209                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    340756209                       # number of overall hits
-system.cpu.icache.overall_hits::total       340756209                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst     15887482                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total      15887482                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst     15887482                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total       15887482                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst     15887482                       # number of overall misses
-system.cpu.icache.overall_misses::total      15887482                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 214918228873                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 214918228873                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 214918228873                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 214918228873                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 214918228873                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 214918228873                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    356643691                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    356643691                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    356643691                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    356643691                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    356643691                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    356643691                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.044547                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.044547                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.044547                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.044547                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.044547                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.044547                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13527.519897                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13527.519897                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13527.519897                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13527.519897                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13527.519897                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13527.519897                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        24649                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses         479012658                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        479012658                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst    444441322                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       444441322                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     444441322                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        444441322                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    444441322                       # number of overall hits
+system.cpu.icache.overall_hits::total       444441322                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst     17679342                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total      17679342                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst     17679342                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total       17679342                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst     17679342                       # number of overall misses
+system.cpu.icache.overall_misses::total      17679342                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 234300237389                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 234300237389                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 234300237389                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 234300237389                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 234300237389                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 234300237389                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    462120664                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    462120664                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    462120664                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    462120664                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    462120664                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    462120664                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.038257                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.038257                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.038257                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.038257                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.038257                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.038257                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13252.769101                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13252.769101                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13252.769101                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13252.769101                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13252.769101                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13252.769101                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        16371                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              1517                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              1212                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    16.248517                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    13.507426                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks     15134592                       # number of writebacks
-system.cpu.icache.writebacks::total          15134592                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst       752151                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total       752151                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst       752151                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total       752151                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst       752151                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total       752151                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst     15135331                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total     15135331                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst     15135331                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total     15135331                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst     15135331                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total     15135331                       # number of overall MSHR misses
+system.cpu.icache.writebacks::writebacks     16891256                       # number of writebacks
+system.cpu.icache.writebacks::total          16891256                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst       787348                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total       787348                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst       787348                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total       787348                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst       787348                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total       787348                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst     16891994                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total     16891994                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst     16891994                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total     16891994                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst     16891994                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total     16891994                       # number of overall MSHR misses
 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        21294                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.ReadReq_mshr_uncacheable::total        21294                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        21294                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses::total        21294                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192625378387                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 192625378387                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192625378387                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 192625378387                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192625378387                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 192625378387                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   2684938500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   2684938500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   2684938500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total   2684938500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.042438                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.042438                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.042438                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.042438                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.042438                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.042438                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12726.869230                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12726.869230                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12726.869230                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12726.869230                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12726.869230                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12726.869230                       # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126088.968724                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126088.968724                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126088.968724                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126088.968724                       # average overall mshr uncacheable latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements          1148622                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65301.900403                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           46289210                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1211379                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            38.211996                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       4512200500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 37189.560843                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   293.778433                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   476.562000                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  7800.369043                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 19541.630085                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.567468                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004483                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.007272                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.119024                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.298182                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.996428                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023          234                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        62523                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4          234                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           67                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          564                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2712                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5162                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54018                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.003571                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.954025                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        410396361                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       410396361                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       787478                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       297374                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1084852                       # number of ReadReq hits
-system.cpu.l2cache.WritebackDirty_hits::writebacks      7504086                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      7504086                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks     15131991                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total     15131991                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data         9360                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total         9360                       # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            4                       # number of SCUpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::total            4                       # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1568311                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1568311                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     15051780                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total     15051780                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6254855                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      6254855                       # number of ReadSharedReq hits
-system.cpu.l2cache.InvalidateReq_hits::cpu.data       727039                       # number of InvalidateReq hits
-system.cpu.l2cache.InvalidateReq_hits::total       727039                       # number of InvalidateReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker       787478                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker       297374                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst     15051780                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      7823166                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total        23959798                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker       787478                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker       297374                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst     15051780                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      7823166                       # number of overall hits
-system.cpu.l2cache.overall_hits::total       23959798                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         3559                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         3326                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         6885                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data        34185                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total        34185                       # number of UpgradeReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 210691534398                       # number of ReadReq MSHR miss cycles
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+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 210691534398                       # number of demand (read+write) MSHR miss cycles
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+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 210691534398                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 210691534398                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   1610722500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   1610722500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   1610722500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total   1610722500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.036553                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.036553                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.036553                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.036553                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.036553                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.036553                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12472.863440                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12472.863440                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12472.863440                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12472.863440                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12472.863440                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12472.863440                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75642.082277                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75642.082277                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75642.082277                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75642.082277                       # average overall mshr uncacheable latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.replacements          2372905                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65457.290128                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           58959202                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          2435994                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            24.203345                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle       2520974000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks  9397.889077                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   196.572797                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   228.214718                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  6628.882550                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 49005.730985                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.143400                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.002999                       # Average percentage of cache occupancy
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+system.cpu.l2cache.tags.occ_task_id_blocks::1024        62867                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4          222                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           36                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          376                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1017                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5588                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55850                       # Occupied blocks per task id
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+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.959274                       # Percentage of cache occupancy per task id
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+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
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+system.cpu.l2cache.WritebackDirty_hits::writebacks     10319802                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total     10319802                       # number of WritebackDirty hits
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+system.cpu.l2cache.InvalidateReq_hits::total       673558                       # number of InvalidateReq hits
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 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            4                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            4                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       394921                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       394921                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        83338                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        83338                       # number of ReadCleanReq misses
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+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85598.588427                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85598.588427                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 90470.035629                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 90470.035629                       # average ReadSharedReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data     0.818507                       # average InvalidateReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::total     0.818507                       # average InvalidateReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89750.598831                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 89243.765729                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85598.588427                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92305.741758                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 91930.824377                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89750.598831                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 89243.765729                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85598.588427                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92305.741758                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 91930.824377                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks       962824                       # number of writebacks
-system.cpu.l2cache.writebacks::total           962824                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.dtb.walker            1                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
+system.cpu.l2cache.writebacks::writebacks      2095825                       # number of writebacks
+system.cpu.l2cache.writebacks::total          2095825                       # number of writebacks
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           21                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::total           21                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.dtb.walker            1                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.data           21                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           22                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.dtb.walker            1                       # number of overall MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           21                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data           21                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           22                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         3558                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         3326                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         6884                       # number of ReadReq MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            1                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total            1                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        34185                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total        34185                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.overall_mshr_hits::total           21                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker        10437                       # number of ReadReq MSHR misses
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+system.cpu.l2cache.ReadReq_mshr_misses::total        19179                       # number of ReadReq MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            3                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total            3                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         4078                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         4078                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            4                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            4                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       394921                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       394921                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        83338                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        83338                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       256994                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       256994                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       499544                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::total       499544                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         3558                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         3326                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        83338                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       651915                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       742137                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         3558                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         3326                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        83338                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       651915                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       742137                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data      1333352                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total      1333352                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        96984                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        96984                       # number of ReadCleanReq MSHR misses
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+system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       590099                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::total       590099                       # number of InvalidateReq MSHR misses
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 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        21294                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33678                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total        54972                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        33696                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33696                       # number of WriteReq MSHR uncacheable
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+system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33703                       # number of WriteReq MSHR uncacheable
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        21294                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67374                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total        88668                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    456305510                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    429144000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    885449510                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   2325232000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   2325232000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       277500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       277500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  51081891916                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  51081891916                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst  10406063168                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total  10406063168                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  33266030305                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  33266030305                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  34915200500                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  34915200500                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    456305510                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    429144000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  10406063168                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  84347922221                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  95639434899                       # number of demand (read+write) MSHR miss cycles
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-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    429144000                       # number of overall MSHR miss cycles
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-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  84347922221                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  95639434899                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   2418763500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5770936000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   8189699500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   2418763500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5770936000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   8189699500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.004498                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.011061                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.006306                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67395                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total        88689                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    832356501                       # number of ReadReq MSHR miss cycles
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+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     77850000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       181500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       181500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 110528159195                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 110528159195                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   7331831049                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   7331831049                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  34442081593                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  34442081593                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  12207320002                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  12207320002                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    832356501                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    692749000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   7331831049                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 144970240788                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 153827177338                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    832356501                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    692749000                       # number of overall MSHR miss cycles
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+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 144970240788                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 153827177338                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   1344547500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5804287500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   7148835000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   1344547500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5804287500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   7148835000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.008126                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.028090                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.012019                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.785050                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.785050                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.500000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.201159                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.201159                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005506                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005506                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.039465                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.039465                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.407265                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.407265                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.004498                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.011061                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005506                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.076921                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.030044                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.004498                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.011061                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005506                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.076921                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.030044                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 128247.754356                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 129027.059531                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 128624.275131                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68019.072693                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68019.072693                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        69375                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        69375                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129347.114780                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129347.114780                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124865.765533                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124865.765533                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 129442.828646                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 129442.828646                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69894.144460                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69894.144460                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 128247.754356                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 129027.059531                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124865.765533                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 129384.846523                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128870.322998                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 128247.754356                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 129027.059531                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124865.765533                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129384.846523                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128870.322998                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.968724                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171356.256310                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148979.471367                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.968724                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85655.237926                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 92363.643028                       # average overall mshr uncacheable latency
-system.cpu.toL2Bus.snoop_filter.tot_requests     50407203                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests     25570213                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3413                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         2115                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2115                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.094837                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.094837                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.444444                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.444444                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.437822                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.437822                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005741                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005741                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.045756                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.045756                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.466977                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.466977                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.008126                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.028090                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005741                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.142052                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.060787                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.008126                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.028090                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005741                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.142052                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.060787                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 79750.551020                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 79243.765729                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 79519.552688                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19090.240314                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19090.240314                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        45375                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        45375                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82894.958867                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82894.958867                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75598.356935                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75598.356935                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80471.401186                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80471.401186                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20686.901693                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20686.901693                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 79750.551020                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 79243.765729                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75598.356935                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82306.041929                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81931.089559                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 79750.551020                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 79243.765729                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75598.356935                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82306.041929                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81931.089559                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63142.082277                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172274.946575                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 130011.912123                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63142.082277                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86123.414200                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 80605.655718                       # average overall mshr uncacheable latency
+system.cpu.toL2Bus.snoop_filter.tot_requests     62084255                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests     31529230                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3455                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         2096                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2096                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadReq        1618708                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      23266675                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         33696                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        33696                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      8573574                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean     15134592                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      2391693                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq        43548                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq            8                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp        43556                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1963232                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1963232                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq     15135331                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      6520715                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq      1333247                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateResp      1226583                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     45447628                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     29327152                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       726647                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1928826                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          77430253                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1937602080                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1022907422                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2405600                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6328296                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         2969243398                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     1852603                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic              72285944                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples     27912596                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.024958                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.155996                       # Request fanout histogram
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadReq        2242102                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      28488845                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         33703                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        33703                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty     12415627                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean     16891256                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      3619797                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq        43003                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq            9                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp        43012                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      3045422                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      3045422                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq     16891994                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      9356331                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq      1295806                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateResp      1263657                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     50717623                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     41210208                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       777423                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      3005376                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          95710630                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   2162455328                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1454268658                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2489712                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side     10275752                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         3629489450                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     2999840                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic             138927432                       # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples     35281285                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.026592                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.160887                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           27215961     97.50%     97.50% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             696635      2.50%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           34343098     97.34%     97.34% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             938187      2.66%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       27912596                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    48339894491                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       35281285                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    58941748976                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy      1459384                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy      1470395                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy   22733591738                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy   25369728010                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   13401353655                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   19308156079                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy     426266814                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy     466604190                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy    1138134788                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy    1721722349                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq                40293                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40293                       # Transaction distribution
+system.iobus.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.iobus.trans_dist::ReadReq                40300                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40300                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
 system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
@@ -1618,11 +1612,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230944                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230944                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230958                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230958                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353728                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353742                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
@@ -1637,16 +1631,16 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334208                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334208                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334264                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334264                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492128                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             41884500                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7492184                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             41887500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                11500                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               345000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               337000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer3.occupancy                 9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
@@ -1654,85 +1648,85 @@ system.iobus.reqLayer4.occupancy                 9500                       # La
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy                9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer14.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer15.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               14500                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               14000                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            25117000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            25106500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer24.occupancy            36500500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           567323274                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           568968673                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147704000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147718000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements               115453                       # number of replacements
-system.iocache.tags.tagsinuse               10.423128                       # Cycle average of tags in use
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.replacements               115465                       # number of replacements
+system.iocache.tags.tagsinuse               10.450543                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115469                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115481                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13098782503000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.544201                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.878927                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.221513                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.429933                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.651446                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13091229344000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     5.877255                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     4.573288                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.367328                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.285830                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.653159                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039605                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039605                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.tag_accesses              1039668                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039668                       # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8808                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8845                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8815                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8852                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide       115472                       # number of demand (read+write) misses
-system.iocache.demand_misses::total            115512                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide       115479                       # number of demand (read+write) misses
+system.iocache.demand_misses::total            115519                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide       115472                       # number of overall misses
-system.iocache.overall_misses::total           115512                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5076000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1670063987                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1675139987                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide       115479                       # number of overall misses
+system.iocache.overall_misses::total           115519                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5086000                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1629675592                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1634761592                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  13414774287                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  13414774287                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5427000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide  15084838274                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  15090265274                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5427000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide  15084838274                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  15090265274                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  12811525081                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  12811525081                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5437000                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide  14441200673                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  14446637673                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5437000                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide  14441200673                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total  14446637673                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8808                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8845                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8815                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8852                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide       115472                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total          115512                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide       115479                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total          115519                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide       115472                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total         115512                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide       115479                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total         115519                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -1746,53 +1740,53 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137189.189189                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 189607.627952                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 189388.353533                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 184875.279864                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 184677.089019                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125766.653107                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 125766.653107                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       135675                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 130636.329794                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 130638.074607                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       135675                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 130636.329794                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 130638.074607                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         33964                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120111.050411                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 120111.050411                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet       135925                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 125054.777691                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 125058.541651                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet       135925                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 125054.777691                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 125058.541651                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         32070                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3510                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3415                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.676353                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.390922                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.writebacks::writebacks          106630                       # number of writebacks
 system.iocache.writebacks::total               106630                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8808                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8845                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8815                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8852                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide       115472                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total       115512                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide       115479                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total       115519                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide       115472                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total       115512                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3226000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1229663987                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1232889987                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide       115479                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total       115519                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3236000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1188925592                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1192161592                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8076516803                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   8076516803                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3427000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   9306180790                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   9309607790                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3427000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   9306180790                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   9309607790                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7471582182                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   7471582182                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3437000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   8660507774                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   8663944774                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3437000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   8660507774                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   8663944774                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -1806,89 +1800,95 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87189.189189                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139607.627952                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 139388.353533                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134875.279864                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 134677.089019                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75719.238009                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75719.238009                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85675                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 80592.531436                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 80594.291416                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85675                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 80592.531436                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 80594.291416                       # average overall mshr miss latency
-system.membus.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq               54972                       # Transaction distribution
-system.membus.trans_dist::ReadResp             411033                       # Transaction distribution
-system.membus.trans_dist::WriteReq              33696                       # Transaction distribution
-system.membus.trans_dist::WriteResp             33696                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1069454                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           193565                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            34895                       # Transaction distribution
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70047.834152                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70047.834152                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85925                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 74996.386997                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 75000.171175                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85925                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 74996.386997                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 75000.171175                       # average overall mshr miss latency
+system.membus.snoop_filter.tot_requests       5074419                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests      2524015                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests         3002                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
+system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadReq               54986                       # Transaction distribution
+system.membus.trans_dist::ReadResp             608005                       # Transaction distribution
+system.membus.trans_dist::WriteReq              33703                       # Transaction distribution
+system.membus.trans_dist::WriteResp             33703                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      2202455                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           284620                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4643                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              4                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               8                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            394310                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           394310                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        356061                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        606112                       # Transaction distribution
+system.membus.trans_dist::ReadExReq           1332798                       # Transaction distribution
+system.membus.trans_dist::ReadExResp          1332798                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        553019                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        696755                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6858                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3212019                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3341639                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237917                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       237917                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                3579556                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6900                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      6767333                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      6896995                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237693                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       237693                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                7134688                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          420                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13716                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    109397260                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    109567230                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7269248                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7269248                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               116836478                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             2560                       # Total snoops (count)
-system.membus.snoopTraffic                     163328                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples           2743103                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13800                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    254577484                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    254747538                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7253696                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7253696                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               262001234                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             2809                       # Total snoops (count)
+system.membus.snoopTraffic                     179264                       # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples           2675908                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.013150                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.113918                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 2743103    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 2640719     98.68%     98.68% # Request fanout histogram
+system.membus.snoop_fanout::1                   35189      1.32%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2743103                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           103939500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             2675908                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           103923000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               32500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5573000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5620000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          7172212711                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy         14223305475                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         4075256665                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy        10050154677                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           44789891                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           44814659                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
 system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
 system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
 system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
 system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
 system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
@@ -1898,11 +1898,11 @@ system.realview.ethernet.descDMAReads               0                       # Nu
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
 system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth             151                       # Total Bandwidth (bits/s)
+system.realview.ethernet.totBandwidth             150                       # Total Bandwidth (bits/s)
 system.realview.ethernet.totPackets                 3                       # Total Packets
 system.realview.ethernet.totBytes                 966                       # Total Bytes
 system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth              151                       # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txBandwidth              150                       # Transmit Bandwidth (bits/s)
 system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
 system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
 system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
@@ -1931,30 +1931,30 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
 system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000                       # Cumulative time (in ticks) in various power states
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000                       # Cumulative time (in ticks) in various power states
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    16114                       # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce                    17131                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt
index b33124edd..a22c43be0 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt
@@ -1,58 +1,58 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                 51.111167                       # Number of seconds simulated
-sim_ticks                                51111167192000                       # Number of ticks simulated
-final_tick                               51111167192000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                51111167268500                       # Number of ticks simulated
+final_tick                               51111167268500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 942442                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1107573                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            49042304128                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 674172                       # Number of bytes of host memory used
-host_seconds                                  1042.19                       # Real time elapsed on the host
-sim_insts                                   982198638                       # Number of instructions simulated
-sim_ops                                    1154296340                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 926682                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1089052                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            48222226969                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 681368                       # Number of bytes of host memory used
+host_seconds                                  1059.91                       # Real time elapsed on the host
+sim_insts                                   982198023                       # Number of instructions simulated
+sim_ops                                    1154295627                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.dtb.walker       414464                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker       373568                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           5484148                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          74913608                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           5483444                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          74913992                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide        436800                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             81622588                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      5484148                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5484148                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks    103278016                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             81622268                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      5483444                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         5483444                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks    103278528                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         103298596                       # Number of bytes written to this memory
+system.physmem.bytes_written::total         103299108                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.dtb.walker         6476                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker         5837                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             126097                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1170538                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             126086                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1170544                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide           6825                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1315773                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1613719                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total               1315768                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1613727                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1616292                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1616300                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.dtb.walker           8109                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker           7309                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               107298                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1465699                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               107285                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1465707                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide             8546                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1596962                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          107298                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             107298                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2020655                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1596956                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          107285                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             107285                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2020665                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                 403                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2021057                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2020655                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2021067                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2020665                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker          8109                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker          7309                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              107298                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1466102                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              107285                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1466110                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide            8546                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3618019                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
+system.physmem.bw_total::total                3618023                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 system.realview.nvmem.bytes_read::cpu.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
@@ -69,9 +69,9 @@ system.realview.nvmem.bw_inst_read::total            2                       # I
 system.realview.nvmem.bw_total::cpu.inst            2                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total               3                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
@@ -79,7 +79,7 @@ system.cf0.dma_write_full_pages                  1666                       # Nu
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -109,30 +109,30 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks                    266586                       # Table walker walks requested
-system.cpu.dtb.walker.walksLong                266586                       # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walkWaitTime::samples       266586                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0          266586    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total       266586                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.walks                    266581                       # Table walker walks requested
+system.cpu.dtb.walker.walksLong                266581                       # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walkWaitTime::samples       266581                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0          266581    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total       266581                       # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walksPending::samples     22846000                       # Table walker pending requests distribution
 system.cpu.dtb.walker.walksPending::0        22846000    100.00%    100.00% # Table walker pending requests distribution
 system.cpu.dtb.walker.walksPending::total     22846000                       # Table walker pending requests distribution
 system.cpu.dtb.walker.walkPageSizes::4K        204774     89.35%     89.35% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M         24416     10.65%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total       229190                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       266586                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkPageSizes::2M         24411     10.65%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total       229185                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       266581                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total       266586                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       229190                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total       266581                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       229185                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total       229190                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total       495776                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total       229185                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total       495766                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                    183544097                       # DTB read hits
-system.cpu.dtb.read_misses                     195348                       # DTB read misses
-system.cpu.dtb.write_hits                   167774773                       # DTB write hits
+system.cpu.dtb.read_hits                    183543984                       # DTB read hits
+system.cpu.dtb.read_misses                     195343                       # DTB read misses
+system.cpu.dtb.write_hits                   167774645                       # DTB write hits
 system.cpu.dtb.write_misses                     71238                       # DTB write misses
 system.cpu.dtb.flush_tlb                           11                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
@@ -140,16 +140,16 @@ system.cpu.dtb.flush_tlb_mva_asid               49771                       # Nu
 system.cpu.dtb.flush_tlb_asid                    1139                       # Number of times TLB was flushed by ASID
 system.cpu.dtb.flush_entries                    82439                       # Number of entries that have been flushed from TLB
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   9079                       # Number of TLB faults due to prefetch
+system.cpu.dtb.prefetch_faults                   9074                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
 system.cpu.dtb.perms_faults                     21651                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                183739445                       # DTB read accesses
-system.cpu.dtb.write_accesses               167846011                       # DTB write accesses
+system.cpu.dtb.read_accesses                183739327                       # DTB read accesses
+system.cpu.dtb.write_accesses               167845883                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                         351318870                       # DTB hits
-system.cpu.dtb.misses                          266586                       # DTB misses
-system.cpu.dtb.accesses                     351585456                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.hits                         351318629                       # DTB hits
+system.cpu.dtb.misses                          266581                       # DTB misses
+system.cpu.dtb.accesses                     351585210                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -179,7 +179,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                    126834                       # Table walker walks requested
 system.cpu.itb.walker.walksLong                126834                       # Table walker walks initiated with long descriptors
 system.cpu.itb.walker.walkWaitTime::samples       126834                       # Table walker wait (enqueue to first request) latency
@@ -198,7 +198,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0
 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       114696                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::total       114696                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin::total       241530                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                    982675484                       # ITB inst hits
+system.cpu.itb.inst_hits                    982674869                       # ITB inst hits
 system.cpu.itb.inst_misses                     126834                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
@@ -215,14 +215,14 @@ system.cpu.itb.domain_faults                        0                       # Nu
 system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                982802318                       # ITB inst accesses
-system.cpu.itb.hits                         982675484                       # DTB hits
+system.cpu.itb.inst_accesses                982801703                       # ITB inst accesses
+system.cpu.itb.hits                         982674869                       # DTB hits
 system.cpu.itb.misses                          126834                       # DTB misses
-system.cpu.itb.accesses                     982802318                       # DTB accesses
+system.cpu.itb.accesses                     982801703                       # DTB accesses
 system.cpu.numPwrStateTransitions               33550                       # Number of power state transitions
 system.cpu.pwrStateClkGateDist::samples         16775                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::mean     3012440883.104620                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::stdev    59942517995.825706                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean     3012440908.824083                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev    59942517661.771744                       # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::underflows         7454     44.44%     44.44% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::1000-5e+10         9286     55.36%     99.79% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::5e+10-1e+11            4      0.02%     99.82% # Distribution of time spent in the clock gated state
@@ -235,40 +235,40 @@ system.cpu.pwrStateClkGateDist::4.5e+11-5e+11            1      0.01%     99.89%
 system.cpu.pwrStateClkGateDist::5.5e+11-6e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::overflows           18      0.11%    100.00% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::max_value 1988782948204                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::max_value 1988782931704                       # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::total           16775                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateResidencyTicks::ON    577471377920                       # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::CLK_GATED 50533695814080                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                     102222351160                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON    577471022976                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 50533696245524                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                     102222351313                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                    16775                       # number of quiesce instructions executed
-system.cpu.committedInsts                   982198638                       # Number of instructions committed
-system.cpu.committedOps                    1154296340                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses            1057877800                       # Number of integer alu accesses
+system.cpu.committedInsts                   982198023                       # Number of instructions committed
+system.cpu.committedOps                    1154295627                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses            1057877135                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                 881349                       # Number of float alu accesses
-system.cpu.num_func_calls                    56833909                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts    151622723                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                   1057877800                       # number of integer instructions
+system.cpu.num_func_calls                    56833843                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts    151622640                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                   1057877135                       # number of integer instructions
 system.cpu.num_fp_insts                        881349                       # number of float instructions
-system.cpu.num_int_register_reads          1560754548                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          840513636                       # number of times the integer registers were written
+system.cpu.num_int_register_reads          1560753668                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          840513151                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads              1419767                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes              748560                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            264017562                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes           263439787                       # number of times the CC registers were written
-system.cpu.num_mem_refs                     351538306                       # number of memory refs
-system.cpu.num_load_insts                   183711405                       # Number of load instructions
-system.cpu.num_store_insts                  167826901                       # Number of store instructions
-system.cpu.num_idle_cycles               101067408214.617065                       # Number of idle cycles
-system.cpu.num_busy_cycles               1154942945.382940                       # Number of busy cycles
+system.cpu.num_cc_register_reads            264017457                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes           263439679                       # number of times the CC registers were written
+system.cpu.num_mem_refs                     351538055                       # number of memory refs
+system.cpu.num_load_insts                   183711282                       # Number of load instructions
+system.cpu.num_store_insts                  167826773                       # Number of store instructions
+system.cpu.num_idle_cycles               101067409077.505173                       # Number of idle cycles
+system.cpu.num_busy_cycles               1154942235.494823                       # Number of busy cycles
 system.cpu.not_idle_fraction                 0.011298                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.988702                       # Percentage of idle cycles
-system.cpu.Branches                         219532347                       # Number of branches fetched
+system.cpu.Branches                         219532189                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     1      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                 800829907     69.34%     69.34% # Class of executed instruction
-system.cpu.op_class::IntMult                  2354386      0.20%     69.54% # Class of executed instruction
+system.cpu.op_class::IntAlu                 800829443     69.34%     69.34% # Class of executed instruction
+system.cpu.op_class::IntMult                  2354388      0.20%     69.54% # Class of executed instruction
 system.cpu.op_class::IntDiv                    100543      0.01%     69.55% # Class of executed instruction
 system.cpu.op_class::FloatAdd                       0      0.00%     69.55% # Class of executed instruction
 system.cpu.op_class::FloatCmp                       0      0.00%     69.55% # Class of executed instruction
@@ -296,17 +296,17 @@ system.cpu.op_class::SimdFloatMisc             107822      0.01%     69.56% # Cl
 system.cpu.op_class::SimdFloatMult                  0      0.00%     69.56% # Class of executed instruction
 system.cpu.op_class::SimdFloatMultAcc               0      0.00%     69.56% # Class of executed instruction
 system.cpu.op_class::SimdFloatSqrt                  0      0.00%     69.56% # Class of executed instruction
-system.cpu.op_class::MemRead                183711405     15.91%     85.47% # Class of executed instruction
-system.cpu.op_class::MemWrite               167826901     14.53%    100.00% # Class of executed instruction
+system.cpu.op_class::MemRead                183711282     15.91%     85.47% # Class of executed instruction
+system.cpu.op_class::MemWrite               167826773     14.53%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                 1154931007                       # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements          11605970                       # number of replacements
+system.cpu.op_class::total                 1154930294                       # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements          11606056                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.999719                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           339855114                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs          11606482                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             29.281492                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.total_refs           339854782                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs          11606568                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             29.281247                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle          33050500                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.tags.occ_blocks::cpu.data   511.999719                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999999                       # Average percentage of cache occupancy
@@ -316,87 +316,87 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0          199
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          297                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           16                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1417452931                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1417452931                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data    171110382                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       171110382                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    159073547                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      159073547                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       424481                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        424481                       # number of SoftPFReq hits
+system.cpu.dcache.tags.tag_accesses        1417452033                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1417452033                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data    171110167                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       171110167                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    159090000                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      159090000                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       424478                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        424478                       # number of SoftPFReq hits
 system.cpu.dcache.WriteLineReq_hits::cpu.data       336283                       # number of WriteLineReq hits
 system.cpu.dcache.WriteLineReq_hits::total       336283                       # number of WriteLineReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      4303643                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      4303643                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data      4555646                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      4555646                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     330520212                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        330520212                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    330944693                       # number of overall hits
-system.cpu.dcache.overall_hits::total       330944693                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      6002738                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       6002738                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2568126                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2568126                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data      1586184                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total      1586184                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      4303639                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      4303639                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      4555644                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      4555644                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     330536450                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        330536450                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    330960928                       # number of overall hits
+system.cpu.dcache.overall_hits::total       330960928                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      6002834                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       6002834                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2551547                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2551547                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data      1586190                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total      1586190                       # number of SoftPFReq misses
 system.cpu.dcache.WriteLineReq_misses::cpu.data      1246772                       # number of WriteLineReq misses
 system.cpu.dcache.WriteLineReq_misses::total      1246772                       # number of WriteLineReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data       253806                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total       253806                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data       253808                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total       253808                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            1                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      9817636                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        9817636                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     11403820                       # number of overall misses
-system.cpu.dcache.overall_misses::total      11403820                       # number of overall misses
-system.cpu.dcache.ReadReq_accesses::cpu.data    177113120                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    177113120                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    161641673                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    161641673                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data      2010665                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total      2010665                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data      9801153                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        9801153                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     11387343                       # number of overall misses
+system.cpu.dcache.overall_misses::total      11387343                       # number of overall misses
+system.cpu.dcache.ReadReq_accesses::cpu.data    177113001                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    177113001                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    161641547                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    161641547                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data      2010668                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total      2010668                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.WriteLineReq_accesses::cpu.data      1583055                       # number of WriteLineReq accesses(hits+misses)
 system.cpu.dcache.WriteLineReq_accesses::total      1583055                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4557449                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      4557449                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data      4555647                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      4555647                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    340337848                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    340337848                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    342348513                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    342348513                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.033892                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.033892                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015888                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.015888                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.788885                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.788885                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4557447                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      4557447                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data      4555645                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      4555645                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    340337603                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    340337603                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    342348271                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    342348271                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.033893                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.033893                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015785                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.015785                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.788887                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.788887                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.787573                       # miss rate for WriteLineReq accesses
 system.cpu.dcache.WriteLineReq_miss_rate::total     0.787573                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.055690                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.055690                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.055691                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.055691                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000000                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.028847                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.028847                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.033311                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.033311                       # miss rate for overall accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.028798                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.028798                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.033262                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.033262                       # miss rate for overall accesses
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks      8916642                       # number of writebacks
-system.cpu.dcache.writebacks::total           8916642                       # number of writebacks
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements          14265273                       # number of replacements
+system.cpu.dcache.writebacks::writebacks      8918956                       # number of writebacks
+system.cpu.dcache.writebacks::total           8918956                       # number of writebacks
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements          14265255                       # number of replacements
 system.cpu.icache.tags.tagsinuse           511.984599                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           968524390                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs          14265785                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             67.891419                       # Average number of references to valid blocks.
+system.cpu.icache.tags.total_refs           968523793                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs          14265767                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             67.891463                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle        6061932500                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.tags.occ_blocks::cpu.inst   511.984599                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.999970                       # Average percentage of cache occupancy
@@ -406,27 +406,27 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0          184
 system.cpu.icache.tags.age_task_id_blocks_1024::1          239                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2           89                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         997055970                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        997055970                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst    968524390                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       968524390                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     968524390                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        968524390                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    968524390                       # number of overall hits
-system.cpu.icache.overall_hits::total       968524390                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst     14265790                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total      14265790                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst     14265790                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total       14265790                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst     14265790                       # number of overall misses
-system.cpu.icache.overall_misses::total      14265790                       # number of overall misses
-system.cpu.icache.ReadReq_accesses::cpu.inst    982790180                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    982790180                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    982790180                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    982790180                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    982790180                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    982790180                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses         997055337                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        997055337                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst    968523793                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       968523793                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     968523793                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        968523793                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    968523793                       # number of overall hits
+system.cpu.icache.overall_hits::total       968523793                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst     14265772                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total      14265772                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst     14265772                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total       14265772                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst     14265772                       # number of overall misses
+system.cpu.icache.overall_misses::total      14265772                       # number of overall misses
+system.cpu.icache.ReadReq_accesses::cpu.inst    982789565                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    982789565                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    982789565                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    982789565                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    982789565                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    982789565                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014516                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.014516                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.014516                       # miss rate for demand accesses
@@ -439,200 +439,200 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks     14265273                       # number of writebacks
-system.cpu.icache.writebacks::total          14265273                       # number of writebacks
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.writebacks::writebacks     14265255                       # number of writebacks
+system.cpu.icache.writebacks::total          14265255                       # number of writebacks
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements          1725823                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65319.568119                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           46895862                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1788839                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            26.215809                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle        395986000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 37200.621218                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   312.625793                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   449.901085                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  6075.914096                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 21280.505928                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.567636                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004770                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006865                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.092711                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.324715                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.996698                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023          317                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        62699                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4          317                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          136                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          608                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2778                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4924                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54253                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004837                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.956711                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        425623617                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       425623617                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       509088                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       255953                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         765041                       # number of ReadReq hits
-system.cpu.l2cache.WritebackDirty_hits::writebacks      8916642                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      8916642                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks     14263696                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total     14263696                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data        11204                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total        11204                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1689386                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1689386                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     14182781                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total     14182781                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      7498617                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      7498617                       # number of ReadSharedReq hits
-system.cpu.l2cache.InvalidateReq_hits::cpu.data       694560                       # number of InvalidateReq hits
-system.cpu.l2cache.InvalidateReq_hits::total       694560                       # number of InvalidateReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker       509088                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker       255953                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst     14182781                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      9188003                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total        24135825                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker       509088                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker       255953                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst     14182781                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      9188003                       # number of overall hits
-system.cpu.l2cache.overall_hits::total       24135825                       # number of overall hits
+system.cpu.l2cache.tags.tagsinuse        65403.901916                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           49389938                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1788899                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            27.609126                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle        395496000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks  9615.361386                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   436.090806                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   495.840367                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  6075.388739                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 48781.220619                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.146719                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.006654                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.007566                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.092703                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.744342                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.997984                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023          373                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        62703                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4          373                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          110                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          329                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1444                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5122                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55698                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.005692                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.956772                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        422564531                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       422564531                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       480106                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       237369                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         717475                       # number of ReadReq hits
+system.cpu.l2cache.WritebackDirty_hits::writebacks      8918956                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      8918956                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks     14263678                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total     14263678                       # number of WritebackClean hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data        30692                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total        30692                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1689371                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1689371                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     14182774                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total     14182774                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      7498712                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      7498712                       # number of ReadSharedReq hits
+system.cpu.l2cache.InvalidateReq_hits::cpu.data       694558                       # number of InvalidateReq hits
+system.cpu.l2cache.InvalidateReq_hits::total       694558                       # number of InvalidateReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker       480106                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker       237369                       # number of demand (read+write) hits
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+system.cpu.l2cache.demand_hits::cpu.data      9188083                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total        24088332                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker       480106                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker       237369                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst     14182774                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      9188083                       # number of overall hits
+system.cpu.l2cache.overall_hits::total       24088332                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         6476                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         5837                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total        12313                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data        39927                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total        39927                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data         3878                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total         3878                       # number of UpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            1                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            1                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       827609                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       827609                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        83009                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        83009                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       344111                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       344111                       # number of ReadSharedReq misses
-system.cpu.l2cache.InvalidateReq_misses::cpu.data       552212                       # number of InvalidateReq misses
-system.cpu.l2cache.InvalidateReq_misses::total       552212                       # number of InvalidateReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       827606                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       827606                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        82998                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total        82998                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       344120                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       344120                       # number of ReadSharedReq misses
+system.cpu.l2cache.InvalidateReq_misses::cpu.data       552214                       # number of InvalidateReq misses
+system.cpu.l2cache.InvalidateReq_misses::total       552214                       # number of InvalidateReq misses
 system.cpu.l2cache.demand_misses::cpu.dtb.walker         6476                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.itb.walker         5837                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        83009                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      1171720                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       1267042                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst        82998                       # number of demand (read+write) misses
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+system.cpu.l2cache.demand_misses::total       1267037                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.dtb.walker         6476                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.itb.walker         5837                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        83009                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      1171720                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1267042                       # number of overall misses
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       515564                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       261790                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       777354                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      8916642                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total      8916642                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks     14263696                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total     14263696                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data        51131                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total        51131                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.overall_misses::cpu.inst        82998                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      1171726                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      1267037                       # number of overall misses
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       486582                       # number of ReadReq accesses(hits+misses)
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+system.cpu.l2cache.ReadReq_accesses::total       729788                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      8918956                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      8918956                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks     14263678                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total     14263678                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data        34570                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total        34570                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            1                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::total            1                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      2516995                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      2516995                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     14265790                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total     14265790                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7842728                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      7842728                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      2516977                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      2516977                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     14265772                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total     14265772                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7842832                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      7842832                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1246772                       # number of InvalidateReq accesses(hits+misses)
 system.cpu.l2cache.InvalidateReq_accesses::total      1246772                       # number of InvalidateReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker       515564                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker       261790                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst     14265790                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data     10359723                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total     25402867                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker       515564                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker       261790                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst     14265790                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data     10359723                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total     25402867                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.012561                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.022296                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.015840                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.780877                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.780877                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker       486582                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker       243206                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst     14265772                       # number of demand (read+write) accesses
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+system.cpu.l2cache.demand_accesses::total     25355369                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker       486582                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker       243206                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst     14265772                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data     10359809                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total     25355369                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.013309                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.024000                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.016872                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.112178                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.112178                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.328808                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.328808                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005819                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005819                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.043876                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.043876                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.442913                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::total     0.442913                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.012561                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.022296                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005819                       # miss rate for demand accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.328810                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.328810                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005818                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005818                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.043877                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.043877                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.442915                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::total     0.442915                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.013309                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.024000                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005818                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.113103                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.049878                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.012561                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.022296                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005819                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.049971                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.013309                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.024000                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005818                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.113103                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.049878                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.049971                       # miss rate for overall accesses
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks      1507088                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1507088                       # number of writebacks
-system.cpu.toL2Bus.snoop_filter.tot_requests     52384615                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests     26512337                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.writebacks::writebacks      1507096                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1507096                       # number of writebacks
+system.cpu.toL2Bus.snoop_filter.tot_requests     52368206                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests     26495860                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1744                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         2693                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2693                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         2694                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2694                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadReq        1229989                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      23338507                       # Transaction distribution
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadReq        1229979                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      23338583                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         33606                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        33606                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      8916642                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean     14265273                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      2689328                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq        51131                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      8918956                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean     14265255                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      2687100                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq        34570                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            1                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp        51132                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      2516995                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      2516995                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq     14265790                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      7842728                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp        34571                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      2516977                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      2516977                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq     14265772                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      7842832                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::InvalidateReq      1246772                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::InvalidateResp      1246772                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     42883103                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     35055544                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     42883049                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     35022680                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       758208                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1548412                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          80245267                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1826160532                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1233877030                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1548392                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          80212329                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1826158228                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1234030630                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      3032832                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6193648                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         3069264042                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     1957594                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic             103278016                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples     55015054                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.010836                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.103531                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6193568                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         3069415258                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1762518                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic              96494656                       # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples     54803543                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.010878                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.103729                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           54418911     98.92%     98.92% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             596143      1.08%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           54207383     98.91%     98.91% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             596160      1.09%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       55015054                       # Request fanout histogram
-system.iobus.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.snoop_fanout::total       54803543                       # Request fanout histogram
+system.iobus.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 system.iobus.trans_dist::ReadReq                40242                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               40242                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136515                       # Transaction distribution
@@ -675,13 +675,13 @@ system.iobus.pkt_size_system.realview.ide.dma::total      7334248
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  7491944                       # Cumulative packet size per connected master and slave (bytes)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 system.iocache.tags.replacements               115459                       # number of replacements
 system.iocache.tags.tagsinuse               10.407111                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs               115475                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13082113306009                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.warmup_cycle         13082113307009                       # Cycle when the warmup percentage was hit.
 system.iocache.tags.occ_blocks::realview.ethernet     3.554597                       # Average occupied blocks per requestor
 system.iocache.tags.occ_blocks::realview.ide     6.852514                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::realview.ethernet     0.222162                       # Average percentage of cache occupancy
@@ -692,7 +692,7 @@ system.iocache.tags.age_task_id_blocks_1023::3           16
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
 system.iocache.tags.tag_accesses              1039650                       # Number of tag accesses
 system.iocache.tags.data_accesses             1039650                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
+system.iocache.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
 system.iocache.ReadReq_misses::realview.ide         8813                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total             8850                       # number of ReadReq misses
@@ -740,65 +740,71 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.writebacks::writebacks          106631                       # number of writebacks
 system.iocache.writebacks::total               106631                       # number of writebacks
-system.membus.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
+system.membus.snoop_filter.tot_requests       3778694                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests      1875355                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests         2861                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
+system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadReq               76679                       # Transaction distribution
-system.membus.trans_dist::ReadResp             524962                       # Transaction distribution
+system.membus.trans_dist::ReadResp             524960                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33606                       # Transaction distribution
 system.membus.trans_dist::WriteResp             33606                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1613719                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           226329                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            40494                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1613727                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           226320                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4445                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           40495                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            827052                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           827052                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        448283                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        658869                       # Transaction distribution
-system.membus.trans_dist::InvalidateResp       658869                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4446                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            827049                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           827049                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        448281                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        658871                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp       658871                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122480                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6654                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5534331                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      5663523                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5462226                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      5591418                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       346493                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       346493                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                6010016                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5937911                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155610                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13308                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    177701792                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    177870842                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    177701984                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    177871034                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7390784                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      7390784                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               185261626                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               185261818                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
 system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples           3925032                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::samples           3888979                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.009406                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.096529                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 3925032    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 3852398     99.06%     99.06% # Request fanout histogram
+system.membus.snoop_fanout::1                   36581      0.94%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3925032                       # Request fanout histogram
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
+system.membus.snoop_fanout::total             3888979                       # Request fanout histogram
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
 system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
 system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
 system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
 system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
 system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
@@ -841,28 +847,28 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt
index 99716a632..6d4993075 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt
@@ -4,75 +4,75 @@ sim_seconds                                 47.296282                       # Nu
 sim_ticks                                47296281748500                       # Number of ticks simulated
 final_tick                               47296281748500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 717114                       # Simulator instruction rate (inst/s)
-host_op_rate                                   843581                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            34713303168                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 688104                       # Number of bytes of host memory used
-host_seconds                                  1362.48                       # Real time elapsed on the host
+host_inst_rate                                 890958                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1048084                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            43128593002                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 697472                       # Number of bytes of host memory used
+host_seconds                                  1096.63                       # Real time elapsed on the host
 sim_insts                                   977055082                       # Number of instructions simulated
 sim_ops                                    1149364510                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.dtb.walker       151424                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       124352                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          3875572                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         35081800                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       222336                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       221312                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          2647048                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         38747248                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        401984                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             81473076                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      3875572                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      2647048                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         6522620                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks    101454976                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker       154816                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker       128128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          4238644                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         35981768                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       224128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       222976                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          3009416                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         39414640                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        402560                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             83777076                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      4238644                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      3009416                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         7248060                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks    102370496                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         101475560                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         2366                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         1943                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst            100963                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            548166                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         3474                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         3458                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             41467                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            605442                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6281                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1313560                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1585234                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total         102391080                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         2419                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         2002                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst            106636                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            562228                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         3502                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         3484                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             47129                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            615870                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6290                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1349560                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1599539                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1587808                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          3202                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          2629                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               81942                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              741745                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          4701                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          4679                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               55967                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              819245                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8499                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1722611                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          81942                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          55967                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             137910                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2145094                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1602113                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          3273                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          2709                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               89619                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              760774                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          4739                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          4714                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               63629                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              833356                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8511                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1771325                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          89619                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          63629                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             153248                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2164451                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data                435                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2145529                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2145094                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         3202                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         2629                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              81942                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             742181                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         4701                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         4679                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              55967                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             819245                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8499                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3868140                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2164886                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2164451                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         3273                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         2709                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              89619                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             761209                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         4739                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         4714                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              63629                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             833356                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8511                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3936211                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
 system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
@@ -332,11 +332,11 @@ system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Cl
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::total                 584096590                       # Class of executed instruction
 system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements          6248912                       # number of replacements
+system.cpu0.dcache.tags.replacements          6248914                       # number of replacements
 system.cpu0.dcache.tags.tagsinuse          501.980044                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          171607959                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          6249424                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            27.459804                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.total_refs          171607957                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          6249426                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            27.459795                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         33050500                       # Cycle when the warmup percentage was hit.
 system.cpu0.dcache.tags.occ_blocks::cpu0.data   501.980044                       # Average occupied blocks per requestor
 system.cpu0.dcache.tags.occ_percent::cpu0.data     0.980430                       # Average percentage of cache occupancy
@@ -346,41 +346,41 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0          199
 system.cpu0.dcache.tags.age_task_id_blocks_1024::1          306                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2            7                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        362271537                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       362271537                       # Number of data accesses
+system.cpu0.dcache.tags.tag_accesses        362271539                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       362271539                       # Number of data accesses
 system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
 system.cpu0.dcache.ReadReq_hits::cpu0.data     86024172                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::total       86024172                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     80672636                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      80672636                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     80674063                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      80674063                       # number of WriteReq hits
 system.cpu0.dcache.SoftPFReq_hits::cpu0.data       216269                       # number of SoftPFReq hits
 system.cpu0.dcache.SoftPFReq_hits::total       216269                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       261023                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       261023                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      2087977                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      2087977                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2051999                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      2051999                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    166957831                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       166957831                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    167174100                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      167174100                       # number of overall hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       261006                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       261006                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      2087975                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      2087975                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2051823                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      2051823                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    166959241                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       166959241                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    167175510                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      167175510                       # number of overall hits
 system.cpu0.dcache.ReadReq_misses::cpu0.data      3298422                       # number of ReadReq misses
 system.cpu0.dcache.ReadReq_misses::total      3298422                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1479208                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1479208                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1477781                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1477781                       # number of WriteReq misses
 system.cpu0.dcache.SoftPFReq_misses::cpu0.data       769563                       # number of SoftPFReq misses
 system.cpu0.dcache.SoftPFReq_misses::total       769563                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       824176                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total       824176                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       119749                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       119749                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data       154638                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total       154638                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      5601806                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       5601806                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      6371369                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      6371369                       # number of overall misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       824193                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total       824193                       # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       119751                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       119751                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data       154814                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total       154814                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      5600396                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       5600396                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      6369959                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      6369959                       # number of overall misses
 system.cpu0.dcache.ReadReq_accesses::cpu0.data     89322594                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.ReadReq_accesses::total     89322594                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.WriteReq_accesses::cpu0.data     82151844                       # number of WriteReq accesses(hits+misses)
@@ -399,34 +399,34 @@ system.cpu0.dcache.overall_accesses::cpu0.data    173545469
 system.cpu0.dcache.overall_accesses::total    173545469                       # number of overall (read+write) accesses
 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.036927                       # miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_miss_rate::total     0.036927                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.018006                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.018006                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.017988                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.017988                       # miss rate for WriteReq accesses
 system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.780623                       # miss rate for SoftPFReq accesses
 system.cpu0.dcache.SoftPFReq_miss_rate::total     0.780623                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.759470                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.759470                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.054241                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.054241                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.070079                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.070079                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.032463                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.032463                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.036713                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.036713                       # miss rate for overall accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.759486                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.759486                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.054242                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.054242                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.070158                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.070158                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.032455                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.032455                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.036705                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.036705                       # miss rate for overall accesses
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks      6248912                       # number of writebacks
-system.cpu0.dcache.writebacks::total          6248912                       # number of writebacks
+system.cpu0.dcache.writebacks::writebacks      6248914                       # number of writebacks
+system.cpu0.dcache.writebacks::total          6248914                       # number of writebacks
 system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements          5509619                       # number of replacements
+system.cpu0.icache.tags.replacements          5509624                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          511.989024                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          491225335                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          5510131                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            89.149484                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.total_refs          491225330                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          5510136                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            89.149402                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle       5759898000                       # Cycle when the warmup percentage was hit.
 system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.989024                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999979                       # Average percentage of cache occupancy
@@ -437,21 +437,21 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1          248
 system.cpu0.icache.tags.age_task_id_blocks_1024::2           63                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        998981078                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       998981078                       # Number of data accesses
+system.cpu0.icache.tags.tag_accesses        998981083                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       998981083                       # Number of data accesses
 system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst    491225335                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      491225335                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    491225335                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       491225335                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    491225335                       # number of overall hits
-system.cpu0.icache.overall_hits::total      491225335                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      5510136                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      5510136                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      5510136                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       5510136                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      5510136                       # number of overall misses
-system.cpu0.icache.overall_misses::total      5510136                       # number of overall misses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    491225330                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      491225330                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    491225330                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       491225330                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    491225330                       # number of overall hits
+system.cpu0.icache.overall_hits::total      491225330                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      5510141                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      5510141                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      5510141                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       5510141                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      5510141                       # number of overall misses
+system.cpu0.icache.overall_misses::total      5510141                       # number of overall misses
 system.cpu0.icache.ReadReq_accesses::cpu0.inst    496735471                       # number of ReadReq accesses(hits+misses)
 system.cpu0.icache.ReadReq_accesses::total    496735471                       # number of ReadReq accesses(hits+misses)
 system.cpu0.icache.demand_accesses::cpu0.inst    496735471                       # number of demand (read+write) accesses
@@ -470,8 +470,8 @@ system.cpu0.icache.blocked::no_mshrs                0                       # nu
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks      5509619                       # number of writebacks
-system.cpu0.icache.writebacks::total          5509619                       # number of writebacks
+system.cpu0.icache.writebacks::writebacks      5509624                       # number of writebacks
+system.cpu0.icache.writebacks::total          5509624                       # number of writebacks
 system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
 system.cpu0.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
 system.cpu0.l2cache.prefetcher.pfIdentified            0                       # number of prefetch candidates identified
@@ -480,193 +480,192 @@ system.cpu0.l2cache.prefetcher.pfInCache            0                       # nu
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
 system.cpu0.l2cache.prefetcher.pfSpanPage            0                       # number of prefetches not generated due to page crossing
 system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.tags.replacements         2653803                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16139.372932                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs          15525451                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs         2669765                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            5.815287                       # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.replacements         2567589                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       15706.944975                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs           9429067                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs         2583246                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            3.650085                       # Average number of references to valid blocks.
 system.cpu0.l2cache.tags.warmup_cycle       290949000                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 16063.015838                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    35.657747                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    40.699347                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.980409                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.002176                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.002484                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.985069                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023           53                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15909                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           39                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            5                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            9                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          238                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1444                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4368                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         5335                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         4524                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.003235                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.971008                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses       395826781                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses      395826781                       # Number of data accesses
+system.cpu0.l2cache.tags.occ_blocks::writebacks 15656.940594                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    27.364617                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    22.639763                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.955624                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.001670                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.001382                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.958676                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023           57                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15600                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            2                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           41                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            8                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            6                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          421                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         2091                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         5339                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         5411                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2338                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.003479                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.952148                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses       401859473                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses      401859473                       # Number of data accesses
 system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       296735                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       157755                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total        454490                       # number of ReadReq hits
-system.cpu0.l2cache.WritebackDirty_hits::writebacks      4439476                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackDirty_hits::total      4439476                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackClean_hits::writebacks      7317657                       # number of WritebackClean hits
-system.cpu0.l2cache.WritebackClean_hits::total      7317657                       # number of WritebackClean hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data          746                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total          746                       # number of UpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       639086                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       639086                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      5010934                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total      5010934                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2954772                       # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total      2954772                       # number of ReadSharedReq hits
-system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       221315                       # number of InvalidateReq hits
-system.cpu0.l2cache.InvalidateReq_hits::total       221315                       # number of InvalidateReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       296735                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker       157755                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      5010934                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data      3593858                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total        9059282                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       296735                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker       157755                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      5010934                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data      3593858                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total       9059282                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        11441                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         8530                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total        19971                       # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       138499                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total       138499                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       154638                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total       154638                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data       701212                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total       701212                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       499202                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::total       499202                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data      1232962                       # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total      1232962                       # number of ReadSharedReq misses
-system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       602526                       # number of InvalidateReq misses
-system.cpu0.l2cache.InvalidateReq_misses::total       602526                       # number of InvalidateReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        11441                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker         8530                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst       499202                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data      1934174                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total      2453347                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        11441                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker         8530                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst       499202                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data      1934174                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total      2453347                       # number of overall misses
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       308176                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       166285                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total       474461                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::writebacks      4439476                       # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::total      4439476                       # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::writebacks      7317657                       # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::total      7317657                       # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       139245                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total       139245                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       154638                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total       154638                       # number of SCUpgradeReq accesses(hits+misses)
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+system.cpu0.l2cache.WritebackDirty_hits::total      4441046                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackClean_hits::writebacks      7316094                       # number of WritebackClean hits
+system.cpu0.l2cache.WritebackClean_hits::total      7316094                       # number of WritebackClean hits
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data       640560                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadExReq_hits::total       640560                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      5011469                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::total      5011469                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2961462                       # number of ReadSharedReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::total      2961462                       # number of ReadSharedReq hits
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+system.cpu0.l2cache.InvalidateReq_hits::total       222733                       # number of InvalidateReq hits
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+system.cpu0.l2cache.overall_hits::cpu0.inst      5011469                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.data      3602022                       # number of overall hits
+system.cpu0.l2cache.overall_hits::total       9056382                       # number of overall hits
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        20057                       # number of ReadReq misses
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+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       137835                       # number of UpgradeReq misses
+system.cpu0.l2cache.UpgradeReq_misses::total       137835                       # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       154814                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::total       154814                       # number of SCUpgradeReq misses
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+system.cpu0.l2cache.ReadExReq_misses::total       699738                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       498672                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::total       498672                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data      1226274                       # number of ReadSharedReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::total      1226274                       # number of ReadSharedReq misses
+system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       601108                       # number of InvalidateReq misses
+system.cpu0.l2cache.InvalidateReq_misses::total       601108                       # number of InvalidateReq misses
+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        20057                       # number of demand (read+write) misses
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+system.cpu0.l2cache.demand_misses::cpu0.data      1926012                       # number of demand (read+write) misses
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+system.cpu0.l2cache.overall_misses::cpu0.itb.walker         9858                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.inst       498672                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.data      1926012                       # number of overall misses
+system.cpu0.l2cache.overall_misses::total      2454599                       # number of overall misses
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       307426                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       165380                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total       472806                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::writebacks      4441046                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::total      4441046                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::writebacks      7316094                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::total      7316094                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       137835                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total       137835                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       154814                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total       154814                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1340298                       # number of ReadExReq accesses(hits+misses)
 system.cpu0.l2cache.ReadExReq_accesses::total      1340298                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      5510136                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::total      5510136                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      4187734                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::total      4187734                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      5510141                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::total      5510141                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      4187736                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::total      4187736                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       823841                       # number of InvalidateReq accesses(hits+misses)
 system.cpu0.l2cache.InvalidateReq_accesses::total       823841                       # number of InvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       308176                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       166285                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst      5510136                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data      5528032                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total     11512629                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       308176                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       166285                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst      5510136                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data      5528032                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total     11512629                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.037125                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.051297                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.042092                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.994643                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.994643                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       307426                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       165380                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.inst      5510141                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.data      5528034                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::total     11510981                       # number of demand (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       307426                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       165380                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst      5510141                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data      5528034                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total     11510981                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.065242                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.059608                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.063271                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data            1                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.523176                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.523176                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.090597                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.090597                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.294422                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.294422                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.731362                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.731362                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.037125                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.051297                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.090597                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.349885                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.213101                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.037125                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.051297                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.090597                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.349885                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.213101                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.522076                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.522076                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.090501                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.090501                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.292825                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.292825                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.729641                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.729641                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.065242                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.059608                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.090501                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.348408                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.213240                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.065242                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.059608                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.090501                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.348408                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.213240                       # miss rate for overall accesses
 system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.l2cache.writebacks::writebacks      1559963                       # number of writebacks
-system.cpu0.l2cache.writebacks::total         1559963                       # number of writebacks
-system.cpu0.toL2Bus.snoop_filter.tot_requests     24176858                       # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests     12314856                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.l2cache.writebacks::writebacks      1552940                       # number of writebacks
+system.cpu0.l2cache.writebacks::total         1552940                       # number of writebacks
+system.cpu0.toL2Bus.snoop_filter.tot_requests     24175638                       # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests     12313629                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         1398                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops      1775409                       # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops      1775098                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops          311                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops       303605                       # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       303605                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
 system.cpu0.toL2Bus.trans_dist::ReadReq        622617                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp     10320487                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp     10320494                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::WriteReq        33234                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::WriteResp        33234                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty      4439476                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean      7319055                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq       139245                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       154638                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       293883                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty      4441046                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean      7317492                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq       137835                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       154814                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       292649                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::ReadExReq      1340298                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::ReadExResp      1340298                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      5510136                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4187734                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      5510141                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4187736                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::InvalidateReq       823841                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::InvalidateResp       823841                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     16616141                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     19673024                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     16616156                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     19670562                       # Packet count per connected master and slave (bytes)
 system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       364916                       # Packet count per connected master and slave (bytes)
 system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       727936                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total         37382017                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    705436820                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    753922812                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total         37379570                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    705437460                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    753923068                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1459664                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      2911744                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total        1463731040                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    6082125                       # Total snoops (count)
-system.cpu0.toL2Bus.snoopTraffic            101619328                       # Total snoop traffic (bytes)
-system.cpu0.toL2Bus.snoop_fanout::samples     30471409                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       0.066979                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.250027                       # Request fanout histogram
+system.cpu0.toL2Bus.pkt_size::total        1463731936                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    4670427                       # Total snoops (count)
+system.cpu0.toL2Bus.snoopTraffic            101174852                       # Total snoop traffic (bytes)
+system.cpu0.toL2Bus.snoop_fanout::samples     29058250                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       0.019576                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.138538                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0          28430762     93.30%     93.30% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1           2040336      6.70%    100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2               311      0.00%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0          28489407     98.04%     98.04% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1            568843      1.96%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2                 0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total      30471409                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::total      29058250                       # Request fanout histogram
 system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -888,11 +887,11 @@ system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Cl
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::total                 565908654                       # Class of executed instruction
 system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.tags.replacements          5970882                       # number of replacements
+system.cpu1.dcache.tags.replacements          5970884                       # number of replacements
 system.cpu1.dcache.tags.tagsinuse          423.354804                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs          166384450                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs          5971393                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            27.863591                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.total_refs          166384448                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs          5971395                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            27.863581                       # Average number of references to valid blocks.
 system.cpu1.dcache.tags.warmup_cycle     8470277781000                       # Cycle when the warmup percentage was hit.
 system.cpu1.dcache.tags.occ_blocks::cpu1.data   423.354804                       # Average occupied blocks per requestor
 system.cpu1.dcache.tags.occ_percent::cpu1.data     0.826865                       # Average percentage of cache occupancy
@@ -902,41 +901,41 @@ system.cpu1.dcache.tags.age_task_id_blocks_1024::0          180
 system.cpu1.dcache.tags.age_task_id_blocks_1024::1          330                       # Occupied blocks per task id
 system.cpu1.dcache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
 system.cpu1.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses        350957209                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses       350957209                       # Number of data accesses
+system.cpu1.dcache.tags.tag_accesses        350957211                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses       350957211                       # Number of data accesses
 system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.ReadReq_hits::cpu1.data     84198599                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       84198599                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data     77532107                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total      77532107                       # number of WriteReq hits
+system.cpu1.dcache.ReadReq_hits::cpu1.data     84198598                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       84198598                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data     77531561                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total      77531561                       # number of WriteReq hits
 system.cpu1.dcache.SoftPFReq_hits::cpu1.data       187263                       # number of SoftPFReq hits
 system.cpu1.dcache.SoftPFReq_hits::total       187263                       # number of SoftPFReq hits
-system.cpu1.dcache.WriteLineReq_hits::cpu1.data        64879                       # number of WriteLineReq hits
-system.cpu1.dcache.WriteLineReq_hits::total        64879                       # number of WriteLineReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      2055501                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total      2055501                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data      2044925                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total      2044925                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data    161795585                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total       161795585                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data    161982848                       # number of overall hits
-system.cpu1.dcache.overall_hits::total      161982848                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data      3367289                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total      3367289                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data      1465578                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      1465578                       # number of WriteReq misses
+system.cpu1.dcache.WriteLineReq_hits::cpu1.data        64886                       # number of WriteLineReq hits
+system.cpu1.dcache.WriteLineReq_hits::total        64886                       # number of WriteLineReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      2055500                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total      2055500                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data      2044725                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total      2044725                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data    161795045                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total       161795045                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data    161982308                       # number of overall hits
+system.cpu1.dcache.overall_hits::total      161982308                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data      3367290                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total      3367290                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      1466124                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      1466124                       # number of WriteReq misses
 system.cpu1.dcache.SoftPFReq_misses::cpu1.data       793623                       # number of SoftPFReq misses
 system.cpu1.dcache.SoftPFReq_misses::total       793623                       # number of SoftPFReq misses
-system.cpu1.dcache.WriteLineReq_misses::cpu1.data       433878                       # number of WriteLineReq misses
-system.cpu1.dcache.WriteLineReq_misses::total       433878                       # number of WriteLineReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       147104                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total       147104                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data       156474                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total       156474                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data      5266745                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total       5266745                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data      6060368                       # number of overall misses
-system.cpu1.dcache.overall_misses::total      6060368                       # number of overall misses
+system.cpu1.dcache.WriteLineReq_misses::cpu1.data       433871                       # number of WriteLineReq misses
+system.cpu1.dcache.WriteLineReq_misses::total       433871                       # number of WriteLineReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       147105                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total       147105                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data       156674                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total       156674                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data      5267285                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total       5267285                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data      6060908                       # number of overall misses
+system.cpu1.dcache.overall_misses::total      6060908                       # number of overall misses
 system.cpu1.dcache.ReadReq_accesses::cpu1.data     87565888                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.ReadReq_accesses::total     87565888                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.WriteReq_accesses::cpu1.data     78997685                       # number of WriteReq accesses(hits+misses)
@@ -955,28 +954,28 @@ system.cpu1.dcache.overall_accesses::cpu1.data    168043216
 system.cpu1.dcache.overall_accesses::total    168043216                       # number of overall (read+write) accesses
 system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.038454                       # miss rate for ReadReq accesses
 system.cpu1.dcache.ReadReq_miss_rate::total     0.038454                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.018552                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.018552                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.018559                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.018559                       # miss rate for WriteReq accesses
 system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.809088                       # miss rate for SoftPFReq accesses
 system.cpu1.dcache.SoftPFReq_miss_rate::total     0.809088                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.869919                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::total     0.869919                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.066786                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.066786                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.071079                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.071079                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.031526                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.031526                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.036064                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.036064                       # miss rate for overall accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.869905                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::total     0.869905                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.066787                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.066787                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.071170                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.071170                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.031529                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.031529                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.036068                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.036068                       # miss rate for overall accesses
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.writebacks::writebacks      5970882                       # number of writebacks
-system.cpu1.dcache.writebacks::total          5970882                       # number of writebacks
+system.cpu1.dcache.writebacks::writebacks      5970884                       # number of writebacks
+system.cpu1.dcache.writebacks::total          5970884                       # number of writebacks
 system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
 system.cpu1.icache.tags.replacements          4768482                       # number of replacements
 system.cpu1.icache.tags.tagsinuse          496.452247                       # Cycle average of tags in use
@@ -1035,193 +1034,191 @@ system.cpu1.l2cache.prefetcher.pfInCache            0                       # nu
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
 system.cpu1.l2cache.prefetcher.pfSpanPage            0                       # number of prefetches not generated due to page crossing
 system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.tags.replacements         2262891                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       13357.261726                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs          14305129                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs         2278874                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs            6.277279                       # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle    9829187815500                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 13247.067066                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    51.785938                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    58.408722                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.808537                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.003161                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.003565                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.815263                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           91                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        15892                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           53                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           17                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.replacements         2174770                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       13105.960937                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs           8815603                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs         2190453                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs            4.024557                       # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
+system.cpu1.l2cache.tags.occ_blocks::writebacks 13068.855777                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    21.863128                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    15.242032                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.797660                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.001334                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000930                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.799924                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           90                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        15593                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           57                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           12                       # Occupied blocks per task id
 system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           21                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          152                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1574                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         6119                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4359                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3688                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005554                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.969971                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses       363588050                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses      363588050                       # Number of data accesses
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          246                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         2414                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         7618                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         3564                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         1751                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005493                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.951721                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses       369059783                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses      369059783                       # Number of data accesses
 system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       348760                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       155429                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total        504189                       # number of ReadReq hits
-system.cpu1.l2cache.WritebackDirty_hits::writebacks      4050331                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackDirty_hits::total      4050331                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackClean_hits::writebacks      6688666                       # number of WritebackClean hits
-system.cpu1.l2cache.WritebackClean_hits::total      6688666                       # number of WritebackClean hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         1054                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total         1054                       # number of UpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data       613437                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total       613437                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      4306709                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total      4306709                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      3087044                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total      3087044                       # number of ReadSharedReq hits
-system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       164780                       # number of InvalidateReq hits
-system.cpu1.l2cache.InvalidateReq_hits::total       164780                       # number of InvalidateReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       348760                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker       155429                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst      4306709                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data      3700481                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total        8511379                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       348760                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker       155429                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst      4306709                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data      3700481                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total       8511379                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        12218                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         9629                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total        21847                       # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       143649                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total       143649                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       156474                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total       156474                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data       707649                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total       707649                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       462285                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total       462285                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data      1220972                       # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total      1220972                       # number of ReadSharedReq misses
-system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       268887                       # number of InvalidateReq misses
-system.cpu1.l2cache.InvalidateReq_misses::total       268887                       # number of InvalidateReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        12218                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker         9629                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst       462285                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data      1928621                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total      2412753                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        12218                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker         9629                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst       462285                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data      1928621                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total      2412753                       # number of overall misses
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       360978                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       165058                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total       526036                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::writebacks      4050331                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::total      4050331                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::writebacks      6688666                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::total      6688666                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       144703                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total       144703                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       156474                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total       156474                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       338101                       # number of ReadReq hits
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+system.cpu1.l2cache.ReadReq_hits::total        491768                       # number of ReadReq hits
+system.cpu1.l2cache.WritebackDirty_hits::writebacks      4061526                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackDirty_hits::total      4061526                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackClean_hits::writebacks      6677473                       # number of WritebackClean hits
+system.cpu1.l2cache.WritebackClean_hits::total      6677473                       # number of WritebackClean hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data       614785                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total       614785                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      4308825                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::total      4308825                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      3093892                       # number of ReadSharedReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::total      3093892                       # number of ReadSharedReq hits
+system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       164960                       # number of InvalidateReq hits
+system.cpu1.l2cache.InvalidateReq_hits::total       164960                       # number of InvalidateReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       338101                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker       153667                       # number of demand (read+write) hits
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+system.cpu1.l2cache.demand_hits::cpu1.data      3708677                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total        8509270                       # number of demand (read+write) hits
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       338101                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker       153667                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst      4308825                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data      3708677                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total       8509270                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        22355                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker        10972                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total        33327                       # number of ReadReq misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       145242                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total       145242                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       156674                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total       156674                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data       706301                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadExReq_misses::total       706301                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       460169                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::total       460169                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data      1214126                       # number of ReadSharedReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::total      1214126                       # number of ReadSharedReq misses
+system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       268707                       # number of InvalidateReq misses
+system.cpu1.l2cache.InvalidateReq_misses::total       268707                       # number of InvalidateReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        22355                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker        10972                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.inst       460169                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.data      1920427                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::total      2413923                       # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        22355                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker        10972                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst       460169                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data      1920427                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total      2413923                       # number of overall misses
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       360456                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       164639                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total       525095                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::writebacks      4061526                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::total      4061526                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::writebacks      6677473                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::total      6677473                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       145242                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total       145242                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       156674                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total       156674                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1321086                       # number of ReadExReq accesses(hits+misses)
 system.cpu1.l2cache.ReadExReq_accesses::total      1321086                       # number of ReadExReq accesses(hits+misses)
 system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      4768994                       # number of ReadCleanReq accesses(hits+misses)
 system.cpu1.l2cache.ReadCleanReq_accesses::total      4768994                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      4308016                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total      4308016                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      4308018                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::total      4308018                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       433667                       # number of InvalidateReq accesses(hits+misses)
 system.cpu1.l2cache.InvalidateReq_accesses::total       433667                       # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       360978                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       165058                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       360456                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       164639                       # number of demand (read+write) accesses
 system.cpu1.l2cache.demand_accesses::cpu1.inst      4768994                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data      5629102                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total     10924132                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       360978                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       165058                       # number of overall (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data      5629104                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total     10923193                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       360456                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       164639                       # number of overall (read+write) accesses
 system.cpu1.l2cache.overall_accesses::cpu1.inst      4768994                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data      5629102                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total     10924132                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.033847                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.058337                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.041531                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.992716                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.992716                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data      5629104                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total     10923193                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.062019                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.066643                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.063469                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.535657                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.535657                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.096936                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.096936                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.283419                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.283419                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.620031                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.620031                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.033847                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.058337                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.096936                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.342616                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.220865                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.033847                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.058337                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.096936                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.342616                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.220865                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.534637                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.534637                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.096492                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.096492                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.281829                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.281829                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.619616                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.619616                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.062019                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.066643                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.096492                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.341160                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.220991                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.062019                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.066643                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.096492                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.341160                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.220991                       # miss rate for overall accesses
 system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.l2cache.writebacks::writebacks      1200117                       # number of writebacks
-system.cpu1.l2cache.writebacks::total         1200117                       # number of writebacks
-system.cpu1.toL2Bus.snoop_filter.tot_requests     22145801                       # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests     11314039                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.l2cache.writebacks::writebacks      1197912                       # number of writebacks
+system.cpu1.l2cache.writebacks::total         1197912                       # number of writebacks
+system.cpu1.toL2Bus.snoop_filter.tot_requests     22146544                       # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests     11314780                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu1.toL2Bus.snoop_filter.hit_multi_requests          367                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops      1748963                       # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops      1748793                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops          170                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops       285761                       # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       285759                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops            2                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
 system.cpu1.toL2Bus.trans_dist::ReadReq        607661                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp      9684671                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp      9684673                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::WriteReq         5564                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::WriteResp         5564                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty      4050331                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean      6689033                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq       144703                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       156474                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp       301177                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty      4061526                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean      6677840                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq       145242                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       156674                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp       301916                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::ReadExReq      1321086                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::ReadExResp      1321086                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::ReadCleanReq      4768994                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4308016                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4308018                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::InvalidateReq       433667                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::InvalidateResp       433667                       # Transaction distribution
 system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     14306730                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     18721524                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     18723008                       # Packet count per connected master and slave (bytes)
 system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       366766                       # Packet count per connected master and slave (bytes)
 system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       836674                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total         34231694                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total         34233178                       # Packet count per connected master and slave (bytes)
 system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    610398984                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    742432303                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    742432559                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1467064                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      3346696                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total        1357645047                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                    5675394                       # Total snoops (count)
-system.cpu1.toL2Bus.snoopTraffic             79399936                       # Total snoop traffic (bytes)
-system.cpu1.toL2Bus.snoop_fanout::samples     28001988                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       0.072258                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.258938                       # Request fanout histogram
+system.cpu1.toL2Bus.pkt_size::total        1357645303                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                    4277162                       # Total snoops (count)
+system.cpu1.toL2Bus.snoopTraffic             79243712                       # Total snoop traffic (bytes)
+system.cpu1.toL2Bus.snoop_fanout::samples     26604267                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       0.021049                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.143548                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0          25978793     92.77%     92.77% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1           2023025      7.22%    100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2               170      0.00%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0          26044274     97.90%     97.90% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1            559991      2.10%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2                 2      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total      28001988                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::total      26604267                       # Request fanout histogram
 system.iobus.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
 system.iobus.trans_dist::ReadReq                40301                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               40301                       # Transaction distribution
@@ -1331,263 +1328,263 @@ system.iocache.avg_blocked_cycles::no_targets          nan
 system.iocache.writebacks::writebacks          106694                       # number of writebacks
 system.iocache.writebacks::total               106694                       # number of writebacks
 system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements                  1774395                       # number of replacements
-system.l2c.tags.tagsinuse                63409.930559                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    4611925                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1833378                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     2.515534                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                514828500                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   34658.678488                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    33.446161                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker    43.299197                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3299.237288                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     7180.746684                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   272.688902                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   432.688870                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     2834.364418                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data    14654.780551                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.528849                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000510                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.000661                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.050342                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.109569                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.004161                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.006602                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.043249                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.223614                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.967559                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023          232                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        58751                       # Occupied blocks per task id
+system.l2c.tags.replacements                  1924793                       # number of replacements
+system.l2c.tags.tagsinuse                65250.197909                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    5713780                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1986359                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     2.876509                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle                477350500                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   10662.392220                       # Average occupied blocks per requestor
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+system.l2c.tags.occ_blocks::cpu0.itb.walker    44.787257                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3175.849688                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data    15990.343630                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   362.595804                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   421.087250                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     2804.760651                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data    31746.652822                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.162695                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000637                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.000683                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.048460                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.243993                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.005533                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.006425                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.042797                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.484415                       # Average percentage of cache occupancy
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 system.l2c.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          231                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          463                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         3223                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5259                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        49760                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.003540                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.896469                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 73267769                       # Number of tag accesses
-system.l2c.tags.data_accesses                73267769                       # Number of data accesses
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+system.l2c.tags.data_accesses                71904156                       # Number of data accesses
 system.l2c.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
-system.l2c.WritebackDirty_hits::writebacks      2760080                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total         2760080                       # number of WritebackDirty hits
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-system.l2c.UpgradeReq_hits::cpu1.data           15288                       # number of UpgradeReq hits
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-system.l2c.InvalidateReq_hits::cpu1.data       102728                       # number of InvalidateReq hits
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-system.l2c.ReadSharedReq_misses::cpu1.itb.walker         3458                       # number of ReadSharedReq misses
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-system.l2c.WritebackDirty_accesses::total      2760080                       # number of WritebackDirty accesses(hits+misses)
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-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.797914                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.791273                       # miss rate for UpgradeReq accesses
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-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.198366                       # miss rate for ReadSharedReq accesses
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-system.l2c.InvalidateReq_miss_rate::cpu1.data     0.609358                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::total     0.744959                       # miss rate for InvalidateReq accesses
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+system.l2c.overall_hits::cpu1.itb.walker         4097                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             413141                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             841040                       # number of overall hits
+system.l2c.overall_hits::total                2630251                       # number of overall hits
+system.l2c.UpgradeReq_misses::cpu0.data         21889                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data         25427                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             47316                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data          415                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data          794                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total            1209                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data         372583                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data         420111                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             792694                       # number of ReadExReq misses
+system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         2419                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.itb.walker         2002                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.inst        63535                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data       191729                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         3502                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.itb.walker         3484                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.inst        47028                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data       197713                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total         511412                       # number of ReadSharedReq misses
+system.l2c.InvalidateReq_misses::cpu0.data       462716                       # number of InvalidateReq misses
+system.l2c.InvalidateReq_misses::cpu1.data       149158                       # number of InvalidateReq misses
+system.l2c.InvalidateReq_misses::total         611874                       # number of InvalidateReq misses
+system.l2c.demand_misses::cpu0.dtb.walker         2419                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.itb.walker         2002                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst             63535                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            564312                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker         3502                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.itb.walker         3484                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst             47028                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data            617824                       # number of demand (read+write) misses
+system.l2c.demand_misses::total               1304106                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker         2419                       # number of overall misses
+system.l2c.overall_misses::cpu0.itb.walker         2002                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst            63535                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           564312                       # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker         3502                       # number of overall misses
+system.l2c.overall_misses::cpu1.itb.walker         3484                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst            47028                       # number of overall misses
+system.l2c.overall_misses::cpu1.data           617824                       # number of overall misses
+system.l2c.overall_misses::total              1304106                       # number of overall misses
+system.l2c.WritebackDirty_accesses::writebacks      2750852                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total      2750852                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data        82021                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data        76966                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total          158987                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data         8915                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data         8489                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total         17404                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       572093                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       596668                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total          1168761                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker        14787                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         7248                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.inst       498672                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data       899336                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker        15607                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         7581                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.inst       460169                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data       862196                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total      2765596                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu0.data       593072                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu1.data       262725                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::total       855797                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker        14787                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         7248                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          498672                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data         1471429                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker        15607                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         7581                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          460169                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data         1458864                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             3934357                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker        14787                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         7248                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         498672                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data        1471429                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker        15607                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         7581                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         460169                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data        1458864                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            3934357                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.266871                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.330367                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.297609                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.046551                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.093533                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.069467                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.651263                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.704095                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.678234                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.163590                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.276214                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.127408                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.213190                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.224386                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.459570                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.102197                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.229313                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.184919                       # miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu0.data     0.780202                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu1.data     0.567734                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::total     0.714976                       # miss rate for InvalidateReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.163590                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.276214                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.127408                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.383513                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.224386                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.459570                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.102197                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.423497                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.331466                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.163590                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.276214                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.127408                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.383513                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.224386                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.459570                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.102197                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.423497                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.331466                       # miss rate for overall accesses
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.writebacks::writebacks             1478540                       # number of writebacks
-system.l2c.writebacks::total                  1478540                       # number of writebacks
-system.membus.snoop_filter.tot_requests       4495065                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests      2597713                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests         3483                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.l2c.writebacks::writebacks             1492845                       # number of writebacks
+system.l2c.writebacks::total                  1492845                       # number of writebacks
+system.membus.snoop_filter.tot_requests       4436915                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests      2508187                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests         3478                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadReq               82130                       # Transaction distribution
-system.membus.trans_dist::ReadResp             571159                       # Transaction distribution
+system.membus.trans_dist::ReadResp             602460                       # Transaction distribution
 system.membus.trans_dist::WriteReq              38798                       # Transaction distribution
 system.membus.trans_dist::WriteResp             38798                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1585234                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           247687                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           337993                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq         306149                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp          159131                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            787924                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           784573                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        489029                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        741049                       # Transaction distribution
-system.membus.trans_dist::InvalidateResp       741049                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1599539                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           267122                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           245150                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq         295293                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           53835                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            792754                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           789263                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        520330                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        716726                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp       716726                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122576                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           92                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        27542                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      6413605                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      6563815                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      6261826                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      6412036                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       346888                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       346888                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                6910703                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                6758924                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155683                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          204                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        55084                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    175760092                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    175971063                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    178979036                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    179190007                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7399168                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      7399168                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               183370231                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               186589175                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
 system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples           4615993                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.007281                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.085020                       # Request fanout histogram
+system.membus.snoop_fanout::samples           4557842                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.007340                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.085359                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 4582382     99.27%     99.27% # Request fanout histogram
-system.membus.snoop_fanout::1                   33611      0.73%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 4524387     99.27%     99.27% # Request fanout histogram
+system.membus.snoop_fanout::1                   33455      0.73%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             4615993                       # Request fanout histogram
+system.membus.snoop_fanout::total             4557842                       # Request fanout histogram
 system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
 system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
 system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
@@ -1668,45 +1665,45 @@ system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500
 system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
 system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
 system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests     11098491                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      5714084                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests      1638499                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops         134977                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops       121387                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops        13590                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_requests     11075061                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      5706480                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests      1648775                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops         269190                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops       248390                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops        20800                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47296281748500                       # Cumulative time (in ticks) in various power states
 system.toL2Bus.trans_dist::ReadReq              82132                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           3539371                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           3544615                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             38798                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            38798                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty      2760080                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         2007636                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          350499                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq        311112                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         661611                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          1354403                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         1354403                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      3457239                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq       857520                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp       857520                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      9497179                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      8173943                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              17671122                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    255360528                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    229634423                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              484994951                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         1809010                       # Total snoops (count)
-system.toL2Bus.snoopTraffic                  94667072                       # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples         13026748                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.284748                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.453600                       # Request fanout histogram
+system.toL2Bus.trans_dist::WritebackDirty      2750852                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         1991304                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          351511                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq        311488                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         662999                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          1351623                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         1351623                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      3462483                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq       855797                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp       855797                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      9483041                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      8166779                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              17649820                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    254997904                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    229564151                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              484562055                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         1959256                       # Total snoops (count)
+system.toL2Bus.snoopTraffic                  95582592                       # Total snoop traffic (bytes)
+system.toL2Bus.snoop_fanout::samples         13153559                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.293824                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.458971                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                9330997     71.63%     71.63% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                3682161     28.27%     99.90% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                  13590      0.10%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                9309527     70.78%     70.78% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                3823232     29.07%     99.84% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                  20800      0.16%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           13026748                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::total           13153559                       # Request fanout histogram
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt
index e11d9e780..8ece6948a 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt
@@ -1,58 +1,58 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                 51.111167                       # Number of seconds simulated
-sim_ticks                                51111167192000                       # Number of ticks simulated
-final_tick                               51111167192000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                51111167268500                       # Number of ticks simulated
+final_tick                               51111167268500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 779536                       # Simulator instruction rate (inst/s)
-host_op_rate                                   916124                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            40565130498                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 670816                       # Number of bytes of host memory used
-host_seconds                                  1259.98                       # Real time elapsed on the host
-sim_insts                                   982198638                       # Number of instructions simulated
-sim_ops                                    1154296340                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 937025                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1101207                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            48760450215                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 680056                       # Number of bytes of host memory used
+host_seconds                                  1048.21                       # Real time elapsed on the host
+sim_insts                                   982198023                       # Number of instructions simulated
+sim_ops                                    1154295627                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.dtb.walker       414464                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker       373568                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           5484148                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          74913608                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           5483444                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          74913992                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide        436800                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             81622588                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      5484148                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5484148                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks    103278016                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             81622268                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      5483444                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         5483444                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks    103278528                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         103298596                       # Number of bytes written to this memory
+system.physmem.bytes_written::total         103299108                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.dtb.walker         6476                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker         5837                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             126097                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1170538                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             126086                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1170544                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide           6825                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1315773                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1613719                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total               1315768                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1613727                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1616292                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1616300                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.dtb.walker           8109                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker           7309                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               107298                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1465699                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               107285                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1465707                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide             8546                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1596962                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          107298                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             107298                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2020655                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1596956                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          107285                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             107285                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2020665                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                 403                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2021057                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2020655                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2021067                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2020665                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker          8109                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker          7309                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              107298                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1466102                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              107285                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1466110                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide            8546                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3618019                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
+system.physmem.bw_total::total                3618023                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 system.realview.nvmem.bytes_read::cpu.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
@@ -69,9 +69,9 @@ system.realview.nvmem.bw_inst_read::total            2                       # I
 system.realview.nvmem.bw_total::cpu.inst            2                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total               3                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
@@ -79,7 +79,7 @@ system.cf0.dma_write_full_pages                  1666                       # Nu
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -109,30 +109,30 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks                    266586                       # Table walker walks requested
-system.cpu.dtb.walker.walksLong                266586                       # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walkWaitTime::samples       266586                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0          266586    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total       266586                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.walks                    266581                       # Table walker walks requested
+system.cpu.dtb.walker.walksLong                266581                       # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walkWaitTime::samples       266581                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0          266581    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total       266581                       # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walksPending::samples     22846000                       # Table walker pending requests distribution
 system.cpu.dtb.walker.walksPending::0        22846000    100.00%    100.00% # Table walker pending requests distribution
 system.cpu.dtb.walker.walksPending::total     22846000                       # Table walker pending requests distribution
 system.cpu.dtb.walker.walkPageSizes::4K        204774     89.35%     89.35% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M         24416     10.65%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total       229190                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       266586                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkPageSizes::2M         24411     10.65%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total       229185                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       266581                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total       266586                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       229190                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total       266581                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       229185                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total       229190                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total       495776                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total       229185                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total       495766                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                    183544097                       # DTB read hits
-system.cpu.dtb.read_misses                     195348                       # DTB read misses
-system.cpu.dtb.write_hits                   167774773                       # DTB write hits
+system.cpu.dtb.read_hits                    183543984                       # DTB read hits
+system.cpu.dtb.read_misses                     195343                       # DTB read misses
+system.cpu.dtb.write_hits                   167774645                       # DTB write hits
 system.cpu.dtb.write_misses                     71238                       # DTB write misses
 system.cpu.dtb.flush_tlb                           11                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
@@ -140,16 +140,16 @@ system.cpu.dtb.flush_tlb_mva_asid               49771                       # Nu
 system.cpu.dtb.flush_tlb_asid                    1139                       # Number of times TLB was flushed by ASID
 system.cpu.dtb.flush_entries                    82439                       # Number of entries that have been flushed from TLB
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   9079                       # Number of TLB faults due to prefetch
+system.cpu.dtb.prefetch_faults                   9074                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
 system.cpu.dtb.perms_faults                     21651                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                183739445                       # DTB read accesses
-system.cpu.dtb.write_accesses               167846011                       # DTB write accesses
+system.cpu.dtb.read_accesses                183739327                       # DTB read accesses
+system.cpu.dtb.write_accesses               167845883                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                         351318870                       # DTB hits
-system.cpu.dtb.misses                          266586                       # DTB misses
-system.cpu.dtb.accesses                     351585456                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.hits                         351318629                       # DTB hits
+system.cpu.dtb.misses                          266581                       # DTB misses
+system.cpu.dtb.accesses                     351585210                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -179,7 +179,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                    126834                       # Table walker walks requested
 system.cpu.itb.walker.walksLong                126834                       # Table walker walks initiated with long descriptors
 system.cpu.itb.walker.walkWaitTime::samples       126834                       # Table walker wait (enqueue to first request) latency
@@ -198,7 +198,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0
 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       114696                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::total       114696                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin::total       241530                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                    982675484                       # ITB inst hits
+system.cpu.itb.inst_hits                    982674869                       # ITB inst hits
 system.cpu.itb.inst_misses                     126834                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
@@ -215,14 +215,14 @@ system.cpu.itb.domain_faults                        0                       # Nu
 system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                982802318                       # ITB inst accesses
-system.cpu.itb.hits                         982675484                       # DTB hits
+system.cpu.itb.inst_accesses                982801703                       # ITB inst accesses
+system.cpu.itb.hits                         982674869                       # DTB hits
 system.cpu.itb.misses                          126834                       # DTB misses
-system.cpu.itb.accesses                     982802318                       # DTB accesses
+system.cpu.itb.accesses                     982801703                       # DTB accesses
 system.cpu.numPwrStateTransitions               33550                       # Number of power state transitions
 system.cpu.pwrStateClkGateDist::samples         16775                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::mean     3012440883.104620                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::stdev    59942517995.825706                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean     3012440908.824083                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev    59942517661.771744                       # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::underflows         7454     44.44%     44.44% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::1000-5e+10         9286     55.36%     99.79% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::5e+10-1e+11            4      0.02%     99.82% # Distribution of time spent in the clock gated state
@@ -235,40 +235,40 @@ system.cpu.pwrStateClkGateDist::4.5e+11-5e+11            1      0.01%     99.89%
 system.cpu.pwrStateClkGateDist::5.5e+11-6e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::overflows           18      0.11%    100.00% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::max_value 1988782948204                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::max_value 1988782931704                       # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::total           16775                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateResidencyTicks::ON    577471377920                       # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::CLK_GATED 50533695814080                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                     102222351160                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON    577471022976                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 50533696245524                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                     102222351313                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                    16775                       # number of quiesce instructions executed
-system.cpu.committedInsts                   982198638                       # Number of instructions committed
-system.cpu.committedOps                    1154296340                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses            1057877800                       # Number of integer alu accesses
+system.cpu.committedInsts                   982198023                       # Number of instructions committed
+system.cpu.committedOps                    1154295627                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses            1057877135                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                 881349                       # Number of float alu accesses
-system.cpu.num_func_calls                    56833909                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts    151622723                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                   1057877800                       # number of integer instructions
+system.cpu.num_func_calls                    56833843                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts    151622640                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                   1057877135                       # number of integer instructions
 system.cpu.num_fp_insts                        881349                       # number of float instructions
-system.cpu.num_int_register_reads          1560754548                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          840513636                       # number of times the integer registers were written
+system.cpu.num_int_register_reads          1560753668                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          840513151                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads              1419767                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes              748560                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            264017562                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes           263439787                       # number of times the CC registers were written
-system.cpu.num_mem_refs                     351538306                       # number of memory refs
-system.cpu.num_load_insts                   183711405                       # Number of load instructions
-system.cpu.num_store_insts                  167826901                       # Number of store instructions
-system.cpu.num_idle_cycles               101067408214.617065                       # Number of idle cycles
-system.cpu.num_busy_cycles               1154942945.382940                       # Number of busy cycles
+system.cpu.num_cc_register_reads            264017457                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes           263439679                       # number of times the CC registers were written
+system.cpu.num_mem_refs                     351538055                       # number of memory refs
+system.cpu.num_load_insts                   183711282                       # Number of load instructions
+system.cpu.num_store_insts                  167826773                       # Number of store instructions
+system.cpu.num_idle_cycles               101067409077.505173                       # Number of idle cycles
+system.cpu.num_busy_cycles               1154942235.494823                       # Number of busy cycles
 system.cpu.not_idle_fraction                 0.011298                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.988702                       # Percentage of idle cycles
-system.cpu.Branches                         219532347                       # Number of branches fetched
+system.cpu.Branches                         219532189                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     1      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                 800829907     69.34%     69.34% # Class of executed instruction
-system.cpu.op_class::IntMult                  2354386      0.20%     69.54% # Class of executed instruction
+system.cpu.op_class::IntAlu                 800829443     69.34%     69.34% # Class of executed instruction
+system.cpu.op_class::IntMult                  2354388      0.20%     69.54% # Class of executed instruction
 system.cpu.op_class::IntDiv                    100543      0.01%     69.55% # Class of executed instruction
 system.cpu.op_class::FloatAdd                       0      0.00%     69.55% # Class of executed instruction
 system.cpu.op_class::FloatCmp                       0      0.00%     69.55% # Class of executed instruction
@@ -296,17 +296,17 @@ system.cpu.op_class::SimdFloatMisc             107822      0.01%     69.56% # Cl
 system.cpu.op_class::SimdFloatMult                  0      0.00%     69.56% # Class of executed instruction
 system.cpu.op_class::SimdFloatMultAcc               0      0.00%     69.56% # Class of executed instruction
 system.cpu.op_class::SimdFloatSqrt                  0      0.00%     69.56% # Class of executed instruction
-system.cpu.op_class::MemRead                183711405     15.91%     85.47% # Class of executed instruction
-system.cpu.op_class::MemWrite               167826901     14.53%    100.00% # Class of executed instruction
+system.cpu.op_class::MemRead                183711282     15.91%     85.47% # Class of executed instruction
+system.cpu.op_class::MemWrite               167826773     14.53%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                 1154931007                       # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements          11605970                       # number of replacements
+system.cpu.op_class::total                 1154930294                       # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements          11606056                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.999719                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           339855114                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs          11606482                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             29.281492                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.total_refs           339854782                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs          11606568                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             29.281247                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle          33050500                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.tags.occ_blocks::cpu.data   511.999719                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999999                       # Average percentage of cache occupancy
@@ -316,87 +316,87 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0          199
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          297                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           16                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1417452931                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1417452931                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data    171110382                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       171110382                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    159073547                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      159073547                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       424481                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        424481                       # number of SoftPFReq hits
+system.cpu.dcache.tags.tag_accesses        1417452033                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1417452033                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data    171110167                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       171110167                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    159090000                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      159090000                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       424478                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        424478                       # number of SoftPFReq hits
 system.cpu.dcache.WriteLineReq_hits::cpu.data       336283                       # number of WriteLineReq hits
 system.cpu.dcache.WriteLineReq_hits::total       336283                       # number of WriteLineReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      4303643                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      4303643                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data      4555646                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      4555646                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     330520212                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        330520212                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    330944693                       # number of overall hits
-system.cpu.dcache.overall_hits::total       330944693                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      6002738                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       6002738                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2568126                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2568126                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data      1586184                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total      1586184                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      4303639                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      4303639                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      4555644                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      4555644                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     330536450                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        330536450                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    330960928                       # number of overall hits
+system.cpu.dcache.overall_hits::total       330960928                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      6002834                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       6002834                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2551547                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2551547                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data      1586190                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total      1586190                       # number of SoftPFReq misses
 system.cpu.dcache.WriteLineReq_misses::cpu.data      1246772                       # number of WriteLineReq misses
 system.cpu.dcache.WriteLineReq_misses::total      1246772                       # number of WriteLineReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data       253806                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total       253806                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data       253808                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total       253808                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            1                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      9817636                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        9817636                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     11403820                       # number of overall misses
-system.cpu.dcache.overall_misses::total      11403820                       # number of overall misses
-system.cpu.dcache.ReadReq_accesses::cpu.data    177113120                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    177113120                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    161641673                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    161641673                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data      2010665                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total      2010665                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data      9801153                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        9801153                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     11387343                       # number of overall misses
+system.cpu.dcache.overall_misses::total      11387343                       # number of overall misses
+system.cpu.dcache.ReadReq_accesses::cpu.data    177113001                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    177113001                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    161641547                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    161641547                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data      2010668                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total      2010668                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.WriteLineReq_accesses::cpu.data      1583055                       # number of WriteLineReq accesses(hits+misses)
 system.cpu.dcache.WriteLineReq_accesses::total      1583055                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4557449                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      4557449                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data      4555647                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      4555647                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    340337848                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    340337848                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    342348513                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    342348513                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.033892                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.033892                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015888                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.015888                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.788885                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.788885                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4557447                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      4557447                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data      4555645                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      4555645                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    340337603                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    340337603                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    342348271                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    342348271                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.033893                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.033893                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015785                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.015785                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.788887                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.788887                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.787573                       # miss rate for WriteLineReq accesses
 system.cpu.dcache.WriteLineReq_miss_rate::total     0.787573                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.055690                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.055690                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.055691                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.055691                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000000                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.028847                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.028847                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.033311                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.033311                       # miss rate for overall accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.028798                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.028798                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.033262                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.033262                       # miss rate for overall accesses
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks      8916642                       # number of writebacks
-system.cpu.dcache.writebacks::total           8916642                       # number of writebacks
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements          14265273                       # number of replacements
+system.cpu.dcache.writebacks::writebacks      8918956                       # number of writebacks
+system.cpu.dcache.writebacks::total           8918956                       # number of writebacks
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements          14265255                       # number of replacements
 system.cpu.icache.tags.tagsinuse           511.984599                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           968524390                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs          14265785                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             67.891419                       # Average number of references to valid blocks.
+system.cpu.icache.tags.total_refs           968523793                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs          14265767                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             67.891463                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle        6061932500                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.tags.occ_blocks::cpu.inst   511.984599                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.999970                       # Average percentage of cache occupancy
@@ -406,27 +406,27 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0          184
 system.cpu.icache.tags.age_task_id_blocks_1024::1          239                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2           89                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         997055970                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        997055970                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst    968524390                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       968524390                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     968524390                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        968524390                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    968524390                       # number of overall hits
-system.cpu.icache.overall_hits::total       968524390                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst     14265790                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total      14265790                       # number of ReadReq misses
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-system.cpu.icache.demand_misses::total       14265790                       # number of demand (read+write) misses
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-system.cpu.icache.overall_misses::total      14265790                       # number of overall misses
-system.cpu.icache.ReadReq_accesses::cpu.inst    982790180                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    982790180                       # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.overall_accesses::total    982790180                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses         997055337                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        997055337                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst    968523793                       # number of ReadReq hits
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 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014516                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.014516                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.014516                       # miss rate for demand accesses
@@ -439,200 +439,200 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks     14265273                       # number of writebacks
-system.cpu.icache.writebacks::total          14265273                       # number of writebacks
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.writebacks::writebacks     14265255                       # number of writebacks
+system.cpu.icache.writebacks::total          14265255                       # number of writebacks
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements          1725823                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65319.568119                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           46895862                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1788839                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            26.215809                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle        395986000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 37200.621218                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   312.625793                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   449.901085                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  6075.914096                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 21280.505928                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.567636                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004770                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006865                       # Average percentage of cache occupancy
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-system.cpu.l2cache.tags.occ_task_id_blocks::1024        62699                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4          317                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          136                       # Occupied blocks per task id
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-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004837                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.956711                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        425623617                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       425623617                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
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-system.cpu.l2cache.WritebackDirty_hits::writebacks      8916642                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      8916642                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks     14263696                       # number of WritebackClean hits
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 system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1246772                       # number of InvalidateReq accesses(hits+misses)
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-system.cpu.l2cache.overall_accesses::cpu.dtb.walker       515564                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker       261790                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst     14265790                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data     10359723                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total     25402867                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.012561                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.022296                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.015840                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.780877                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.780877                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker       486582                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker       243206                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst     14265772                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data     10359809                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total     25355369                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker       486582                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker       243206                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst     14265772                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data     10359809                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total     25355369                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.013309                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.024000                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.016872                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.112178                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.112178                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.328808                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.328808                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005819                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005819                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.043876                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.043876                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.442913                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::total     0.442913                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.012561                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.022296                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005819                       # miss rate for demand accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.328810                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.328810                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005818                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005818                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.043877                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.043877                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.442915                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::total     0.442915                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.013309                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.024000                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005818                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.113103                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.049878                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.012561                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.022296                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005819                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.049971                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.013309                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.024000                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005818                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.113103                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.049878                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.049971                       # miss rate for overall accesses
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks      1507088                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1507088                       # number of writebacks
-system.cpu.toL2Bus.snoop_filter.tot_requests     52384615                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests     26512337                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.writebacks::writebacks      1507096                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1507096                       # number of writebacks
+system.cpu.toL2Bus.snoop_filter.tot_requests     52368206                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests     26495860                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1744                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         2693                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2693                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         2694                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2694                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadReq        1229989                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      23338507                       # Transaction distribution
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadReq        1229979                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      23338583                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         33606                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        33606                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      8916642                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean     14265273                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      2689328                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq        51131                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      8918956                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean     14265255                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      2687100                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq        34570                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            1                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp        51132                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      2516995                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      2516995                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq     14265790                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      7842728                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp        34571                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      2516977                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      2516977                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq     14265772                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      7842832                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::InvalidateReq      1246772                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::InvalidateResp      1246772                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     42883103                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     35055544                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     42883049                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     35022680                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       758208                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1548412                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          80245267                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1826160532                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1233877030                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1548392                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          80212329                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1826158228                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1234030630                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      3032832                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6193648                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         3069264042                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     1957594                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic             103278016                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples     55015054                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.010836                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.103531                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6193568                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         3069415258                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1762518                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic              96494656                       # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples     54803543                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.010878                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.103729                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           54418911     98.92%     98.92% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             596143      1.08%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           54207383     98.91%     98.91% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             596160      1.09%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       55015054                       # Request fanout histogram
-system.iobus.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.snoop_fanout::total       54803543                       # Request fanout histogram
+system.iobus.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 system.iobus.trans_dist::ReadReq                40242                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               40242                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136515                       # Transaction distribution
@@ -675,13 +675,13 @@ system.iobus.pkt_size_system.realview.ide.dma::total      7334248
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  7491944                       # Cumulative packet size per connected master and slave (bytes)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 system.iocache.tags.replacements               115459                       # number of replacements
 system.iocache.tags.tagsinuse               10.407111                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs               115475                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13082113306009                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.warmup_cycle         13082113307009                       # Cycle when the warmup percentage was hit.
 system.iocache.tags.occ_blocks::realview.ethernet     3.554597                       # Average occupied blocks per requestor
 system.iocache.tags.occ_blocks::realview.ide     6.852514                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::realview.ethernet     0.222162                       # Average percentage of cache occupancy
@@ -692,7 +692,7 @@ system.iocache.tags.age_task_id_blocks_1023::3           16
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
 system.iocache.tags.tag_accesses              1039650                       # Number of tag accesses
 system.iocache.tags.data_accesses             1039650                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
+system.iocache.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
 system.iocache.ReadReq_misses::realview.ide         8813                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total             8850                       # number of ReadReq misses
@@ -740,65 +740,71 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.writebacks::writebacks          106631                       # number of writebacks
 system.iocache.writebacks::total               106631                       # number of writebacks
-system.membus.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
+system.membus.snoop_filter.tot_requests       3778694                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests      1875355                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests         2861                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
+system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadReq               76679                       # Transaction distribution
-system.membus.trans_dist::ReadResp             524962                       # Transaction distribution
+system.membus.trans_dist::ReadResp             524960                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33606                       # Transaction distribution
 system.membus.trans_dist::WriteResp             33606                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1613719                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           226329                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            40494                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1613727                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           226320                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4445                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           40495                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            827052                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           827052                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        448283                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        658869                       # Transaction distribution
-system.membus.trans_dist::InvalidateResp       658869                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4446                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            827049                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           827049                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        448281                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        658871                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp       658871                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122480                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6654                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5534331                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      5663523                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5462226                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      5591418                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       346493                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       346493                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                6010016                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5937911                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155610                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13308                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    177701792                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    177870842                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    177701984                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    177871034                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7390784                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      7390784                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               185261626                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               185261818                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
 system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples           3925032                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::samples           3888979                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.009406                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.096529                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 3925032    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 3852398     99.06%     99.06% # Request fanout histogram
+system.membus.snoop_fanout::1                   36581      0.94%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3925032                       # Request fanout histogram
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
+system.membus.snoop_fanout::total             3888979                       # Request fanout histogram
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
 system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
 system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
 system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
 system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
 system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
@@ -841,28 +847,28 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000                       # Cumulative time (in ticks) in various power states
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
index 815a8f351..c73396a86 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
@@ -1,168 +1,168 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 47.403575                       # Number of seconds simulated
-sim_ticks                                47403574916500                       # Number of ticks simulated
-final_tick                               47403574916500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 47.374315                       # Number of seconds simulated
+sim_ticks                                47374315410500                       # Number of ticks simulated
+final_tick                               47374315410500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 473223                       # Simulator instruction rate (inst/s)
-host_op_rate                                   556671                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            25492174892                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 749540                       # Number of bytes of host memory used
-host_seconds                                  1859.53                       # Real time elapsed on the host
-sim_insts                                   879974755                       # Number of instructions simulated
-sim_ops                                    1035148021                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 573964                       # Simulator instruction rate (inst/s)
+host_op_rate                                   675116                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            30496109280                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 762100                       # Number of bytes of host memory used
+host_seconds                                  1553.45                       # Real time elapsed on the host
+sim_insts                                   891626325                       # Number of instructions simulated
+sim_ops                                    1048762579                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.dtb.walker       121792                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       126720                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          3082292                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         13718664                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher     15413504                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       111872                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       105344                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          2806840                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          9358928                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher     11301824                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        428736                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             56576516                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      3082292                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      2806840                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5889132                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     75184384                       # Number of bytes written to this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu0.dtb.walker       107264                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker       103104                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          3762996                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         12951880                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher     13484096                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       112000                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       117056                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          2426936                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         10199632                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher     12856576                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        431488                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             56553028                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      3762996                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      2426936                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         6189932                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     74832448                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          75204968                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         1903                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         1980                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             88568                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            214367                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       240836                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         1748                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         1646                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             43945                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            146246                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher       176591                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6699                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                924529                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1174756                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          74853032                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         1676                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         1611                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             99204                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            202386                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       210689                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         1750                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         1829                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             38009                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            159382                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher       200884                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6742                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                924162                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1169257                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1177330                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          2569                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          2673                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               65022                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              289401                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher       325155                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          2360                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          2222                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               59212                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              197431                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       238417                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             9044                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1193507                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          65022                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          59212                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             124234                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1586049                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1171831                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          2264                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          2176                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               79431                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              273395                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher       284629                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          2364                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          2471                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               51229                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              215299                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       271383                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             9108                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1193749                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          79431                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          51229                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             130660                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1579600                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data                434                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1586483                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1586049                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         2569                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         2673                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              65022                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             289836                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher       325155                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         2360                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         2222                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              59212                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             197431                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       238417                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            9044                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2779990                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        924529                       # Number of read requests accepted
-system.physmem.writeReqs                      1177330                       # Number of write requests accepted
-system.physmem.readBursts                      924529                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1177330                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 59142848                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     27008                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  75203008                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  56576516                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               75204968                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      422                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2259                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bw_write::total                1580034                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1579600                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         2264                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         2176                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              79431                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             273829                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher       284629                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         2364                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         2471                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              51229                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             215299                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       271383                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            9108                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2773783                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        924162                       # Number of read requests accepted
+system.physmem.writeReqs                      1171831                       # Number of write requests accepted
+system.physmem.readBursts                      924162                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1171831                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 59123712                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     22656                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  74852544                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  56553028                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               74853032                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      354                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2245                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               51848                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               60547                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               52943                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               59873                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               53995                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               59394                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               55656                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               56350                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               47470                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               98045                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              51346                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              58216                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              52575                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              60842                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              50185                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              54822                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               69717                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               76530                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               71410                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               77292                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               71372                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               75019                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               75211                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               75617                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               67898                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               76939                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              70016                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              75357                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              71664                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              78615                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              70257                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              72133                       # Per bank write bursts
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+system.physmem.perBankRdBursts::5               67623                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               62592                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               58195                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               51047                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               95684                       # Per bank write bursts
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+system.physmem.perBankRdBursts::14              49130                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              49949                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               71660                       # Per bank write bursts
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+system.physmem.perBankWrBursts::10              67611                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              70918                       # Per bank write bursts
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+system.physmem.perBankWrBursts::14              70570                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              72018                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          33                       # Number of times write queue was full causing retry
-system.physmem.totGap                    47403571626000                       # Total gap between requests
+system.physmem.numWrRetry                          85                       # Number of times write queue was full causing retry
+system.physmem.totGap                    47374312061000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                   43195                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       5                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  881304                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  880937                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1174756                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    659566                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     77579                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::20                        7                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1169257                       # Write request sizes (log2)
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+system.physmem.rdQLenPdf::20                        3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
@@ -189,169 +189,173 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::52                      232                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::59                      130                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::62                       67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       98                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       970623                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      138.411655                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      95.318742                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     185.703174                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         665453     68.56%     68.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       189210     19.49%     88.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        42199      4.35%     92.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        19114      1.97%     94.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        13470      1.39%     95.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         8660      0.89%     96.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         6031      0.62%     97.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         4990      0.51%     97.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        21496      2.21%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         970623                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         60964                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        15.158028                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      130.577791                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          60961    100.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                    29578                       # What write queue length does an incoming req see
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+system.physmem.bytesPerActivate::samples       927168                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      144.500035                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      98.409552                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     191.008164                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         615708     66.41%     66.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       189300     20.42%     86.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        44500      4.80%     91.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        20695      2.23%     93.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        14869      1.60%     95.46% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::768-895         6380      0.69%     97.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         5518      0.60%     97.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        21025      2.27%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         927168                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         60983                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        15.148533                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      130.608088                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          60979     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            2      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::20480-21503            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::23552-24575            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           60964                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         60964                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        19.274441                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.533375                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        7.742081                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           49066     80.48%     80.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23            4709      7.72%     88.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27            2977      4.88%     93.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31            1753      2.88%     95.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             988      1.62%     97.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             316      0.52%     98.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             174      0.29%     98.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47             124      0.20%     98.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              67      0.11%     98.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              44      0.07%     98.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              37      0.06%     98.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              48      0.08%     98.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             425      0.70%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              48      0.08%     99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              48      0.08%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              40      0.07%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              26      0.04%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.00%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               2      0.00%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               3      0.00%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               3      0.00%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.00%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             2      0.00%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111            10      0.02%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             2      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            27      0.04%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             3      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             4      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             6      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             3      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           60964                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    29056215697                       # Total ticks spent queuing
-system.physmem.totMemAccLat               46383221947                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   4620535000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       31442.48                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total           60983                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         60983                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        19.178640                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.436589                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        7.785486                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           49393     80.99%     80.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23            4571      7.50%     88.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27            2800      4.59%     93.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31            1776      2.91%     95.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35            1006      1.65%     97.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             308      0.51%     98.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             149      0.24%     98.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47             125      0.20%     98.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              64      0.10%     98.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              38      0.06%     98.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              29      0.05%     98.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              41      0.07%     98.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             435      0.71%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              54      0.09%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              52      0.09%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              40      0.07%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              33      0.05%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               5      0.01%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               3      0.00%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               1      0.00%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               5      0.01%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.00%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             2      0.00%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             5      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             3      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             1      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            14      0.02%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             3      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             3      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             4      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             1      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             9      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::212-215             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-243             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           60983                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    30413749694                       # Total ticks spent queuing
+system.physmem.totMemAccLat               47735149694                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   4619040000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       32922.15                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  50192.48                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  51672.15                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           1.25                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.59                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.58                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        1.19                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.59                       # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.58                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.06                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        22.95                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     688543                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    439987                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   74.51                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  37.44                       # Row buffer hit rate for writes
-system.physmem.avgGap                     22553164.43                       # Average gap between requests
-system.physmem.pageHitRate                      53.76                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 3707333280                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 2022850500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                3514687800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3837248640                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3096170747280                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1188225117900                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           27399839328750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             31697317314150                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.669411                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   45581711195731                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1582909380000                       # Time in different power states
+system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.27                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     683627                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    482581                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   74.00                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  41.26                       # Row buffer hit rate for writes
+system.physmem.avgGap                     22602323.61                       # Average gap between requests
+system.physmem.pageHitRate                      55.71                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 3700302480                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 2019014250                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                3695975400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3926705040                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3094259578800                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1192499073090                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           27378533808750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             31678634457810                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.688048                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   45546210437205                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1581932300000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    238953890769                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    246167130795                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 3630576600                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 1980969375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                3693307800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3777055920                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3096170747280                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1193695955100                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           27395040340500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             31697988952575                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.683580                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   45573641620138                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1582909380000                       # Time in different power states
+system.physmem_1.actEnergy                 3308936400                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1805471250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                3509181000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3651784560                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3094259578800                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1178425765395                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           27390878815500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             31675839532905                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.629051                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   45566794873385                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1581932300000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    247019106112                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    225582219115                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
 system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst           64                       # Number of bytes read from this memory
@@ -378,17 +382,17 @@ system.realview.nvmem.bw_total::cpu0.data            1                       # T
 system.realview.nvmem.bw_total::cpu1.inst            1                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total               4                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
-system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
+system.cf0.dma_write_full_pages                  1671                       # Number of full page size DMA writes.
+system.cf0.dma_write_bytes                    6846976                       # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs                         1674                       # Number of DMA write transactions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -418,75 +422,73 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.cpu0.dtb.walker.walks                   114038                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               114038                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        12642                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        85549                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore           19                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples       114019                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean     0.228032                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev    76.998938                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-2047       114018    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::24576-26623            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       114019                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples        98210                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 22487.465635                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 21018.091466                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 14315.982425                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-32767        93486     95.19%     95.19% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-65535         3452      3.51%     98.70% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-98303          155      0.16%     98.86% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::98304-131071          934      0.95%     99.81% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-163839           21      0.02%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::163840-196607           20      0.02%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-229375           48      0.05%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::229376-262143           12      0.01%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-294911           37      0.04%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::294912-327679           30      0.03%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-360447            5      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::360448-393215            5      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.walker.walks                   101108                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               101108                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2         9051                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        76906                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore           14                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples       101094                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0         101094    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       101094                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples        85971                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 24170.842493                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 22339.898543                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 14600.032387                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-32767        76182     88.61%     88.61% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-65535         8727     10.15%     98.76% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-98303          200      0.23%     99.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::98304-131071          718      0.84%     99.83% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-163839           29      0.03%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::163840-196607           15      0.02%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-229375           34      0.04%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::229376-262143           15      0.02%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-294911           12      0.01%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::294912-327679           19      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-360447           11      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::360448-393215            4      0.00%     99.99% # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walkCompletionTime::393216-425983            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total        98210                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples   3576910072                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     1.522403                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0    -1868589580    -52.24%    -52.24% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1     5445499652    152.24%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total   3576910072                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        85549     87.13%     87.13% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M        12642     12.87%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total        98191                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       114038                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkCompletionTime::total        85971                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples   -250064880                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.334382                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.471774                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0     -166447796     66.56%     66.56% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1      -83617084     33.44%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total   -250064880                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        76906     89.47%     89.47% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M         9051     10.53%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total        85957                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       101108                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       114038                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        98191                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       101108                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        85957                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        98191                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       212229                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        85957                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       187065                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    86092375                       # DTB read hits
-system.cpu0.dtb.read_misses                     87013                       # DTB read misses
-system.cpu0.dtb.write_hits                   77928513                       # DTB write hits
-system.cpu0.dtb.write_misses                    27025                       # DTB write misses
+system.cpu0.dtb.read_hits                    84046306                       # DTB read hits
+system.cpu0.dtb.read_misses                     73432                       # DTB read misses
+system.cpu0.dtb.write_hits                   77237834                       # DTB write hits
+system.cpu0.dtb.write_misses                    27676                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              41066                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                   1040                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   38112                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_tlb_mva_asid              41711                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                   1058                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   35922                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  4351                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                  4635                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                     9561                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                86179388                       # DTB read accesses
-system.cpu0.dtb.write_accesses               77955538                       # DTB write accesses
+system.cpu0.dtb.perms_faults                     9711                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                84119738                       # DTB read accesses
+system.cpu0.dtb.write_accesses               77265510                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        164020888                       # DTB hits
-system.cpu0.dtb.misses                         114038                       # DTB misses
-system.cpu0.dtb.accesses                    164134926                       # DTB accesses
-system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.hits                        161284140                       # DTB hits
+system.cpu0.dtb.misses                         101108                       # DTB misses
+system.cpu0.dtb.accesses                    161385248                       # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -516,891 +518,888 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.cpu0.itb.walker.walks                    57747                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong                57747                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2          561                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3        51498                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples        57747                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0          57747    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        57747                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples        52059                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 25570.833093                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 23301.899076                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 19704.068320                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-32767        48075     92.35%     92.35% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-65535         2753      5.29%     97.64% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-98303           34      0.07%     97.70% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::98304-131071         1024      1.97%     99.67% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-163839           15      0.03%     99.70% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::163840-196607           13      0.02%     99.72% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-229375           43      0.08%     99.80% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::229376-262143           19      0.04%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-294911           37      0.07%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::294912-327679           21      0.04%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-360447            6      0.01%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::360448-393215            5      0.01%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-425983            6      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::425984-458751            3      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-491519            3      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::491520-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total        52059                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.cpu0.itb.walker.walks                    58460                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                58460                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2          540                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        52669                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples        58460                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0          58460    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        58460                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        53209                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 26190.982728                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 24044.890366                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 17871.734437                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-32767        47169     88.65%     88.65% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-65535         4943      9.29%     97.94% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-98303           65      0.12%     98.06% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::98304-131071          859      1.61%     99.67% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-163839           39      0.07%     99.75% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::163840-196607           17      0.03%     99.78% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-229375           47      0.09%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::229376-262143           13      0.02%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-294911           25      0.05%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::294912-327679           20      0.04%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-360447            7      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::360448-393215            1      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-425983            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total        53209                       # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walksPending::samples   -282313796                       # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::0     -282313796    100.00%    100.00% # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::total   -282313796                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        51498     98.92%     98.92% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M          561      1.08%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        52059                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::4K        52669     98.99%     98.99% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M          540      1.01%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        53209                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        57747                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        57747                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        58460                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        58460                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        52059                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        52059                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       109806                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   458544228                       # ITB inst hits
-system.cpu0.itb.inst_misses                     57747                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        53209                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        53209                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       111669                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   449335815                       # ITB inst hits
+system.cpu0.itb.inst_misses                     58460                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              41066                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                   1040                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   26949                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              41711                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                   1058                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   24946                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               458601975                       # ITB inst accesses
-system.cpu0.itb.hits                        458544228                       # DTB hits
-system.cpu0.itb.misses                          57747                       # DTB misses
-system.cpu0.itb.accesses                    458601975                       # DTB accesses
-system.cpu0.numPwrStateTransitions              27516                       # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples        13758                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean    3404463734.886103                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev   97180881292.374130                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::underflows         3759     27.32%     27.32% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10         9972     72.48%     99.80% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::5e+10-1e+11           11      0.08%     99.88% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11            1      0.01%     99.90% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11            1      0.01%     99.91% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11            1      0.01%     99.91% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::overflows           12      0.09%    100.00% # Distribution of time spent in the clock gated state
+system.cpu0.itb.inst_accesses               449394275                       # ITB inst accesses
+system.cpu0.itb.hits                        449335815                       # DTB hits
+system.cpu0.itb.misses                          58460                       # DTB misses
+system.cpu0.itb.accesses                    449394275                       # DTB accesses
+system.cpu0.numPwrStateTransitions               8624                       # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples         4312                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean    10857440365.954313                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev   156382311444.961365                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows         3059     70.94%     70.94% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10         1229     28.50%     99.44% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11            2      0.05%     99.49% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11            2      0.05%     99.54% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11            2      0.05%     99.58% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::5e+11-5.5e+11            1      0.02%     99.61% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11            1      0.02%     99.63% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11            1      0.02%     99.65% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11            1      0.02%     99.68% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::overflows           14      0.32%    100.00% # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::max_value 7033293879000                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total          13758                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON   564962851937                       # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 46838612064563                       # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles                     94807149833                       # number of cpu cycles simulated
+system.cpu0.pwrStateClkGateDist::max_value 7470353528320                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total           4312                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON   557032552505                       # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 46817282857995                       # Cumulative time (in ticks) in various power states
+system.cpu0.numCycles                     94748630821                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   13758                       # number of quiesce instructions executed
-system.cpu0.committedInsts                  458270897                       # Number of instructions committed
-system.cpu0.committedOps                    538093671                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            494447989                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                420942                       # Number of float alu accesses
-system.cpu0.num_func_calls                   27507374                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     69395953                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   494447989                       # number of integer instructions
-system.cpu0.num_fp_insts                       420942                       # number of float instructions
-system.cpu0.num_int_register_reads          717601691                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         392303230                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads              699105                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             312628                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           119518995                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes          119177994                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                    164010919                       # number of memory refs
-system.cpu0.num_load_insts                   86087147                       # Number of load instructions
-system.cpu0.num_store_insts                  77923772                       # Number of store instructions
-system.cpu0.num_idle_cycles              93677224129.124023                       # Number of idle cycles
-system.cpu0.num_busy_cycles              1129925703.875976                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.011918                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.988082                       # Percentage of idle cycles
-system.cpu0.Branches                        102213618                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                373117768     69.30%     69.30% # Class of executed instruction
-system.cpu0.op_class::IntMult                 1177948      0.22%     69.52% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    60910      0.01%     69.53% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc             42581      0.01%     69.54% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.54% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.54% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.54% # Class of executed instruction
-system.cpu0.op_class::MemRead                86087147     15.99%     85.53% # Class of executed instruction
-system.cpu0.op_class::MemWrite               77923772     14.47%    100.00% # Class of executed instruction
+system.cpu0.kern.inst.quiesce                    4312                       # number of quiesce instructions executed
+system.cpu0.committedInsts                  449083110                       # Number of instructions committed
+system.cpu0.committedOps                    528384419                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            485390643                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                507449                       # Number of float alu accesses
+system.cpu0.num_func_calls                   26866500                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     68160489                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   485390643                       # number of integer instructions
+system.cpu0.num_fp_insts                       507449                       # number of float instructions
+system.cpu0.num_int_register_reads          703891240                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         384865941                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads              816779                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes             435492                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads           117650799                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes          117386896                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                    161276211                       # number of memory refs
+system.cpu0.num_load_insts                   84042257                       # Number of load instructions
+system.cpu0.num_store_insts                  77233954                       # Number of store instructions
+system.cpu0.num_idle_cycles              93634565715.988022                       # Number of idle cycles
+system.cpu0.num_busy_cycles              1114065105.011976                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.011758                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.988242                       # Percentage of idle cycles
+system.cpu0.Branches                        100200450                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                366086093     69.25%     69.25% # Class of executed instruction
+system.cpu0.op_class::IntMult                 1185979      0.22%     69.47% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    59083      0.01%     69.48% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     69.48% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     69.48% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     69.48% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     69.48% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     69.48% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     69.48% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     69.48% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.48% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     69.48% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     69.48% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     69.48% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     69.48% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     69.48% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.48% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     69.48% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.48% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     69.48% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  8      0.00%     69.48% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.48% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                 13      0.00%     69.48% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                 21      0.00%     69.48% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.48% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc             72839      0.01%     69.49% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.49% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.49% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.49% # Class of executed instruction
+system.cpu0.op_class::MemRead                84042257     15.90%     85.39% # Class of executed instruction
+system.cpu0.op_class::MemWrite               77233954     14.61%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 538410126                       # Class of executed instruction
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements          5755741                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          471.832715                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          158017240                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          5756252                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            27.451411                       # Average number of references to valid blocks.
+system.cpu0.op_class::total                 528680248                       # Class of executed instruction
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.tags.replacements          5566798                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          502.671926                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          155470196                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          5567308                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            27.925560                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle       4031081000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   471.832715                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.921548                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.921548                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0           21                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          181                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2          308                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        333769183                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       333769183                       # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data     80089936                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       80089936                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     73524451                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      73524451                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       195750                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       195750                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       158273                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       158273                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1825906                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      1825906                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1807959                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      1807959                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    153772660                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       153772660                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    153968410                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      153968410                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      3122111                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      3122111                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1430717                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1430717                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       657703                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       657703                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       783281                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total       783281                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       173414                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       173414                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data       190134                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total       190134                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      5336109                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       5336109                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      5993812                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      5993812                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  46238724000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  46238724000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  29544894000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  29544894000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  25637315000                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total  25637315000                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2487014500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   2487014500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4740803500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total   4740803500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      2810500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total      2810500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 101420933000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 101420933000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 101420933000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 101420933000                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     83212047                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     83212047                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     74955168                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     74955168                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       853453                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       853453                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       941554                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total       941554                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1999320                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      1999320                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1998093                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      1998093                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    159108769                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    159108769                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    159962222                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    159962222                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.037520                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.037520                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.019088                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.019088                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.770638                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.770638                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.831902                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.831902                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.086736                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.086736                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.095158                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.095158                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.033537                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.033537                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.037470                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.037470                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14810.083306                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14810.083306                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20650.410948                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 20650.410948                       # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32730.673922                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32730.673922                       # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14341.486270                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14341.486270                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24934.012328                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24934.012328                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   502.671926                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.981781                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.981781                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0           60                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          419                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           31                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses        328131694                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       328131694                       # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.ReadReq_hits::cpu0.data     78275725                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       78275725                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     72837974                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      72837974                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       200143                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       200143                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       232092                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       232092                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1764306                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      1764306                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1721538                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      1721538                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    151345791                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       151345791                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    151545934                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      151545934                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      2974115                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      2974115                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1412109                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1412109                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       649854                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       649854                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       801670                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total       801670                       # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       161158                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       161158                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data       202775                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total       202775                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      5187894                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       5187894                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      5837748                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      5837748                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  44497648000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  44497648000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  28844482000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  28844482000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  25694293000                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total  25694293000                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2462602000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   2462602000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4821620000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total   4821620000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      2416000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total      2416000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  99036423000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  99036423000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  99036423000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  99036423000                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     81249840                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     81249840                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     74250083                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     74250083                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       849997                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       849997                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data      1033762                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total      1033762                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1925464                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      1925464                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1924313                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      1924313                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    156533685                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    156533685                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    157383682                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    157383682                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.036605                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.036605                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.019018                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.019018                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.764537                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.764537                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.775488                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.775488                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.083698                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.083698                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.105375                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.105375                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.033142                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.033142                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.037092                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.037092                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14961.643380                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14961.643380                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20426.526564                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 20426.526564                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32050.959871                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32050.959871                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15280.668661                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15280.668661                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23778.177783                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23778.177783                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19006.533225                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 19006.533225                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16920.939963                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 16920.939963                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19089.908738                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 19089.908738                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16964.833528                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 16964.833528                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks      5755741                       # number of writebacks
-system.cpu0.dcache.writebacks::total          5755741                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        25545                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total        25545                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data        21233                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total        21233                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        44607                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        44607                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data        46778                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total        46778                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data        46778                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total        46778                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3096566                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      3096566                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1409484                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1409484                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       656541                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       656541                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       783281                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total       783281                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       128807                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       128807                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       190134                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total       190134                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      5289331                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      5289331                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      5945872                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      5945872                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        27575                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        27575                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        26540                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        26540                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        54115                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        54115                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  42074729000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  42074729000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  27794776000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  27794776000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  13747691500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  13747691500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  24854034000                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  24854034000                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1645535500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1645535500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   4550721500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   4550721500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      2758500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2758500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  94723539000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  94723539000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 108471230500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 108471230500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5071681500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5071681500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5071681500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   5071681500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.037213                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.037213                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018804                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018804                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.769276                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.769276                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.831902                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.831902                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.064425                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.064425                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.095158                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.095158                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.033243                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.033243                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.037170                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.037170                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13587.544719                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13587.544719                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19719.823709                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19719.823709                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20939.578031                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20939.578031                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31730.673922                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31730.673922                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12775.202435                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12775.202435                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23934.285819                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23934.285819                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks      5566798                       # number of writebacks
+system.cpu0.dcache.writebacks::total          5566798                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        29633                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total        29633                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data        21518                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total        21518                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        45711                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        45711                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data        51151                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total        51151                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data        51151                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total        51151                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2944482                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      2944482                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1390591                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1390591                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       648168                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       648168                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       801670                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total       801670                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       115447                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       115447                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       202775                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total       202775                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      5136743                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      5136743                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      5784911                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      5784911                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        21025                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        21025                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        22388                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        22388                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        43413                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        43413                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  40085054500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  40085054500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  26946583500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  26946583500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  14957704500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  14957704500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  24892623000                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  24892623000                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1575244000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1575244000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   4618898000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   4618898000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      2363000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2363000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  91924261000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  91924261000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 106881965500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 106881965500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3989550000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3989550000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3989550000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3989550000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036240                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036240                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018728                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018728                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.762553                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.762553                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.775488                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.775488                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059958                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059958                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.105375                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.105375                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.032816                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.032816                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.036757                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.036757                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13613.618456                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13613.618456                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19377.792248                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19377.792248                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23076.894416                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23076.894416                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31050.959871                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31050.959871                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13644.737412                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13644.737412                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22778.439157                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22778.439157                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17908.415828                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17908.415828                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18243.115644                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18243.115644                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183923.173164                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183923.173164                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93720.437956                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93720.437956                       # average overall mshr uncacheable latency
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements          4916262                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.907947                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          453627454                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          4916774                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            92.261197                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      29905343000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.907947                       # Average occupied blocks per requestor
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17895.437050                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17895.437050                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18475.991333                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18475.991333                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189752.675386                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189752.675386                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 91897.588280                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 91897.588280                       # average overall mshr uncacheable latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.tags.replacements          5174135                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.907744                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          444161163                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          5174647                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            85.834099                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      30089682000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.907744                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999820                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.999820                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          241                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          215                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          265                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          186                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        922005230                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       922005230                       # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst    453627454                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      453627454                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    453627454                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       453627454                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    453627454                       # number of overall hits
-system.cpu0.icache.overall_hits::total      453627454                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      4916774                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      4916774                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      4916774                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       4916774                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      4916774                       # number of overall misses
-system.cpu0.icache.overall_misses::total      4916774                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  52276659500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  52276659500                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  52276659500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  52276659500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  52276659500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  52276659500                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    458544228                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    458544228                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    458544228                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    458544228                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    458544228                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    458544228                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.010723                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.010723                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.010723                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.010723                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.010723                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.010723                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10632.308807                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 10632.308807                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10632.308807                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 10632.308807                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10632.308807                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 10632.308807                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        903846282                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       903846282                       # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.ReadReq_hits::cpu0.inst    444161163                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      444161163                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    444161163                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       444161163                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    444161163                       # number of overall hits
+system.cpu0.icache.overall_hits::total      444161163                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      5174652                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      5174652                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      5174652                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       5174652                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      5174652                       # number of overall misses
+system.cpu0.icache.overall_misses::total      5174652                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  55704586500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  55704586500                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  55704586500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  55704586500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  55704586500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  55704586500                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    449335815                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    449335815                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    449335815                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    449335815                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    449335815                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    449335815                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.011516                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.011516                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.011516                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.011516                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.011516                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.011516                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10764.895205                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 10764.895205                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10764.895205                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 10764.895205                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10764.895205                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 10764.895205                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks      4916262                       # number of writebacks
-system.cpu0.icache.writebacks::total          4916262                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      4916774                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      4916774                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      4916774                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      4916774                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      4916774                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      4916774                       # number of overall MSHR misses
+system.cpu0.icache.writebacks::writebacks      5174135                       # number of writebacks
+system.cpu0.icache.writebacks::total          5174135                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      5174652                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      5174652                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      5174652                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      5174652                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      5174652                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      5174652                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total        43125                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total        43125                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  49818272500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  49818272500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  49818272500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  49818272500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  49818272500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  49818272500                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  53117260500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  53117260500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  53117260500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  53117260500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  53117260500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  53117260500                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   3819470000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   3819470000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   3819470000                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total   3819470000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.010723                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.010723                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.010723                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.010723                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.010723                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.010723                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10132.308807                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10132.308807                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10132.308807                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 10132.308807                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10132.308807                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 10132.308807                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.011516                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.011516                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.011516                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.011516                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.011516                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.011516                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10264.895205                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10264.895205                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10264.895205                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 10264.895205                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10264.895205                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 10264.895205                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88567.420290                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88567.420290                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      7829609                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      7829625                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit           14                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      7568346                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      7568354                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit            7                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage      1043159                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.tags.replacements         2362641                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16162.227513                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs          14986861                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs         2378231                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            6.301684                       # Average number of references to valid blocks.
+system.cpu0.l2cache.prefetcher.pfSpanPage       981182                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.cpu0.l2cache.tags.replacements         2342884                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       15723.839714                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs           9135802                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs         2358598                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            3.873404                       # Average number of references to valid blocks.
 system.cpu0.l2cache.tags.warmup_cycle      5100393500                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 15129.176557                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    55.599278                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    80.860024                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   896.591654                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.923412                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003394                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.004935                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.054724                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.986464                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1593                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_blocks::writebacks 15407.459260                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    38.158261                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    27.135006                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   251.087187                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.940397                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.002329                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.001656                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.015325                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.959707                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022          345                       # Occupied blocks per task id
 system.cpu0.l2cache.tags.occ_task_id_blocks::1023           72                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        13925                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          258                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          732                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          603                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           11                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           40                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           21                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          191                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         2612                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         5888                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         5210                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.097229                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15297                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           19                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          130                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          167                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4           29                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           18                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           53                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          118                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1333                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         5696                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7896                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4          254                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.021057                       # Percentage of cache occupancy per task id
 system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.004395                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.849915                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses       362405390                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses      362405390                       # Number of data accesses
-system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       268274                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       147126                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total        415400                       # number of ReadReq hits
-system.cpu0.l2cache.WritebackDirty_hits::writebacks      3821588                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackDirty_hits::total      3821588                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackClean_hits::writebacks      6849535                       # number of WritebackClean hits
-system.cpu0.l2cache.WritebackClean_hits::total      6849535                       # number of WritebackClean hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data          548                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total          548                       # number of UpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       933451                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       933451                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      4462897                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total      4462897                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2959469                       # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total      2959469                       # number of ReadSharedReq hits
-system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       207284                       # number of InvalidateReq hits
-system.cpu0.l2cache.InvalidateReq_hits::total       207284                       # number of InvalidateReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       268274                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker       147126                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      4462897                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data      3892920                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total        8771217                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       268274                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker       147126                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      4462897                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data      3892920                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total       8771217                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        10042                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         8210                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total        18252                       # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       241773                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total       241773                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       190127                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total       190127                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            7                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::total            7                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data       253021                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total       253021                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       453877                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::total       453877                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       922445                       # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total       922445                       # number of ReadSharedReq misses
-system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       574180                       # number of InvalidateReq misses
-system.cpu0.l2cache.InvalidateReq_misses::total       574180                       # number of InvalidateReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        10042                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker         8210                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst       453877                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data      1175466                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total      1647595                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        10042                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker         8210                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst       453877                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data      1175466                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total      1647595                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    376993500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    339890500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total    716884000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   1915432500                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total   1915432500                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   1581298000                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   1581298000                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      2680500                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      2680500                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  12742251999                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total  12742251999                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  15633345500                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::total  15633345500                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  32366023500                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::total  32366023500                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data    286150500                       # number of InvalidateReq miss cycles
-system.cpu0.l2cache.InvalidateReq_miss_latency::total    286150500                       # number of InvalidateReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    376993500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    339890500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst  15633345500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data  45108275499                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total  61458504999                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    376993500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    339890500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst  15633345500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data  45108275499                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total  61458504999                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       278316                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       155336                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total       433652                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::writebacks      3821588                       # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::total      3821588                       # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::writebacks      6849535                       # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::total      6849535                       # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       242321                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total       242321                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       190127                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total       190127                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            7                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            7                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1186472                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total      1186472                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      4916774                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::total      4916774                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      3881914                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::total      3881914                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       781464                       # number of InvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.InvalidateReq_accesses::total       781464                       # number of InvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       278316                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       155336                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst      4916774                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data      5068386                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total     10418812                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       278316                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       155336                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst      4916774                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data      5068386                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total     10418812                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.036081                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.052853                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.042089                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.997739                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.997739                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.933655                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses       370311903                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses      370311903                       # Number of data accesses
+system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       225709                       # number of ReadReq hits
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+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        18676                       # number of demand (read+write) misses
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+system.cpu0.l2cache.overall_misses::cpu0.data      1233929                       # number of overall misses
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+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    564732000                       # number of ReadReq miss cycles
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+system.cpu0.l2cache.ReadReq_miss_latency::total    936682000                       # number of ReadReq miss cycles
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+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    321936500                       # number of SCUpgradeReq miss cycles
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+system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  33121351500                       # number of ReadSharedReq miss cycles
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+system.cpu0.l2cache.InvalidateReq_miss_latency::total    399249500                       # number of InvalidateReq miss cycles
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+system.cpu0.l2cache.demand_miss_latency::cpu0.data  45747790498                       # number of demand (read+write) miss cycles
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+system.cpu0.l2cache.overall_miss_latency::cpu0.data  45747790498                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::total  63836411998                       # number of overall miss cycles
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+system.cpu0.l2cache.ReadReq_accesses::total       403160                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::writebacks      3696575                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::total      3696575                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::writebacks      7043197                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::total      7043197                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       251664                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total       251664                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       202763                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total       202763                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data           12                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::total           12                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1157220                       # number of ReadExReq accesses(hits+misses)
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+system.cpu0.l2cache.ReadCleanReq_accesses::total      5174652                       # number of ReadCleanReq accesses(hits+misses)
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+system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       799396                       # number of InvalidateReq accesses(hits+misses)
+system.cpu0.l2cache.InvalidateReq_accesses::total       799396                       # number of InvalidateReq accesses(hits+misses)
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+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       158775                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst      5174652                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data      4865317                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total     10443129                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.076420                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.066805                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.072634                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data            1                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.213255                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.213255                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.092312                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.092312                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.237626                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.237626                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.734749                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.734749                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.036081                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.052853                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.092312                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.231921                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.158137                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.036081                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.052853                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.092312                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.231921                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.158137                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 37541.674965                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 41399.573691                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 39277.010739                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  7922.441712                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  7922.441712                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  8317.061753                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  8317.061753                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 382928.571429                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 382928.571429                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50360.452291                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50360.452291                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 34444.013466                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 34444.013466                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 35087.212246                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 35087.212246                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data   498.363754                       # average InvalidateReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total   498.363754                       # average InvalidateReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 37541.674965                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 41399.573691                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34444.013466                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38374.802418                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 37301.949204                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 37541.674965                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 41399.573691                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34444.013466                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38374.802418                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 37301.949204                       # average overall miss latency
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.240693                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.240693                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.092581                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.092581                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.257651                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.257651                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.728943                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.728943                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.076420                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.066805                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.092581                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.253617                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.166836                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.076420                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.066805                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.092581                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.253617                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.166836                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 30238.380810                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 35066.465542                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31987.228085                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  3643.014098                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  3643.014098                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  1587.747765                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  1587.747765                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 190208.250000                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 190208.250000                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 45331.606434                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 45331.606434                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 35802.051653                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 35802.051653                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34667.740744                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34667.740744                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data   685.155153                       # average InvalidateReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total   685.155153                       # average InvalidateReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 30238.380810                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 35066.465542                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 35802.051653                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 37074.896933                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 36639.393349                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 30238.380810                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 35066.465542                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 35802.051653                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 37074.896933                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 36639.393349                       # average overall miss latency
 system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.l2cache.unused_prefetches           39736                       # number of HardPF blocks evicted w/o reference
-system.cpu0.l2cache.writebacks::writebacks      1527732                       # number of writebacks
-system.cpu0.l2cache.writebacks::total         1527732                       # number of writebacks
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         5839                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total         5839                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          307                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          307                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data         6146                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total         6146                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data         6146                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total         6146                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        10042                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         8210                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total        18252                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       748015                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       748015                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       241773                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total       241773                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       190127                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       190127                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            7                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            7                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       247182                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total       247182                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       453877                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       453877                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       922138                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       922138                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       574180                       # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::total       574180                       # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        10042                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         8210                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       453877                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1169320                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total      1641449                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        10042                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         8210                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       453877                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1169320                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       748015                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total      2389464                       # number of overall MSHR misses
+system.cpu0.l2cache.unused_prefetches           41508                       # number of HardPF blocks evicted w/o reference
+system.cpu0.l2cache.writebacks::writebacks      1560695                       # number of writebacks
+system.cpu0.l2cache.writebacks::total         1560695                       # number of writebacks
+system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         5412                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::total         5412                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          417                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          417                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.data         5829                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::total         5829                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.data         5829                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::total         5829                       # number of overall MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        18676                       # number of ReadReq MSHR misses
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+system.cpu0.l2cache.ReadReq_mshr_misses::total        29283                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       726457                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::total       726457                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       251664                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total       251664                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       202763                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       202763                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data           12                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total           12                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       273123                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::total       273123                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       479077                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       479077                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       954977                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       954977                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       582714                       # number of InvalidateReq MSHR misses
+system.cpu0.l2cache.InvalidateReq_mshr_misses::total       582714                       # number of InvalidateReq MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        18676                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker        10607                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       479077                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1228100                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::total      1736460                       # number of demand (read+write) MSHR misses
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+system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker        10607                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       479077                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1228100                       # number of overall MSHR misses
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+system.cpu0.l2cache.overall_mshr_misses::total      2462917                       # number of overall MSHR misses
 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        27575                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        70700                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        26540                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        26540                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        21025                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        64150                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        22388                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        22388                       # number of WriteReq MSHR uncacheable
 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        54115                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        97240                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    316741500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    290630500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    607372000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  33693542276                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  33693542276                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   5018820000                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   5018820000                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   3123659500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   3123659500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      2368500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2368500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  10716539999                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  10716539999                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  12910083500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  12910083500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  26808700000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  26808700000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  18844533500                       # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  18844533500                       # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    316741500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    290630500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  12910083500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  37525239999                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total  51042695499                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    316741500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    290630500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  12910083500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  37525239999                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  33693542276                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total  84736237775                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        43413                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        86538                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    452676000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    308308000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    760984000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  31463015041                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  31463015041                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   4662148500                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   4662148500                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   3097020500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   3097020500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1964499                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1964499                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  10454677998                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  10454677998                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  14277477500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  14277477500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  27353907000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  27353907000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  18732640000                       # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  18732640000                       # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    452676000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    308308000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  14277477500                       # number of demand (read+write) MSHR miss cycles
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+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    308308000                       # number of overall MSHR miss cycles
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+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  37808584998                       # number of overall MSHR miss cycles
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+system.cpu0.l2cache.overall_mshr_miss_latency::total  84310061539                       # number of overall MSHR miss cycles
 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   3496032500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   4850748500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   8346781000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   3820807000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   7316839500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   3496032500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   4850748500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   8346781000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.036081                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.052853                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.042089                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   3820807000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   7316839500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.076420                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.066805                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.072634                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.997739                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.997739                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.208334                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.208334                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.092312                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.092312                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.237547                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.237547                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.734749                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.734749                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.036081                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.052853                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.092312                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.230709                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.157547                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.036081                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.052853                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.092312                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.230709                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.236016                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.236016                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.092581                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.092581                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.257538                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.257538                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.728943                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.728943                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.076420                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.066805                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.092581                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.252419                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.166278                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.076420                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.066805                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.092581                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.252419                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.229341                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 31541.674965                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 35399.573691                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 33277.010739                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45043.939327                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45043.939327                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20758.397340                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20758.397340                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16429.331447                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16429.331447                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 338357.142857                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 338357.142857                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 43354.855932                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 43354.855932                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 28444.013466                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28444.013466                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 29072.329738                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29072.329738                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 32819.905779                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 32819.905779                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 31541.674965                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 35399.573691                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 28444.013466                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 32091.506174                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31096.120257                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 31541.674965                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 35399.573691                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 28444.013466                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 32091.506174                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45043.939327                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35462.445877                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.235841                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24238.380810                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 29066.465542                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25987.228085                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 43310.223511                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 43310.223511                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18525.289672                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18525.289672                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15274.090934                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15274.090934                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 163708.250000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 163708.250000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38278.277545                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38278.277545                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 29802.051653                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29802.051653                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28643.524399                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28643.524399                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 32147.228314                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 32147.228314                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24238.380810                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 29066.465542                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 29802.051653                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30786.242975                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30433.782810                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24238.380810                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 29066.465542                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 29802.051653                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30786.242975                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 43310.223511                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34231.791627                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 175911.097008                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 118059.137199                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 181726.848989                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 114058.293063                       # average ReadReq mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 89637.780652                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 85836.908680                       # average overall mshr uncacheable latency
-system.cpu0.toL2Bus.snoop_filter.tot_requests     22110497                       # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests     11343995                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests          879                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops      1795730                       # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops      1795410                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops          320                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.cpu0.toL2Bus.trans_dist::ReadReq        572087                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp      9462372                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        26540                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        26540                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty      5352908                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean      6850414                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict      2268094                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq       917561                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq       438813                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       347856                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       497865                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           64                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          109                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq      1218452                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp      1195725                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      4916774                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4752404                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq       832834                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateResp       781464                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     14836060                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     18594952                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       327877                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       607160                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total         34366049                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    629486804                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    699379029                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1242688                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      2226528                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total        1332335049                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    6259200                       # Total snoops (count)
-system.cpu0.toL2Bus.snoopTraffic            105003768                       # Total snoop traffic (bytes)
-system.cpu0.toL2Bus.snoop_fanout::samples     17822799                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       0.114255                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.318177                       # Request fanout histogram
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 88010.665008                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 84550.596270                       # average overall mshr uncacheable latency
+system.cpu0.toL2Bus.snoop_filter.tot_requests     22270826                       # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests     11431607                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         1159                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops       634641                       # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       634635                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops            6                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.cpu0.toL2Bus.trans_dist::ReadReq        532548                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp      9516927                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        22389                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        22388                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty      5262772                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean      7044356                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict      1133181                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       892107                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq       438346                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       371201                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       524392                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           61                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          102                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq      1190804                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp      1167926                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      5174652                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4606140                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq       845268                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateResp       799396                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     15609689                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     18074319                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       333482                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       538074                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total         34555564                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    662494868                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    674962485                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1270200                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1955080                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total        1340682633                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    5171785                       # Total snoops (count)
+system.cpu0.toL2Bus.snoopTraffic            107950516                       # Total snoop traffic (bytes)
+system.cpu0.toL2Bus.snoop_fanout::samples     16772894                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       0.051983                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.221994                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0          15786774     88.58%     88.58% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1           2035705     11.42%    100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2               320      0.00%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0          15900995     94.80%     94.80% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1            871893      5.20%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2                 6      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total      17822799                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy   21920125505                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total      16772894                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy   22046960997                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    184217084                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    203834159                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   7418286000                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   7805103000                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   8250668056                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   7957435977                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy    172541000                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy    174707000                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy    328844000                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy    293689000                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1430,69 +1429,75 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.cpu1.dtb.walker.walks                   102344                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong               102344                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        10188                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        77277                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore           10                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples       102334                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean     0.244298                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev    78.150189                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-2047       102333    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.walker.walks                   113512                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               113512                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        10824                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        86665                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore           27                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples       113485                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean     0.290787                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev    77.918264                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-2047       113483    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::6144-8191            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::24576-26623            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total       102334                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples        87475                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 22637.736496                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 21131.866681                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 13933.012219                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535        86378     98.75%     98.75% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071          960      1.10%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607           39      0.04%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143           45      0.05%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679           38      0.04%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215           10      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total        87475                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples  -5328755248                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.736470                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.440547                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0    -1404285148     26.35%     26.35% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1    -3924470100     73.65%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total  -5328755248                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        77278     88.35%     88.35% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M        10188     11.65%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total        87466                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       102344                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkWaitTime::total       113485                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples        97516                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 23769.576275                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 22071.904189                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 14608.572728                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-32767        88342     90.59%     90.59% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-65535         8042      8.25%     98.84% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-98303          147      0.15%     98.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::98304-131071          810      0.83%     99.82% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-163839           21      0.02%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::163840-196607           18      0.02%     99.86% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-229375           45      0.05%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::229376-262143           20      0.02%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-294911           17      0.02%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::294912-327679           36      0.04%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-360447            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::360448-393215            4      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-425983            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::425984-458751            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total        97516                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples     14762172                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean   194.841712                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0    -2861524688 -19384.17% -19384.17% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1     2876286860  19484.17%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total     14762172                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        86666     88.90%     88.90% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M        10824     11.10%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total        97490                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       113512                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       102344                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        87466                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       113512                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        97490                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        87466                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total       189810                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        97490                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total       211002                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    79660508                       # DTB read hits
-system.cpu1.dtb.read_misses                     74735                       # DTB read misses
-system.cpu1.dtb.write_hits                   72705787                       # DTB write hits
-system.cpu1.dtb.write_misses                    27609                       # DTB write misses
+system.cpu1.dtb.read_hits                    83873503                       # DTB read hits
+system.cpu1.dtb.read_misses                     85876                       # DTB read misses
+system.cpu1.dtb.write_hits                   75393075                       # DTB write hits
+system.cpu1.dtb.write_misses                    27636                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              41066                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                   1040                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   36374                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid              41711                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                   1058                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   39012                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  4588                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                  3907                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    10004                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                79735243                       # DTB read accesses
-system.cpu1.dtb.write_accesses               72733396                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    10199                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                83959379                       # DTB read accesses
+system.cpu1.dtb.write_accesses               75420711                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        152366295                       # DTB hits
-system.cpu1.dtb.misses                         102344                       # DTB misses
-system.cpu1.dtb.accesses                    152468639                       # DTB accesses
-system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.hits                        159266578                       # DTB hits
+system.cpu1.dtb.misses                         113512                       # DTB misses
+system.cpu1.dtb.accesses                    159380090                       # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1522,897 +1527,889 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.cpu1.itb.walker.walks                    58593                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong                58593                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2          620                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        52801                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples        58593                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0          58593    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        58593                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        53421                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 25912.740308                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 23776.245370                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 18077.529945                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-32767        47948     89.75%     89.75% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-65535         4330      8.11%     97.86% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-98303           49      0.09%     97.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::98304-131071          923      1.73%     99.68% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-163839           30      0.06%     99.74% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::163840-196607           25      0.05%     99.78% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-229375           42      0.08%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::229376-262143           13      0.02%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-294911           27      0.05%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::294912-327679           20      0.04%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-360447            7      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::360448-393215            3      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-425983            1      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::425984-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        53421                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples  -1503171148                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0    -1503171148    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total  -1503171148                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        52801     98.84%     98.84% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M          620      1.16%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        53421                       # Table walker page sizes translated
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.cpu1.itb.walker.walks                    59776                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                59776                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2          674                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        53293                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples        59776                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0          59776    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        59776                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        53967                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 25622.306224                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 23504.254601                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 18586.945639                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535        52820     97.87%     97.87% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071          977      1.81%     99.68% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607           34      0.06%     99.75% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143           58      0.11%     99.86% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679           61      0.11%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215           10      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        53967                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples  -1314622148                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0    -1314622148    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total  -1314622148                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K        53293     98.75%     98.75% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M          674      1.25%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        53967                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        58593                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total        58593                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        59776                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        59776                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        53421                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        53421                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       112014                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   421982441                       # ITB inst hits
-system.cpu1.itb.inst_misses                     58593                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        53967                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        53967                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       113743                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   442849873                       # ITB inst hits
+system.cpu1.itb.inst_misses                     59776                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              41066                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                   1040                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   25297                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              41711                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                   1058                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   27503                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               422041034                       # ITB inst accesses
-system.cpu1.itb.hits                        421982441                       # DTB hits
-system.cpu1.itb.misses                          58593                       # DTB misses
-system.cpu1.itb.accesses                    422041034                       # DTB accesses
-system.cpu1.numPwrStateTransitions               9904                       # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples         4952                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean    9471329494.171041                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev   145765994017.543427                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::underflows         3395     68.56%     68.56% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1000-5e+10         1531     30.92%     99.47% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::5e+10-1e+11            1      0.02%     99.50% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11            2      0.04%     99.54% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11            3      0.06%     99.60% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11            2      0.04%     99.64% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11            1      0.02%     99.66% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11            1      0.02%     99.68% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11            1      0.02%     99.70% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12            1      0.02%     99.72% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::overflows           14      0.28%    100.00% # Distribution of time spent in the clock gated state
+system.cpu1.itb.inst_accesses               442909649                       # ITB inst accesses
+system.cpu1.itb.hits                        442849873                       # DTB hits
+system.cpu1.itb.misses                          59776                       # DTB misses
+system.cpu1.itb.accesses                    442909649                       # DTB accesses
+system.cpu1.numPwrStateTransitions              28574                       # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples        14287                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean    3279405691.982362                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev   123453533761.994095                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows         4140     28.98%     28.98% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10        10126     70.88%     99.85% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5e+10-1e+11            7      0.05%     99.90% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11            1      0.01%     99.91% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11            1      0.01%     99.92% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11            1      0.01%     99.92% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11            1      0.01%     99.93% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::overflows           10      0.07%    100.00% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::max_value 7470352176392                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total           4952                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON   501551261365                       # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 46902023655135                       # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles                     94807149833                       # number of cpu cycles simulated
+system.cpu1.pwrStateClkGateDist::max_value 11813601970000                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total          14287                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON   521446289148                       # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 46852869121352                       # Cumulative time (in ticks) in various power states
+system.cpu1.numCycles                     94748630821                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    4952                       # number of quiesce instructions executed
-system.cpu1.committedInsts                  421703858                       # Number of instructions committed
-system.cpu1.committedOps                    497054350                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses            456781482                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                475663                       # Number of float alu accesses
-system.cpu1.num_func_calls                   25188507                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts     64210733                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                   456781482                       # number of integer instructions
-system.cpu1.num_fp_insts                       475663                       # number of float instructions
-system.cpu1.num_int_register_reads          664763727                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes         362355133                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads              757340                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes             426036                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads           109701618                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes          109432507                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                    152358964                       # number of memory refs
-system.cpu1.num_load_insts                   79658830                       # Number of load instructions
-system.cpu1.num_store_insts                  72700134                       # Number of store instructions
-system.cpu1.num_idle_cycles              93804047310.268021                       # Number of idle cycles
-system.cpu1.num_busy_cycles              1003102522.731979                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.010580                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.989420                       # Percentage of idle cycles
-system.cpu1.Branches                         94064671                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                343802607     69.13%     69.13% # Class of executed instruction
-system.cpu1.op_class::IntMult                 1044362      0.21%     69.34% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    57840      0.01%     69.35% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc             69226      0.01%     69.36% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.36% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.36% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.36% # Class of executed instruction
-system.cpu1.op_class::MemRead                79658830     16.02%     85.38% # Class of executed instruction
-system.cpu1.op_class::MemWrite               72700134     14.62%    100.00% # Class of executed instruction
+system.cpu1.kern.inst.quiesce                   14287                       # number of quiesce instructions executed
+system.cpu1.committedInsts                  442543215                       # Number of instructions committed
+system.cpu1.committedOps                    520378160                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses            478315040                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                404780                       # Number of float alu accesses
+system.cpu1.num_func_calls                   26483096                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts     67217461                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                   478315040                       # number of integer instructions
+system.cpu1.num_fp_insts                       404780                       # number of float instructions
+system.cpu1.num_int_register_reads          696723237                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes         379679857                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads              664337                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes             317564                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads           114632172                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes          114267384                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                    159256484                       # number of memory refs
+system.cpu1.num_load_insts                   83870110                       # Number of load instructions
+system.cpu1.num_store_insts                  75386374                       # Number of store instructions
+system.cpu1.num_idle_cycles              93705738242.702026                       # Number of idle cycles
+system.cpu1.num_busy_cycles              1042892578.297978                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.011007                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.988993                       # Percentage of idle cycles
+system.cpu1.Branches                         98643380                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                360264761     69.19%     69.19% # Class of executed instruction
+system.cpu1.op_class::IntMult                 1062033      0.20%     69.39% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    60918      0.01%     69.41% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     69.41% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     69.41% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     69.41% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     69.41% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     69.41% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     69.41% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     69.41% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.41% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     69.41% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     69.41% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     69.41% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     69.41% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     69.41% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.41% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     69.41% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.41% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     69.41% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     69.41% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.41% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     69.41% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     69.41% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.41% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc             40731      0.01%     69.41% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.41% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.41% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.41% # Class of executed instruction
+system.cpu1.op_class::MemRead                83870110     16.11%     85.52% # Class of executed instruction
+system.cpu1.op_class::MemWrite               75386374     14.48%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                 497333042                       # Class of executed instruction
-system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.tags.replacements          5003393                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          453.941998                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs          147178696                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs          5003905                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            29.412768                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     8378733231000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   453.941998                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.886605                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.886605                       # Average percentage of cache occupancy
+system.cpu1.op_class::total                 520684927                       # Class of executed instruction
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.tags.replacements          5203972                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          424.411021                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs          153866536                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs          5204484                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            29.564225                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     8378899013000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   424.411021                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.828928                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.828928                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0           67                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          398                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           47                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0          153                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          310                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           48                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses        309758535                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses       309758535                       # Number of data accesses
-system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.ReadReq_hits::cpu1.data     74209320                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       74209320                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data     68941180                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total      68941180                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data       175621                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total       175621                       # number of SoftPFReq hits
-system.cpu1.dcache.WriteLineReq_hits::cpu1.data       163479                       # number of WriteLineReq hits
-system.cpu1.dcache.WriteLineReq_hits::total       163479                       # number of WriteLineReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1660182                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total      1660182                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1630108                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total      1630108                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data    143313979                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total       143313979                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data    143489600                       # number of overall hits
-system.cpu1.dcache.overall_hits::total      143489600                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data      2836392                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total      2836392                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data      1297238                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      1297238                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data       605603                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total       605603                       # number of SoftPFReq misses
-system.cpu1.dcache.WriteLineReq_misses::cpu1.data       460373                       # number of WriteLineReq misses
-system.cpu1.dcache.WriteLineReq_misses::total       460373                       # number of WriteLineReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       162387                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total       162387                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data       191354                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total       191354                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data      4594003                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total       4594003                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data      5199606                       # number of overall misses
-system.cpu1.dcache.overall_misses::total      5199606                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  40714366500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total  40714366500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  24361465000                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  24361465000                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  11037691000                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::total  11037691000                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2429522000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total   2429522000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4779056000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total   4779056000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      2991500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      2991500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  76113522500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  76113522500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  76113522500                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  76113522500                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data     77045712                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     77045712                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data     70238418                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total     70238418                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       781224                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total       781224                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       623852                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::total       623852                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1822569                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total      1822569                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1821462                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total      1821462                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data    147907982                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total    147907982                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data    148689206                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total    148689206                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.036814                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.036814                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.018469                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.018469                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.775198                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.775198                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.737952                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::total     0.737952                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.089098                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.089098                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.105055                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.105055                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.031060                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.031060                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.034970                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.034970                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14354.280544                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14354.280544                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18779.487650                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 18779.487650                       # average WriteReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23975.539400                       # average WriteLineReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 23975.539400                       # average WriteLineReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14961.308479                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14961.308479                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24974.946957                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24974.946957                       # average StoreCondReq miss latency
+system.cpu1.dcache.tags.tag_accesses        323742508                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses       323742508                       # Number of data accesses
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.ReadReq_hits::cpu1.data     78110378                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       78110378                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data     71558729                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total      71558729                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data       177304                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total       177304                       # number of SoftPFReq hits
+system.cpu1.dcache.WriteLineReq_hits::cpu1.data        95899                       # number of WriteLineReq hits
+system.cpu1.dcache.WriteLineReq_hits::total        95899                       # number of WriteLineReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1773602                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total      1773602                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1738086                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total      1738086                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data    149765006                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total       149765006                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data    149942310                       # number of overall hits
+system.cpu1.dcache.overall_hits::total      149942310                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data      2993339                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total      2993339                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      1322577                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      1322577                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data       630415                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total       630415                       # number of SoftPFReq misses
+system.cpu1.dcache.WriteLineReq_misses::cpu1.data       446111                       # number of WriteLineReq misses
+system.cpu1.dcache.WriteLineReq_misses::total       446111                       # number of WriteLineReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       170906                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total       170906                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data       205163                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total       205163                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data      4762027                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total       4762027                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data      5392442                       # number of overall misses
+system.cpu1.dcache.overall_misses::total      5392442                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  43487315000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total  43487315000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  24009342500                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  24009342500                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  10785817000                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::total  10785817000                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2544188500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total   2544188500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4864957000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total   4864957000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      2180500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      2180500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  78282474500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  78282474500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  78282474500                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  78282474500                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data     81103717                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total     81103717                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data     72881306                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total     72881306                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       807719                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total       807719                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       542010                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::total       542010                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1944508                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total      1944508                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1943249                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total      1943249                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data    154527033                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total    154527033                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data    155334752                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total    155334752                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.036908                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.036908                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.018147                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.018147                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.780488                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.780488                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.823068                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::total     0.823068                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.087892                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.087892                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.105577                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.105577                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.030817                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.030817                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.034715                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.034715                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14528.028733                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14528.028733                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18153.455338                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 18153.455338                       # average WriteReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24177.428936                       # average WriteLineReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24177.428936                       # average WriteLineReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14886.478532                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14886.478532                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23712.643118                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23712.643118                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16568.017587                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 16568.017587                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14638.325000                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 14638.325000                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16438.897658                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 16438.897658                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14517.073063                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 14517.073063                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.writebacks::writebacks      5003393                       # number of writebacks
-system.cpu1.dcache.writebacks::total          5003393                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        17753                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total        17753                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data          420                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total          420                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        44380                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        44380                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data        18173                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total        18173                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data        18173                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total        18173                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2818639                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total      2818639                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1296818                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total      1296818                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       605603                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total       605603                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       460373                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::total       460373                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       118007                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total       118007                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       191354                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total       191354                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data      4575830                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total      4575830                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data      5181433                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total      5181433                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        11021                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total        11021                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        11924                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total        11924                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        22945                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total        22945                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  36912397500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total  36912397500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  23044975500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total  23044975500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  12992134000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  12992134000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  10577318000                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  10577318000                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1572635000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1572635000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   4587759000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   4587759000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      2934500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      2934500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  70534691000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total  70534691000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  83526825000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total  83526825000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   1888408000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   1888408000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1888408000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1888408000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036584                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036584                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018463                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018463                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.775198                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.775198                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.737952                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.737952                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.064748                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.064748                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.105055                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.105055                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.030937                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.030937                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.034847                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.034847                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13095.823020                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13095.823020                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17770.400704                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17770.400704                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21453.219353                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21453.219353                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22975.539400                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 22975.539400                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13326.624692                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13326.624692                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23975.244834                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23975.244834                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks      5203972                       # number of writebacks
+system.cpu1.dcache.writebacks::total          5203972                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        14156                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total        14156                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data          216                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total          216                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        44175                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        44175                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data        14372                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total        14372                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data        14372                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total        14372                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2979183                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total      2979183                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1322361                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total      1322361                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       630415                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total       630415                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       446111                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::total       446111                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       126731                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total       126731                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       205163                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total       205163                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data      4747655                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total      4747655                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data      5378070                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total      5378070                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        17577                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total        17577                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        16125                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total        16125                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        33702                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total        33702                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  39805955500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total  39805955500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  22681350000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total  22681350000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  12330973000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  12330973000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  10339706000                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  10339706000                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1686365000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1686365000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   4659843000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   4659843000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      2131500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      2131500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  72827011500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total  72827011500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  85157984500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total  85157984500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2978895500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2978895500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   2978895500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   2978895500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036733                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036733                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018144                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018144                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.780488                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.780488                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.823068                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.823068                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.065174                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.065174                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.105577                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.105577                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.030724                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.030724                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.034622                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.034622                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13361.366354                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13361.366354                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17152.161929                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17152.161929                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19560.088196                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19560.088196                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23177.428936                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23177.428936                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13306.649517                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13306.649517                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22712.881952                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22712.881952                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15414.622265                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15414.622265                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16120.410126                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16120.410126                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171346.338808                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171346.338808                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 82301.503596                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 82301.503596                       # average overall mshr uncacheable latency
-system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.cpu1.icache.tags.replacements          5018955                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          496.221127                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs          416962969                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs          5019467                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            83.069172                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     8378705112000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   496.221127                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.969182                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.969182                       # Average percentage of cache occupancy
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15339.575327                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15339.575327                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15834.301989                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15834.301989                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169476.901633                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 169476.901633                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 88389.279568                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 88389.279568                       # average overall mshr uncacheable latency
+system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.cpu1.icache.tags.replacements          4895837                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          496.209399                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs          437953524                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs          4896349                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            89.444916                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     8378871626000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   496.209399                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.969159                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.969159                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          317                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          131                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          149                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          324                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3           12                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses        848984354                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses       848984354                       # Number of data accesses
-system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.cpu1.icache.ReadReq_hits::cpu1.inst    416962969                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total      416962969                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst    416962969                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total       416962969                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst    416962969                       # number of overall hits
-system.cpu1.icache.overall_hits::total      416962969                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst      5019472                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total      5019472                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst      5019472                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total       5019472                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst      5019472                       # number of overall misses
-system.cpu1.icache.overall_misses::total      5019472                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  53186343000                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total  53186343000                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst  53186343000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total  53186343000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst  53186343000                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total  53186343000                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst    421982441                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total    421982441                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst    421982441                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total    421982441                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst    421982441                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total    421982441                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.011895                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.011895                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.011895                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.011895                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.011895                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.011895                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10596.003524                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 10596.003524                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10596.003524                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 10596.003524                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10596.003524                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 10596.003524                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses        890596095                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses       890596095                       # Number of data accesses
+system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.cpu1.icache.ReadReq_hits::cpu1.inst    437953524                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total      437953524                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst    437953524                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total       437953524                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst    437953524                       # number of overall hits
+system.cpu1.icache.overall_hits::total      437953524                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst      4896349                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total      4896349                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst      4896349                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total       4896349                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst      4896349                       # number of overall misses
+system.cpu1.icache.overall_misses::total      4896349                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  51444170000                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total  51444170000                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst  51444170000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total  51444170000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst  51444170000                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total  51444170000                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst    442849873                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total    442849873                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst    442849873                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total    442849873                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst    442849873                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total    442849873                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.011056                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.011056                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.011056                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.011056                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.011056                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.011056                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10506.638722                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 10506.638722                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10506.638722                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 10506.638722                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10506.638722                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 10506.638722                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.writebacks::writebacks      5018955                       # number of writebacks
-system.cpu1.icache.writebacks::total          5018955                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      5019472                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total      5019472                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst      5019472                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total      5019472                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst      5019472                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total      5019472                       # number of overall MSHR misses
+system.cpu1.icache.writebacks::writebacks      4895837                       # number of writebacks
+system.cpu1.icache.writebacks::total          4895837                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      4896349                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total      4896349                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst      4896349                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total      4896349                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst      4896349                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total      4896349                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total          110                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total          110                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  50676607000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total  50676607000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  50676607000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total  50676607000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  50676607000                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total  50676607000                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     10226000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     10226000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     10226000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total     10226000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011895                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.011895                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.011895                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.011895                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.011895                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.011895                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10096.003524                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10096.003524                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10096.003524                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 10096.003524                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10096.003524                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 10096.003524                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92963.636364                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92963.636364                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92963.636364                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92963.636364                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.prefetcher.num_hwpf_issued      6881080                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified      6881096                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit           14                       # number of redundant prefetches already in prefetch queue
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  48995995500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total  48995995500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  48995995500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total  48995995500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  48995995500                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total  48995995500                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     10402000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     10402000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     10402000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total     10402000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011056                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.011056                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.011056                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.011056                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.011056                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.011056                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10006.638722                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10006.638722                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10006.638722                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 10006.638722                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10006.638722                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 10006.638722                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 94563.636364                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 94563.636364                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 94563.636364                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 94563.636364                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.cpu1.l2cache.prefetcher.num_hwpf_issued      7252070                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified      7252079                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit            8                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage       855832                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.tags.replacements         1952199                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       13310.052713                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs          14647404                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs         1968271                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs            7.441762                       # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle    9691338413500                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 12374.908537                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    46.710351                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    42.105943                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   846.327882                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.755304                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.002851                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.002570                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.051656                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.812381                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1315                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           51                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14706                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           28                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          206                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          560                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          521                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           20                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           22                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            9                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           79                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          976                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         4506                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         5198                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3947                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.080261                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.003113                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.897583                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses       339868675                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses      339868675                       # Number of data accesses
-system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       236019                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       150274                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total        386293                       # number of ReadReq hits
-system.cpu1.l2cache.WritebackDirty_hits::writebacks      3171050                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackDirty_hits::total      3171050                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackClean_hits::writebacks      6850339                       # number of WritebackClean hits
-system.cpu1.l2cache.WritebackClean_hits::total      6850339                       # number of WritebackClean hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data          404                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total          404                       # number of UpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data       839001                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total       839001                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      4555671                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total      4555671                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2665864                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total      2665864                       # number of ReadSharedReq hits
-system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       201941                       # number of InvalidateReq hits
-system.cpu1.l2cache.InvalidateReq_hits::total       201941                       # number of InvalidateReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       236019                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker       150274                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst      4555671                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data      3504865                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total        8446829                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       236019                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker       150274                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst      4555671                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data      3504865                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total       8446829                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        10494                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         9148                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total        19642                       # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       207236                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total       207236                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       191347                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total       191347                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            7                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::total            7                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data       252464                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total       252464                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       463801                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total       463801                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       876385                       # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total       876385                       # number of ReadSharedReq misses
-system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       256334                       # number of InvalidateReq misses
-system.cpu1.l2cache.InvalidateReq_misses::total       256334                       # number of InvalidateReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        10494                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker         9148                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst       463801                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data      1128849                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total      1612292                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        10494                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker         9148                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst       463801                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data      1128849                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total      1612292                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    383427500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    341472000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total    724899500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   1893664000                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total   1893664000                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   1540982500                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   1540982500                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      2848499                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      2848499                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  10062122499                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total  10062122499                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  15777836000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::total  15777836000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  28794953500                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total  28794953500                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data    441282000                       # number of InvalidateReq miss cycles
-system.cpu1.l2cache.InvalidateReq_miss_latency::total    441282000                       # number of InvalidateReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    383427500                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    341472000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst  15777836000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data  38857075999                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total  55359811499                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    383427500                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    341472000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst  15777836000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data  38857075999                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total  55359811499                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       246513                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       159422                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total       405935                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::writebacks      3171050                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::total      3171050                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::writebacks      6850339                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::total      6850339                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       207640                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total       207640                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       191347                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total       191347                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            7                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            7                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1091465                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total      1091465                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      5019472                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total      5019472                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3542249                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total      3542249                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       458275                       # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.InvalidateReq_accesses::total       458275                       # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       246513                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       159422                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst      5019472                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data      4633714                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total     10059121                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       246513                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       159422                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst      5019472                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data      4633714                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total     10059121                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.042570                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.057382                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.048387                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.998054                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.998054                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.prefetcher.pfSpanPage       909185                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.cpu1.l2cache.tags.replacements         1859788                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       13078.836793                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs           8983696                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs         1875537                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs            4.789933                       # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
+system.cpu1.l2cache.tags.occ_blocks::writebacks 12823.617935                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    17.493162                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    11.479573                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   226.246124                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.782692                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.001068                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000701                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.013809                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.798269                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022          286                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           54                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        15409                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           12                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          107                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          144                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4           23                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           13                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           39                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            2                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          175                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          868                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         6435                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         7258                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4          673                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.017456                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.003296                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.940491                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses       348956442                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses      348956442                       # Number of data accesses
+system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       258658                       # number of ReadReq hits
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+system.cpu1.l2cache.ReadReq_hits::total        410205                       # number of ReadReq hits
+system.cpu1.l2cache.WritebackDirty_hits::writebacks      3266667                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackDirty_hits::total      3266667                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackClean_hits::writebacks      6832390                       # number of WritebackClean hits
+system.cpu1.l2cache.WritebackClean_hits::total      6832390                       # number of WritebackClean hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data       881671                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total       881671                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      4452144                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::total      4452144                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2841120                       # number of ReadSharedReq hits
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+system.cpu1.l2cache.InvalidateReq_hits::total       192152                       # number of InvalidateReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       258658                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker       151547                       # number of demand (read+write) hits
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+system.cpu1.l2cache.overall_hits::cpu1.data      3722791                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total       8585140                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        18381                       # number of ReadReq misses
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+system.cpu1.l2cache.UpgradeReq_misses::total       207506                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       205160                       # number of SCUpgradeReq misses
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+system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            3                       # number of SCUpgradeFailReq misses
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+system.cpu1.l2cache.ReadExReq_misses::cpu1.data       235234                       # number of ReadExReq misses
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+system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       444205                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::total       444205                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       895209                       # number of ReadSharedReq misses
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+system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       252043                       # number of InvalidateReq misses
+system.cpu1.l2cache.InvalidateReq_misses::total       252043                       # number of InvalidateReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        18381                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker         9249                       # number of demand (read+write) misses
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+system.cpu1.l2cache.demand_misses::total      1602278                       # number of demand (read+write) misses
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+system.cpu1.l2cache.overall_misses::cpu1.data      1130443                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total      1602278                       # number of overall misses
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    560546000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    349476500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::total    910022500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    940760500                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total    940760500                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    308144500                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    308144500                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      2058000                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      2058000                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   9879714999                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::total   9879714999                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  14896666000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::total  14896666000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  29710253000                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::total  29710253000                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data    322403500                       # number of InvalidateReq miss cycles
+system.cpu1.l2cache.InvalidateReq_miss_latency::total    322403500                       # number of InvalidateReq miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    560546000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    349476500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.inst  14896666000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.data  39589967999                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::total  55396656499                       # number of demand (read+write) miss cycles
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+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    349476500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst  14896666000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.data  39589967999                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total  55396656499                       # number of overall miss cycles
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+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       160796                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total       437835                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::writebacks      3266667                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::total      3266667                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::writebacks      6832390                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::total      6832390                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       207506                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total       207506                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       205160                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total       205160                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            3                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            3                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1116905                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total      1116905                       # number of ReadExReq accesses(hits+misses)
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+system.cpu1.l2cache.ReadCleanReq_accesses::total      4896349                       # number of ReadCleanReq accesses(hits+misses)
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+system.cpu1.l2cache.InvalidateReq_accesses::total       444195                       # number of InvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       277039                       # number of demand (read+write) accesses
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+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       277039                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       160796                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst      4896349                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data      4853234                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total     10187418                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.066348                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.057520                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.063106                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.231307                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.231307                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.092400                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.092400                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.247409                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.247409                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.559345                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.559345                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.042570                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.057382                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.092400                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.243616                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.160282                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.042570                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.057382                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.092400                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.243616                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.160282                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 36537.783495                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 37327.503279                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 36905.584971                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  9137.717385                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  9137.717385                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  8053.340267                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  8053.340267                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 406928.428571                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 406928.428571                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39855.672488                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39855.672488                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 34018.546747                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 34018.546747                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 32856.511122                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 32856.511122                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data  1721.511778                       # average InvalidateReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total  1721.511778                       # average InvalidateReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 36537.783495                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 37327.503279                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34018.546747                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34421.854472                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 34336.095136                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 36537.783495                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 37327.503279                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34018.546747                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34421.854472                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 34336.095136                       # average overall miss latency
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.210612                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.210612                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.090722                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.090722                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.239596                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.239596                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.567415                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.567415                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.066348                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.057520                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.090722                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.232926                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.157280                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.066348                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.057520                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.090722                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.232926                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.157280                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 30495.946902                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 37785.328144                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 32936.029678                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  4533.654449                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  4533.654449                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  1501.971632                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  1501.971632                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data       686000                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total       686000                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 41999.519623                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 41999.519623                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 33535.565786                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 33535.565786                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 33188.063346                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 33188.063346                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data  1279.160699                       # average InvalidateReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total  1279.160699                       # average InvalidateReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 30495.946902                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 37785.328144                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 33535.565786                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 35021.640188                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 34573.686026                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 30495.946902                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 37785.328144                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 33535.565786                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 35021.640188                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 34573.686026                       # average overall miss latency
 system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.l2cache.unused_prefetches           40910                       # number of HardPF blocks evicted w/o reference
-system.cpu1.l2cache.writebacks::writebacks      1077285                       # number of writebacks
-system.cpu1.l2cache.writebacks::total         1077285                       # number of writebacks
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         4355                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total         4355                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          371                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          371                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data         4726                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total         4726                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data         4726                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total         4726                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        10494                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         9148                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total        19642                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       670250                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total       670250                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       207236                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total       207236                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       191347                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       191347                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            7                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            7                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       248109                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total       248109                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       463801                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       463801                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       876014                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       876014                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       256334                       # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::total       256334                       # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        10494                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         9148                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       463801                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1124123                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total      1607566                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        10494                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         9148                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       463801                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1124123                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       670250                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total      2277816                       # number of overall MSHR misses
+system.cpu1.l2cache.unused_prefetches           39888                       # number of HardPF blocks evicted w/o reference
+system.cpu1.l2cache.writebacks::writebacks      1080406                       # number of writebacks
+system.cpu1.l2cache.writebacks::total         1080406                       # number of writebacks
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         5355                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total         5355                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          314                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          314                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data            2                       # number of InvalidateReq MSHR hits
+system.cpu1.l2cache.InvalidateReq_mshr_hits::total            2                       # number of InvalidateReq MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.data         5669                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total         5669                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.data         5669                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::total         5669                       # number of overall MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        18381                       # number of ReadReq MSHR misses
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+system.cpu1.l2cache.ReadReq_mshr_misses::total        27630                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       700284                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total       700284                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       207506                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total       207506                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       205160                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       205160                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            3                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            3                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       229879                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::total       229879                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       444205                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       444205                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       894895                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       894895                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       252041                       # number of InvalidateReq MSHR misses
+system.cpu1.l2cache.InvalidateReq_mshr_misses::total       252041                       # number of InvalidateReq MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        18381                       # number of demand (read+write) MSHR misses
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+system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1124774                       # number of demand (read+write) MSHR misses
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+system.cpu1.l2cache.overall_mshr_misses::total      2296893                       # number of overall MSHR misses
 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        11021                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        11131                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        11924                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        11924                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        17577                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        17687                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        16125                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        16125                       # number of WriteReq MSHR uncacheable
 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        22945                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        23055                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    320463500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    286584000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    607047500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  26432385766                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  26432385766                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   4355093500                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   4355093500                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   3151504000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   3151504000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      2506499                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2506499                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   8136910999                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   8136910999                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  12995030000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  12995030000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  23494652500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  23494652500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data   6984949000                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total   6984949000                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    320463500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    286584000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  12995030000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  31631563499                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total  45233640999                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    320463500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    286584000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  12995030000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  31631563499                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  26432385766                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total  71666026765                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9401000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   1799706000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   1809107000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      9401000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   1799706000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1809107000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.042570                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.057382                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.048387                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        33702                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        33812                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    450260000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    293982500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    744242500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  29274832519                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  29274832519                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   3856981999                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   3856981999                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   3119783996                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   3119783996                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1764000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1764000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   7964098999                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   7964098999                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  12231436000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  12231436000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  24307582500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  24307582500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data   6863337500                       # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total   6863337500                       # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    450260000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    293982500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  12231436000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  32271681499                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total  45247359999                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    450260000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    293982500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  12231436000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  32271681499                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  29274832519                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total  74522192518                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9577000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2837977500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2847554500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      9577000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   2837977500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   2847554500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.066348                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.057520                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.063106                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.998054                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.998054                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.227317                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.227317                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.092400                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.092400                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.247304                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.247304                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.559345                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.559345                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.042570                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.057382                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.092400                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.242597                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.159812                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.042570                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.057382                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.092400                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.242597                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.205818                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.205818                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.090722                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.090722                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.239512                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.239512                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.567411                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.567411                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.066348                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.057520                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.090722                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.231758                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.156724                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.066348                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.057520                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.090722                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.231758                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.226443                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 30537.783495                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31327.503279                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30905.584971                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39436.606887                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39436.606887                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21015.139744                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21015.139744                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16470.098826                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16470.098826                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 358071.285714                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 358071.285714                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32795.710752                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32795.710752                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 28018.546747                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28018.546747                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 26819.950937                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26819.950937                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 27249.405073                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 27249.405073                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 30537.783495                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31327.503279                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28018.546747                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28138.881154                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28137.968207                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 30537.783495                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31327.503279                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28018.546747                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28138.881154                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39436.606887                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31462.605744                       # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 85463.636364                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163297.885854                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162528.703621                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 85463.636364                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 78435.650469                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 78469.182390                       # average overall mshr uncacheable latency
-system.cpu1.toL2Bus.snoop_filter.tot_requests     20762161                       # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests     10650842                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests          958                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops      1727817                       # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops      1727605                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops          212                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.cpu1.toL2Bus.trans_dist::ReadReq        482395                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp      9130479                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq        11924                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp        11924                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty      4254476                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean      6851297                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict      2274133                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq       818827                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq       384823                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       346834                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp       460171                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           59                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          109                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq      1120311                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp      1099104                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq      5019472                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4398430                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq       506547                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateResp       458275                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     15058119                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16186537                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       334443                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       542756                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total         32121855                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    642459768                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    622853650                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1275376                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1972104                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total        1268560898                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                    5663025                       # Total snoops (count)
-system.cpu1.toL2Bus.snoopTraffic             75880456                       # Total snoop traffic (bytes)
-system.cpu1.toL2Bus.snoop_fanout::samples     16447181                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       0.119069                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.323910                       # Request fanout histogram
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.225464                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24495.946902                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31785.328144                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 26936.029678                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41804.228740                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41804.228740                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18587.327591                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18587.327591                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15206.589959                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15206.589959                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       588000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       588000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34644.743535                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34644.743535                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 27535.565786                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27535.565786                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 27162.496717                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27162.496717                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 27231.035824                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 27231.035824                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24495.946902                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31785.328144                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27535.565786                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28691.702955                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28339.662371                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24495.946902                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31785.328144                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27535.565786                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28691.702955                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41804.228740                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32444.781937                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87063.636364                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161459.720089                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 160997.031718                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87063.636364                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 84207.984689                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 84217.274932                       # average overall mshr uncacheable latency
+system.cpu1.toL2Bus.snoop_filter.tot_requests     20954555                       # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests     10760929                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests          751                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops       564007                       # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       564007                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.cpu1.toL2Bus.trans_dist::ReadReq        525208                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp      9244496                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq        16125                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp        16125                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty      4351848                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean      6833141                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict      1083593                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq       850253                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq       408331                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       372440                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp       477174                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           56                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          102                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq      1146242                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp      1123232                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq      4896349                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4644090                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq       493781                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateResp       444195                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     14688755                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16849115                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       339302                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       606054                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total         32483226                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    626700344                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    649733422                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1286368                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      2216312                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total        1279936446                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                    4601099                       # Total snoops (count)
+system.cpu1.toL2Bus.snoopTraffic             75959664                       # Total snoop traffic (bytes)
+system.cpu1.toL2Bus.snoop_fanout::samples     15521649                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       0.052382                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.222797                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0          14489040     88.09%     88.09% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1           1957929     11.90%    100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2               212      0.00%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0          14708591     94.76%     94.76% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1            813058      5.24%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2                 0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total      16447181                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy   20541870997                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::total      15521649                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy   20731667993                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy    171936035                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy    171895510                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy   7529318000                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy   7344633500                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy   7396555908                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy   7734220026                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy    175021499                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy    178506000                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy    296243499                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy    329015998                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq                40346                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40346                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136621                       # Transaction distribution
-system.iobus.trans_dist::WriteResp             136621                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47682                       # Packet count per connected master and slave (bytes)
+system.iobus.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.iobus.trans_dist::ReadReq                40399                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40399                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136980                       # Transaction distribution
+system.iobus.trans_dist::WriteResp             136980                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47798                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
@@ -2423,15 +2420,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29808                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       122616                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231238                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231238                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       122940                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231738                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231738                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353934                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47702                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  354758                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47818                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -2442,21 +2439,21 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17703                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       155723                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338968                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7338968                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       155955                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7355304                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7355304                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7496777                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             36887001                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7513345                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             37010502                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                12500                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                12000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               320000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               320500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                 8500                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                 9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy                 8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
@@ -2464,7 +2461,7 @@ system.iobus.reqLayer10.occupancy                8000                       # La
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy                9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer15.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
@@ -2472,75 +2469,75 @@ system.iobus.reqLayer16.occupancy               14000                       # La
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            26455501                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            26741000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            37419000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            37418500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           569241095                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           570750713                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            92726000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            92947000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147934000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           148178000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements               115616                       # number of replacements
-system.iocache.tags.tagsinuse               11.233110                       # Cycle average of tags in use
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.replacements               115853                       # number of replacements
+system.iocache.tags.tagsinuse               11.245503                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115632                       # Sample count of references to valid blocks.
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 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         9095552544000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     7.412176                       # Average occupied blocks per requestor
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 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
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 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1040928                       # Number of tag accesses
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-system.iocache.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
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+system.iocache.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
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 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
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-system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
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 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide       115619                       # number of demand (read+write) misses
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 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide       115619                       # number of overall misses
-system.iocache.overall_misses::total           115659                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5198000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1628324544                       # number of ReadReq miss cycles
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 system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  12891433551                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  12891433551                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5567000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide  14519758095                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  14525325095                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5567000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide  14519758095                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  14525325095                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  12911092626                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  12911092626                       # number of WriteLineReq miss cycles
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+system.iocache.demand_miss_latency::realview.ide  14544685713                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  14550332713                       # number of demand (read+write) miss cycles
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+system.iocache.overall_miss_latency::realview.ide  14544685713                       # number of overall miss cycles
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 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8891                       # number of ReadReq accesses(hits+misses)
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 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::realview.ide       106984                       # number of WriteLineReq accesses(hits+misses)
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 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide       115619                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total          115659                       # number of demand (read+write) accesses
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 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide       115619                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total         115659                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide       115869                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total         115909                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -2554,53 +2551,53 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 183143.014734                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 182966.234767                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 142648.648649                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 183859.660889                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 183688.756669                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120787.736592                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 120787.736592                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       139175                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 125582.802956                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 125587.503739                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       139175                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 125582.802956                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 125587.503739                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         31812                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120682.463041                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 120682.463041                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet       141175                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 125526.980582                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 125532.380687                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet       141175                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 125526.980582                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 125532.380687                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         31750                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3498                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3454                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.094340                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.192241                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks          106695                       # number of writebacks
-system.iocache.writebacks::total               106695                       # number of writebacks
+system.iocache.writebacks::writebacks          106953                       # number of writebacks
+system.iocache.writebacks::total               106953                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8891                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8928                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8885                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8922                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::realview.ide       106984                       # number of WriteLineReq MSHR misses
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 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide       115619                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total       115659                       # number of demand (read+write) MSHR misses
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 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide       115619                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total       115659                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3348000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1183774544                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1187122544                       # number of ReadReq MSHR miss cycles
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+system.iocache.overall_mshr_misses::total       115909                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3428000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1189343087                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1192771087                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7546042407                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   7546042407                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3567000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   8729816951                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   8733383951                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3567000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   8729816951                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   8733383951                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7553188799                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   7553188799                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3647000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   8742531886                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   8746178886                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3647000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   8742531886                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   8746178886                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -2614,659 +2611,662 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133143.014734                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 132966.234767                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 92648.648649                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133859.660889                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 133688.756669                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70703.493057                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70703.493057                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        89175                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 75505.037675                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 75509.765353                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        89175                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 75505.037675                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 75509.765353                       # average overall mshr miss latency
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements                  1334376                       # number of replacements
-system.l2c.tags.tagsinuse                63294.471519                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    5390543                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1393372                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     3.868703                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle               9808893500                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   22223.163606                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   261.500257                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   456.360455                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3501.846073                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data    10429.068271                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 16721.904383                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker    41.820782                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker    49.581814                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     3191.520948                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     3798.713740                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  2618.991189                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.339099                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.003990                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.006964                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.053434                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.159135                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.255156                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000638                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.000757                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.048699                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.057964                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.039963                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.965797                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        10362                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023          274                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        48360                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::1            8                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2          240                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3          245                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4         9869                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          274                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           12                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          123                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         1630                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5501                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        41094                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.158112                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.004181                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.737915                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 69824789                       # Number of tag accesses
-system.l2c.tags.data_accesses                69824789                       # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.l2c.WritebackDirty_hits::writebacks      2605015                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total         2605015                       # number of WritebackDirty hits
-system.l2c.UpgradeReq_hits::cpu0.data          157240                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data          131498                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total              288738                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data         36551                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data         35663                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total             72214                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            46670                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            57995                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               104665                       # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         4832                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker         3674                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst       408343                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       539971                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       281420                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         5997                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker         5496                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst       419901                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       530515                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       275271                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total          2475420                       # number of ReadSharedReq hits
-system.l2c.InvalidateReq_hits::cpu0.data       117433                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::cpu1.data       122622                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::total           240055                       # number of InvalidateReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          4832                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          3674                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              408343                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              586641                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher       281420                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          5997                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          5496                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              419901                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              588510                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher       275271                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2580085                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         4832                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         3674                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             408343                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             586641                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher       281420                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         5997                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         5496                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             419901                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             588510                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher       275271                       # number of overall hits
-system.l2c.overall_hits::total                2580085                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data         61532                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         60685                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total            122217                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data        12602                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data        13049                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total           25651                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          81623                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          50736                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             132359                       # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         1903                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.itb.walker         1980                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.inst        45534                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       135010                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       240877                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         1748                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.itb.walker         1646                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.inst        43900                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data        98157                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       176782                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         747537                       # number of ReadSharedReq misses
-system.l2c.InvalidateReq_misses::cpu0.data       445868                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::cpu1.data       117477                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::total         563345                       # number of InvalidateReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         1903                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         1980                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             45534                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            216633                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher       240877                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker         1748                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker         1646                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             43900                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            148893                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher       176782                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                879896                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         1903                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         1980                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            45534                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           216633                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       240877                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker         1748                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker         1646                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            43900                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           148893                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher       176782                       # number of overall misses
-system.l2c.overall_misses::total               879896                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data    390440000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data    373608000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total    764048000                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data     65654000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data     76676500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total    142330500                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   7135565500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   4240679000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  11376244500                       # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    166331500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    176995000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.inst   3903055500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data  11953058500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  28580004804                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    157717000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    151093000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.inst   3757434500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data   9007178500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  21390253127                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total  79243121431                       # number of ReadSharedReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu0.data     55722000                       # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu1.data     43983500                       # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::total     99705500                       # number of InvalidateReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker    166331500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker    176995000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   3903055500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  19088624000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  28580004804                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker    157717000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker    151093000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst   3757434500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data  13247857500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  21390253127                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     90619365931                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker    166331500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker    176995000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   3903055500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  19088624000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  28580004804                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker    157717000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker    151093000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst   3757434500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data  13247857500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  21390253127                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    90619365931                       # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks      2605015                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total      2605015                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data       218772                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data       192183                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total          410955                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data        49153                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data        48712                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total         97865                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       128293                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       108731                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           237024                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker         6735                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         5654                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.inst       453877                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data       674981                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       522297                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         7745                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         7142                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.inst       463801                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data       628672                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       452053                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      3222957                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu0.data       563301                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu1.data       240099                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::total       803400                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker         6735                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         5654                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          453877                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          803274                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher       522297                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         7745                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         7142                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          463801                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          737403                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher       452053                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             3459981                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker         6735                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         5654                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         453877                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         803274                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       522297                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         7745                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         7142                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         463801                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         737403                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher       452053                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            3459981                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.281261                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.315767                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.297398                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.256383                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.267881                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.262106                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.636223                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.466619                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.558420                       # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.282554                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.350195                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.100322                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.200020                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.461188                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.225694                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.230468                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.094653                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.156134                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.391065                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.231941                       # miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu0.data     0.791527                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu1.data     0.489286                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::total     0.701201                       # miss rate for InvalidateReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.282554                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.350195                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.100322                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.269688                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.461188                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.225694                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.230468                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.094653                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.201915                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.391065                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.254307                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.282554                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.350195                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.100322                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.269688                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.461188                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.225694                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.230468                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.094653                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.201915                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.391065                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.254307                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  6345.316258                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  6156.513142                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  6251.568931                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  5209.807967                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5876.044141                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  5548.731044                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 87421.014910                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83583.234784                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 85949.912737                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 87404.887020                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 89391.414141                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 85717.387008                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88534.615954                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 118649.787252                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 90227.116705                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 91794.046173                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 85590.763098                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 91762.976660                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 120997.913402                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 106005.617690                       # average ReadSharedReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu0.data   124.974208                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu1.data   374.400947                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::total   176.988346                       # average InvalidateReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 87404.887020                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 89391.414141                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 85717.387008                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 88115.033259                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 118649.787252                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 90227.116705                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 91794.046173                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 85590.763098                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 88975.690597                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 120997.913402                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 102988.723589                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 87404.887020                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 89391.414141                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 85717.387008                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 88115.033259                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 118649.787252                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 90227.116705                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 91794.046173                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 85590.763098                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 88975.690597                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 120997.913402                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 102988.723589                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs               494                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70601.106698                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70601.106698                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        91175                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 75451.862759                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 75457.288787                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        91175                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 75451.862759                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 75457.288787                       # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.l2c.tags.replacements                  1378015                       # number of replacements
+system.l2c.tags.tagsinuse                64998.786153                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    6107230                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1440978                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     4.238253                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle               9552186500                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   11716.268844                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker   133.184810                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   146.917074                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     4004.381376                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data    14231.433494                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher  7902.194687                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   315.518093                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   369.695425                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     2763.350410                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data    11175.503416                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 12240.338524                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.178776                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002032                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.002242                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.061102                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.217154                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.120578                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.004814                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.005641                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.042165                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.170525                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.186773                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.991803                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022        12060                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023          189                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        50714                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::0           60                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::1          153                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2         1009                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3         1115                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4         9723                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::3            4                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          184                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           15                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          163                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         1849                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         9563                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        39124                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.184021                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.002884                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.773834                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 69629880                       # Number of tag accesses
+system.l2c.tags.data_accesses                69629880                       # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.l2c.WritebackDirty_hits::writebacks      2641101                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total         2641101                       # number of WritebackDirty hits
+system.l2c.UpgradeReq_hits::cpu0.data          213424                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data          155298                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total              368722                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data         50511                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data         50527                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total            101038                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            63650                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            48993                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               112643                       # number of ReadExReq hits
+system.l2c.ReadSharedReq_hits::cpu0.dtb.walker        10681                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.itb.walker         5935                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.inst       422841                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data       567260                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       276728                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         9775                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4116                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.inst       406188                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data       512398                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       278781                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total          2494703                       # number of ReadSharedReq hits
+system.l2c.InvalidateReq_hits::cpu0.data       136557                       # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::cpu1.data       120325                       # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::total           256882                       # number of InvalidateReq hits
+system.l2c.demand_hits::cpu0.dtb.walker         10681                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          5935                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              422841                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              630910                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.l2cache.prefetcher       276728                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker          9775                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          4116                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              406188                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              561391                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.l2cache.prefetcher       278781                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2607346                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker        10681                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         5935                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             422841                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             630910                       # number of overall hits
+system.l2c.overall_hits::cpu0.l2cache.prefetcher       276728                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker         9775                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         4116                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             406188                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             561391                       # number of overall hits
+system.l2c.overall_hits::cpu1.l2cache.prefetcher       278781                       # number of overall hits
+system.l2c.overall_hits::total                2607346                       # number of overall hits
+system.l2c.UpgradeReq_misses::cpu0.data         24497                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data         25507                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             50004                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data          796                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data          825                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total            1621                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          72583                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          52296                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             124879                       # number of ReadExReq misses
+system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         1676                       # number of ReadSharedReq misses
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+system.l2c.ReadSharedReq_misses::cpu0.inst        56236                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data       130395                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       210895                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         1750                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.itb.walker         1829                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.inst        38017                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data       107679                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       200910                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total         750998                       # number of ReadSharedReq misses
+system.l2c.InvalidateReq_misses::cpu0.data       430773                       # number of InvalidateReq misses
+system.l2c.InvalidateReq_misses::cpu1.data       119101                       # number of InvalidateReq misses
+system.l2c.InvalidateReq_misses::total         549874                       # number of InvalidateReq misses
+system.l2c.demand_misses::cpu0.dtb.walker         1676                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.itb.walker         1611                       # number of demand (read+write) misses
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+system.l2c.demand_misses::cpu0.data            202978                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.l2cache.prefetcher       210895                       # number of demand (read+write) misses
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+system.l2c.demand_misses::cpu1.data            159975                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.l2cache.prefetcher       200910                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                875877                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker         1676                       # number of overall misses
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+system.l2c.overall_misses::cpu0.data           202978                       # number of overall misses
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+system.l2c.overall_misses::total               875877                       # number of overall misses
+system.l2c.UpgradeReq_miss_latency::cpu0.data    177641500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data    151031500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total    328673000                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data      8353500                       # number of SCUpgradeReq miss cycles
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+system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  24221293566                       # number of ReadSharedReq miss cycles
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+system.l2c.InvalidateReq_miss_latency::cpu0.data     43381500                       # number of InvalidateReq miss cycles
+system.l2c.InvalidateReq_miss_latency::cpu1.data     30876500                       # number of InvalidateReq miss cycles
+system.l2c.InvalidateReq_miss_latency::total     74258000                       # number of InvalidateReq miss cycles
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+system.l2c.demand_miss_latency::cpu1.inst   3283945500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data  14230677499                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  24221293566                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     91851401420                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker    151916500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.itb.walker    149670500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst   4848581000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data  18295017499                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  26350487356                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker    157377000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.itb.walker    162435000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst   3283945500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data  14230677499                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  24221293566                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    91851401420                       # number of overall miss cycles
+system.l2c.WritebackDirty_accesses::writebacks      2641101                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total      2641101                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data       237921                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data       180805                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total          418726                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data        51307                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data        51352                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total        102659                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       136233                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       101289                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           237522                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker        12357                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         7546                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.inst       479077                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data       697655                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       487623                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker        11525                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         5945                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.inst       444205                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data       620077                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       479691                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total      3245701                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu0.data       567330                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu1.data       239426                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::total       806756                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker        12357                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         7546                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          479077                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          833888                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.l2cache.prefetcher       487623                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker        11525                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         5945                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          444205                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          721366                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher       479691                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             3483223                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker        12357                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         7546                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         479077                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         833888                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       487623                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker        11525                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         5945                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         444205                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         721366                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher       479691                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            3483223                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.102963                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.141075                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.119419                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.015514                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.016066                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.015790                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.532786                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.516305                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.525758                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.135632                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.213491                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.117384                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.186905                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.432496                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.151844                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.307653                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.085584                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.173654                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.418832                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.231382                       # miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu0.data     0.759299                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu1.data     0.497444                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::total     0.681587                       # miss rate for InvalidateReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.135632                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.213491                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.117384                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.243412                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.432496                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.151844                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.307653                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.085584                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.221767                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.418832                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.251456                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.135632                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.213491                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.117384                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.243412                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.432496                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.151844                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.307653                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.085584                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.221767                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.418832                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.251456                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  7251.561416                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  5921.178500                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  6572.934165                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 10494.346734                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  9723.030303                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total 10101.789019                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 89084.517036                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 86664.448505                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 88071.056775                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 90642.303103                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 92905.338299                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 86218.454371                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 90716.637900                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 124946.003253                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 89929.714286                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 88810.825588                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 86380.974301                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90068.383807                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 120557.929252                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 107660.973692                       # average ReadSharedReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu0.data   100.706172                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu1.data   259.246354                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::total   135.045483                       # average InvalidateReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 90642.303103                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 92905.338299                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 86218.454371                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 90133.007020                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 124946.003253                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89929.714286                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 88810.825588                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 86380.974301                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 88955.633687                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 120557.929252                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 104867.922574                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 90642.303103                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 92905.338299                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 86218.454371                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 90133.007020                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 124946.003253                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89929.714286                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 88810.825588                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 86380.974301                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 88955.633687                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 120557.929252                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 104867.922574                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs               424                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        9                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        5                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs     54.888889                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs     84.800000                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.writebacks::writebacks             1068061                       # number of writebacks
-system.l2c.writebacks::total                  1068061                       # number of writebacks
-system.l2c.ReadSharedReq_mshr_hits::cpu0.inst           54                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu0.data           19                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.inst           49                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.data           43                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total          165                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst             54                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data             19                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst             49                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data             43                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                165                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst            54                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data            19                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst            49                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data            43                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total               165                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks        48108                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total        48108                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data        61532                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data        60685                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total       122217                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data        12602                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data        13049                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total        25651                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        81623                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        50736                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        132359                       # number of ReadExReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         1903                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         1980                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        45480                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data       134991                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       240877                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         1748                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         1646                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        43851                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data        98114                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       176782                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total       747372                       # number of ReadSharedReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu0.data       445868                       # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu1.data       117477                       # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::total       563345                       # number of InvalidateReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker         1903                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker         1980                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        45480                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       216614                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       240877                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker         1748                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker         1646                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst        43851                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data       148850                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       176782                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           879731                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker         1903                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker         1980                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        45480                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       216614                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       240877                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker         1748                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.itb.walker         1646                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst        43851                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data       148850                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       176782                       # number of overall MSHR misses
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 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   2719782000                       # number of ReadReq MSHR uncacheable cycles
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 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
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-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.315767                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.297398                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.256383                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.267881                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.262106                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.636223                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.466619                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.558420                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.282554                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.350195                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.100203                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.199992                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.461188                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.225694                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.230468                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.094547                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.156065                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.391065                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.231890                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.791527                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.489286                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::total     0.701201                       # mshr miss rate for InvalidateReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.282554                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.350195                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.100203                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.269664                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.461188                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.225694                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.230468                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.094547                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.201857                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.391065                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.254259                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.282554                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.350195                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.100203                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.269664                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.461188                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.225694                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.230468                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.094547                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.201857                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.391065                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.254259                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21760.189820                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21827.206064                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21793.465721                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24758.927154                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24820.062840                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24790.027679                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 77420.562538                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73582.192289                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 75949.234159                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 77404.887020                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 79390.910101                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75721.735400                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78536.396441                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 108648.993939                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 80226.260297                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 81792.833536                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 75608.300198                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 81766.937359                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110996.474030                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 96011.218611                       # average ReadSharedReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19970.157087                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20362.317730                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20051.936203                       # average InvalidateReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77404.887020                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79390.910101                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75721.735400                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 78115.935572                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 108648.993939                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80226.260297                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 81792.833536                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75608.300198                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 78977.140746                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110996.474030                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 92992.813894                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77404.887020                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79390.910101                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75721.735400                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 78115.935572                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 108648.993939                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80226.260297                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 81792.833536                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75608.300198                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 78977.140746                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110996.474030                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 92992.813894                       # average overall mshr miss latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.102963                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.141075                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.119419                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.015514                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.016066                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.015790                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.532786                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.516305                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.525758                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.135632                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.213491                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.117106                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.186813                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.432496                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.151844                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.307653                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.085384                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.173628                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.418832                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.231289                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.759299                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.497444                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::total     0.681587                       # mshr miss rate for InvalidateReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.135632                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.213491                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.117106                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.243335                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.432496                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.151844                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.307653                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.085384                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.221745                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.418832                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.251369                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.135632                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.213491                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.117106                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.243335                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.432496                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.151844                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.307653                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.085384                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.221745                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.418832                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.251369                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20538.269992                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20386.227310                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20460.713143                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24842.964824                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24346.060606                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24590.067859                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79084.015183                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 76663.895097                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 78070.533332                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 80641.112172                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 82903.479826                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 76244.907652                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80725.208799                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114944.988331                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79929.429143                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 78810.825588                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76423.394880                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80065.548777                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110557.251321                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 97673.842846                       # average ReadSharedReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19906.284749                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19870.744158                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19898.586767                       # average InvalidateReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80641.112172                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 82903.479826                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 76244.907652                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 80138.148487                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114944.988331                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79929.429143                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 78810.825588                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76423.394880                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 78953.433292                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110557.251321                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 94877.918238                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80641.112172                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 82903.479826                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76244.907652                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 80138.148487                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114944.988331                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79929.429143                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 78810.825588                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76423.394880                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 78953.433292                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110557.251321                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 94877.918238                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 157908.812439                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 67459.090909                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145322.987748                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 106109.716665                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 163719.381879                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst        69050                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143473.769616                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 106203.079428                       # average ReadReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 80464.483101                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 67459.090909                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 69795.318921                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 72180.858446                       # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests       3668271                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests      2217535                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests         3152                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 79289.613802                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst        69050                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 74823.486677                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 72216.646766                       # average overall mshr uncacheable latency
+system.membus.snoop_filter.tot_requests       3586859                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests      2135577                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests         3113                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq               81829                       # Transaction distribution
-system.membus.trans_dist::ReadResp             838129                       # Transaction distribution
-system.membus.trans_dist::WriteReq              38464                       # Transaction distribution
-system.membus.trans_dist::WriteResp             38464                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1174756                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           216961                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           398327                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq         309165                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp              22                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            145872                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           127949                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        756300                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        666856                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122616                       # Packet count per connected master and slave (bytes)
+system.membus.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadReq               81835                       # Transaction distribution
+system.membus.trans_dist::ReadResp             841453                       # Transaction distribution
+system.membus.trans_dist::WriteReq              38513                       # Transaction distribution
+system.membus.trans_dist::WriteResp             38513                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1169257                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           224172                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           330190                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq         306798                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp              21                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq            2                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            142313                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           124217                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        759618                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        654423                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122940                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           92                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        26280                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4403166                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4552154                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237974                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       237974                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4790128                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155723                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        26066                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4320804                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4469902                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       238504                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       238504                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4708406                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155955                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          204                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        52560                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    124524268                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    124732755                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7257216                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7257216                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               131989971                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           572885                       # Total snoops (count)
-system.membus.snoopTraffic                     188480                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples           2396814                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.013654                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.116050                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        52132                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    124129580                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    124337871                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7276480                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7276480                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               131614351                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           603280                       # Total snoops (count)
+system.membus.snoopTraffic                     185472                       # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples           2313692                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.013382                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.114902                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 2364088     98.63%     98.63% # Request fanout histogram
-system.membus.snoop_fanout::1                   32726      1.37%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 2282731     98.66%     98.66% # Request fanout histogram
+system.membus.snoop_fanout::1                   30961      1.34%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2396814                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           101168498                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             2313692                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           101576998                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               54500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            21745999                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            21542999                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          8211058586                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          8037178912                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         4830240380                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         4828786098                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           45484396                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           45456460                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
 system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
 system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
 system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
 system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
 system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
@@ -3309,78 +3309,78 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
 system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests     10770571                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      5860830                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests      1720391                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops         132185                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops       120739                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops        11446                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47403574916500                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadReq              81831                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           4048119                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             38464                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            38464                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty      3673076                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         2310912                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          679438                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq        381379                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp        1060817                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq          109                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp          109                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           291982                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          291982                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      3967045                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq       832947                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp       803400                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      8640930                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7144066                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              15784996                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    212830169                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    175839034                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              388669203                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         2716758                       # Total snoops (count)
-system.toL2Bus.snoopTraffic                 119453392                       # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples          7607581                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.354994                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.481646                       # Request fanout histogram
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.snoop_filter.tot_requests     10929949                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      5951808                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests      1800454                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops         181173                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops       166358                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops        14815                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47374315410500                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.trans_dist::ReadReq              81837                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           4119674                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             38513                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            38513                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty      3703405                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         2363493                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          695815                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq        407836                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp        1103651                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq          102                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp          102                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           294367                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          294367                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      4038548                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq       834564                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp       806756                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      8843715                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7139942                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              15983657                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    216752505                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    175713942                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              392466447                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         2839573                       # Total snoops (count)
+system.toL2Bus.snoopTraffic                 122328784                       # Total snoop traffic (bytes)
+system.toL2Bus.snoop_fanout::samples          7769609                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.368989                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.486467                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                4918380     64.65%     64.65% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                2677755     35.20%     99.85% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                  11446      0.15%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                4917524     63.29%     63.29% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                2837270     36.52%     99.81% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                  14815      0.19%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            7607581                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         8483488339                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            7769609                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         8597464366                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          2591888                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          2599172                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        3918166834                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        4012155776                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        3514899349                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        3555978029                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt
index 89d0e34be..db63d86a7 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt
@@ -1,139 +1,139 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.759348                       # Number of seconds simulated
-sim_ticks                                51759347706500                       # Number of ticks simulated
-final_tick                               51759347706500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.820895                       # Number of seconds simulated
+sim_ticks                                51820894502500                       # Number of ticks simulated
+final_tick                               51820894502500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 706961                       # Simulator instruction rate (inst/s)
-host_op_rate                                   830795                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            43773319280                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 670816                       # Number of bytes of host memory used
-host_seconds                                  1182.44                       # Real time elapsed on the host
-sim_insts                                   835939132                       # Number of instructions simulated
-sim_ops                                     982366087                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 612269                       # Simulator instruction rate (inst/s)
+host_op_rate                                   719485                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            35448799247                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 680056                       # Number of bytes of host memory used
+host_seconds                                  1461.85                       # Real time elapsed on the host
+sim_insts                                   895045967                       # Number of instructions simulated
+sim_ops                                    1051780871                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.dtb.walker       152192                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker       158144                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           4715828                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          36073224                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        410496                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             41509884                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      4715828                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         4715828                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     62909632                       # Number of bytes written to this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.dtb.walker       268032                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker       256704                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           5200500                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          51306824                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        409600                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             57441660                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      5200500                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         5200500                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     78712256                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          62930212                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker         2378                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker         2471                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             114092                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             563657                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6414                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                689012                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          982963                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          78732836                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker         4188                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker         4011                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             121665                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             801682                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6400                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                937946                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1229879                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               985536                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker           2940                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker           3055                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst                91111                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               696941                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             7931                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                  801978                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           91111                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              91111                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1215426                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data                 398                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1215823                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1215426                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          2940                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker          3055                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               91111                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              697339                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            7931                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2017802                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        689012                       # Number of read requests accepted
-system.physmem.writeReqs                       985536                       # Number of write requests accepted
-system.physmem.readBursts                      689012                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     985536                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 44056384                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     40384                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  62928960                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  41509884                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               62930212                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      631                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_writes::total              1232452                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           5172                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker           4954                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               100355                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               990080                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             7904                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1108465                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          100355                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             100355                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1518929                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data                 397                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1519326                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1518929                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          5172                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker          4954                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              100355                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              990477                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            7904                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2627791                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        937946                       # Number of read requests accepted
+system.physmem.writeReqs                      1232452                       # Number of write requests accepted
+system.physmem.readBursts                      937946                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1232452                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 59993856                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     34688                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  78731584                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  57441660                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               78732836                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      542                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               41424                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               42196                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               39305                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               41228                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               37796                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               46284                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               37646                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               36984                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               37874                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               85067                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              43899                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              46232                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              39321                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              40035                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              35465                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              37625                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               61899                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               62487                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               61087                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               63695                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               58991                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               64628                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               58592                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               59025                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               60354                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               64900                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              63044                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              64791                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              60176                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              61598                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              57895                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              60103                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               58989                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               58919                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               58679                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               55735                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               54249                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               59544                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               52586                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               53926                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               52975                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              101116                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              56481                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              59298                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              53072                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              58564                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              50527                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              52744                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               76908                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               78477                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               80133                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               78953                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               75778                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               80212                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               72590                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               74527                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               74121                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               79665                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              76241                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              79585                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              74881                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              79432                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              73606                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              75072                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          19                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51759344769500                       # Total gap between requests
+system.physmem.numWrRetry                          41                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51820891581500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                   43101                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  645896                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  894830                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 982963                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    659454                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     23139                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       405                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       338                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       474                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       555                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       545                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      1172                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       668                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       279                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      358                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      162                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      174                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      128                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      114                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      108                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                       96                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                       92                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       72                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       47                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1229879                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    903506                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     28089                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       425                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       344                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       490                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       475                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       651                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       467                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      1235                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       309                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      395                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      169                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      183                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      135                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      109                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      107                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       97                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                       93                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       74                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       51                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
@@ -160,168 +160,154 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::62                       46                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       47                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       438828                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      243.797169                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     147.013209                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     285.979705                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         194919     44.42%     44.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       116778     26.61%     71.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        38832      8.85%     79.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        20430      4.66%     84.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        13130      2.99%     87.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         8793      2.00%     89.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         7414      1.69%     91.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         5819      1.33%     92.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        32713      7.45%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         438828                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         52143                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        13.201312                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      141.003763                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          52140     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                    33600                       # What write queue length does an incoming req see
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+system.physmem.bytesPerActivate::samples       563432                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      246.214486                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     148.153142                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     287.290760                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         250076     44.38%     44.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       147098     26.11%     70.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        49891      8.85%     79.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        26994      4.79%     84.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        18337      3.25%     87.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        11939      2.12%     89.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         8931      1.59%     91.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         7653      1.36%     92.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        42513      7.55%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         563432                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         66023                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        14.197810                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      125.335088                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          66020    100.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::20480-21503            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::23552-24575            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           52143                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         52143                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        18.857085                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.140227                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        8.284435                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           48446     92.91%     92.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23            1855      3.56%     96.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             116      0.22%     96.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             101      0.19%     96.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              48      0.09%     96.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             101      0.19%     97.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             252      0.48%     97.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              24      0.05%     97.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             307      0.59%     98.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              75      0.14%     98.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              29      0.06%     98.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              51      0.10%     98.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             313      0.60%     99.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              41      0.08%     99.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              37      0.07%     99.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79             129      0.25%     99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83             166      0.32%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               2      0.00%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.00%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               1      0.00%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.00%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             2      0.00%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             3      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             2      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            11      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             2      0.00%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147            15      0.03%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             3      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-211             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           52143                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     9222624910                       # Total ticks spent queuing
-system.physmem.totMemAccLat               22129768660                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   3441905000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       13397.56                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total           66023                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         66023                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        18.632613                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.082710                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        6.894597                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23           62853     95.20%     95.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31            1132      1.71%     96.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39            1165      1.76%     98.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47             145      0.22%     98.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55              61      0.09%     98.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63              50      0.08%     99.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71             451      0.68%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79              71      0.11%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87              27      0.04%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95               7      0.01%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103              4      0.01%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111            11      0.02%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119             4      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135            20      0.03%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143             9      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167             4      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191             2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199             4      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::264-271             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           66023                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    12434281516                       # Total ticks spent queuing
+system.physmem.totMemAccLat               30010606516                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   4687020000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       13264.59                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  32147.56                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           0.85                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.22                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        0.80                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.22                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  32014.59                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.16                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.52                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.11                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.52                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.01                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     507228                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    725589                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   73.68                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.79                       # Row buffer hit rate for writes
-system.physmem.avgGap                     30909442.29                       # Average gap between requests
-system.physmem.pageHitRate                      73.75                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 1651557600                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  901147500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                2518331400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3177817920                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3380668873920                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1280908967265                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29932003411500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34601830107105                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.513662                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49794254360042                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1728358320000                       # Time in different power states
+system.physmem.avgWrQLen                        23.96                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     702833                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    901319                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   74.98                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.27                       # Row buffer hit rate for writes
+system.physmem.avgGap                     23876216.06                       # Average gap between requests
+system.physmem.pageHitRate                      74.01                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 2165373000                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1181503125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                3530451600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               4001905440                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3384688532160                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1300349435715                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29951875881000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34647793082040                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.606693                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49827060150280                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1730413360000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    236733614958                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    263420580720                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 1665982080                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  909018000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                2851001400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3193739280                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3380668873920                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1282600048680                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29930520006750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34602408670110                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.524840                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49791748874504                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1728358320000                       # Time in different power states
+system.physmem_1.actEnergy                 2094172920                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1142653875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                3781260600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3969667440                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3384688532160                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1299689474040                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29952454794750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34647820555785                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.607223                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49827979372630                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1730413360000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    239239854996                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    262496082370                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
 system.realview.nvmem.bytes_read::cpu.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
@@ -338,9 +324,9 @@ system.realview.nvmem.bw_inst_read::total            2                       # I
 system.realview.nvmem.bw_total::cpu.inst            2                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total               3                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
@@ -348,7 +334,7 @@ system.cf0.dma_write_full_pages                  1666                       # Nu
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -378,72 +364,69 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks                    186389                       # Table walker walks requested
-system.cpu.dtb.walker.walksLong                186389                       # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksLongTerminationLevel::Level2        11673                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksLongTerminationLevel::Level3       145933                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore           20                       # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples       186369                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean     0.214628                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev    70.564506                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-2047       186367    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.walks                    214264                       # Table walker walks requested
+system.cpu.dtb.walker.walksLong                214264                       # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2        17030                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3       164948                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore           21                       # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples       214243                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean     0.140028                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev    46.737844                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-2047       214241    100.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::10240-12287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::26624-28671            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total       186369                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples       157626                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 24833.263548                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 20845.971920                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 18169.669952                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-65535       156391     99.22%     99.22% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-131071            5      0.00%     99.22% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-196607         1058      0.67%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-262143           24      0.02%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-327679           78      0.05%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-393215           18      0.01%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::393216-458751           45      0.03%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::589824-655359            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total       157626                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples  -5176298892                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean     1.304609                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::gmean          inf                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0      1576748204    -30.46%    -30.46% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::1     -6753047096    130.46%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total  -5176298892                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K        145934     92.59%     92.59% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M         11673      7.41%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total       157607                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       186389                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkWaitTime::16384-18431            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total       214243                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples       181999                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 24181.814186                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 20419.578200                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 15522.698406                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-65535       180089     98.95%     98.95% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-131071         1633      0.90%     99.85% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-196607          118      0.06%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::196608-262143           77      0.04%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-327679           52      0.03%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::327680-393215           23      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-458751            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total       181999                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples   4819875556                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean     1.150179                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0      -723841796    -15.02%    -15.02% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::1      5543717352    115.02%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total   4819875556                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K        164949     90.64%     90.64% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M         17030      9.36%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total       181979                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       214264                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total       186389                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       157607                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total       214264                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       181979                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total       157607                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total       343996                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total       181979                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total       396243                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                    157302470                       # DTB read hits
-system.cpu.dtb.read_misses                     138254                       # DTB read misses
-system.cpu.dtb.write_hits                   142797891                       # DTB write hits
-system.cpu.dtb.write_misses                     48135                       # DTB write misses
+system.cpu.dtb.read_hits                    168009449                       # DTB read hits
+system.cpu.dtb.read_misses                     157878                       # DTB read misses
+system.cpu.dtb.write_hits                   152852610                       # DTB write hits
+system.cpu.dtb.write_misses                     56386                       # DTB write misses
 system.cpu.dtb.flush_tlb                           10                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid               38509                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid                    1009                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                    71109                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_tlb_mva_asid               43022                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                    1067                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                    75936                       # Number of entries that have been flushed from TLB
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   6989                       # Number of TLB faults due to prefetch
+system.cpu.dtb.prefetch_faults                   8201                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                     18784                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                157440724                       # DTB read accesses
-system.cpu.dtb.write_accesses               142846026                       # DTB write accesses
+system.cpu.dtb.perms_faults                     19949                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                168167327                       # DTB read accesses
+system.cpu.dtb.write_accesses               152908996                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                         300100361                       # DTB hits
-system.cpu.dtb.misses                          186389                       # DTB misses
-system.cpu.dtb.accesses                     300286750                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.hits                         320862059                       # DTB hits
+system.cpu.dtb.misses                          214264                       # DTB misses
+system.cpu.dtb.accesses                     321076323                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -473,829 +456,832 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks                    119383                       # Table walker walks requested
-system.cpu.itb.walker.walksLong                119383                       # Table walker walks initiated with long descriptors
-system.cpu.itb.walker.walksLongTerminationLevel::Level2         1122                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksLongTerminationLevel::Level3       107813                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walkWaitTime::samples       119383                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0          119383    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total       119383                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples       108935                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 28686.574563                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 24766.127594                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 21816.949759                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-65535       107446     98.63%     98.63% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-131071            3      0.00%     98.64% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-196607         1285      1.18%     99.82% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::196608-262143           37      0.03%     99.85% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::262144-327679           72      0.07%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::327680-393215           42      0.04%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::393216-458751           32      0.03%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::458752-524287            9      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::524288-589823            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::589824-655359            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total       108935                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples   1449611704                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0      1449611704    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total   1449611704                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K        107813     98.97%     98.97% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::2M          1122      1.03%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total       108935                       # Table walker page sizes translated
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.walks                    122945                       # Table walker walks requested
+system.cpu.itb.walker.walksLong                122945                       # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walksLongTerminationLevel::Level2         1119                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksLongTerminationLevel::Level3       110624                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walkWaitTime::samples       122945                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0          122945    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total       122945                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples       111743                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 27331.219853                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 23493.082733                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 18310.002732                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-65535       109587     98.07%     98.07% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-131071         1865      1.67%     99.74% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-196607          133      0.12%     99.86% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::196608-262143           84      0.08%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-327679           40      0.04%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-393215           22      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::393216-458751            5      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::458752-524287            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total       111743                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples   -850328296                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0      -850328296    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total   -850328296                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K        110624     99.00%     99.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M          1119      1.00%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total       111743                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       119383                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total       119383                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       122945                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total       122945                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       108935                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total       108935                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total       228318                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                    836454912                       # ITB inst hits
-system.cpu.itb.inst_misses                     119383                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       111743                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total       111743                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total       234688                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                    895597591                       # ITB inst hits
+system.cpu.itb.inst_misses                     122945                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.itb.flush_tlb                           10                       # Number of times complete TLB was flushed
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid               38509                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid                    1009                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                    50925                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb_mva_asid               43022                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                    1067                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                    53957                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
 system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                836574295                       # ITB inst accesses
-system.cpu.itb.hits                         836454912                       # DTB hits
-system.cpu.itb.misses                          119383                       # DTB misses
-system.cpu.itb.accesses                     836574295                       # DTB accesses
-system.cpu.numPwrStateTransitions               32056                       # Number of power state transitions
-system.cpu.pwrStateClkGateDist::samples         16028                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::mean     3133878336.314075                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::stdev    60741761061.559830                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::underflows         6738     42.04%     42.04% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1000-5e+10         9255     57.74%     99.78% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::5e+10-1e+11            5      0.03%     99.81% # Distribution of time spent in the clock gated state
+system.cpu.itb.inst_accesses                895720536                       # ITB inst accesses
+system.cpu.itb.hits                         895597591                       # DTB hits
+system.cpu.itb.misses                          122945                       # DTB misses
+system.cpu.itb.accesses                     895720536                       # DTB accesses
+system.cpu.numPwrStateTransitions               32698                       # Number of power state transitions
+system.cpu.pwrStateClkGateDist::samples         16349                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::mean     3072754762.549147                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::stdev    59826711358.002258                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::underflows         7060     43.18%     43.18% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1000-5e+10         9253     56.60%     99.78% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::5e+10-1e+11            6      0.04%     99.82% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::1e+11-1.5e+11            3      0.02%     99.83% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::1.5e+11-2e+11            2      0.01%     99.84% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::2e+11-2.5e+11            1      0.01%     99.85% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::2.5e+11-3e+11            2      0.01%     99.86% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::3e+11-3.5e+11            1      0.01%     99.87% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::4.5e+11-5e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::7e+11-7.5e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::8e+11-8.5e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::1.5e+11-2e+11            1      0.01%     99.84% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::2e+11-2.5e+11            2      0.01%     99.85% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::2.5e+11-3e+11            1      0.01%     99.86% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::3e+11-3.5e+11            2      0.01%     99.87% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::5e+11-5.5e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::6.5e+11-7e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::7.5e+11-8e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::overflows           18      0.11%    100.00% # Distribution of time spent in the clock gated state
 system.cpu.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::max_value 1988775138696                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateClkGateDist::total           16028                       # Distribution of time spent in the clock gated state
-system.cpu.pwrStateResidencyTicks::ON    1529545732058                       # Cumulative time (in ticks) in various power states
-system.cpu.pwrStateResidencyTicks::CLK_GATED 50229801974442                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                     103518695413                       # number of cpu cycles simulated
+system.cpu.pwrStateClkGateDist::max_value 1988775178432                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateClkGateDist::total           16349                       # Distribution of time spent in the clock gated state
+system.cpu.pwrStateResidencyTicks::ON    1584426889584                       # Cumulative time (in ticks) in various power states
+system.cpu.pwrStateResidencyTicks::CLK_GATED 50236467612916                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                     103641789005                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    16028                       # number of quiesce instructions executed
-system.cpu.committedInsts                   835939132                       # Number of instructions committed
-system.cpu.committedOps                     982366087                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             902933087                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                 900158                       # Number of float alu accesses
-system.cpu.num_func_calls                    50090187                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts    126876498                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    902933087                       # number of integer instructions
-system.cpu.num_fp_insts                        900158                       # number of float instructions
-system.cpu.num_int_register_reads          1308206945                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          715740470                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads              1453094                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes              759824                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            216985275                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes           216380044                       # number of times the CC registers were written
-system.cpu.num_mem_refs                     300079118                       # number of memory refs
-system.cpu.num_load_insts                   157292666                       # Number of load instructions
-system.cpu.num_store_insts                  142786452                       # Number of store instructions
-system.cpu.num_idle_cycles               100459603948.882050                       # Number of idle cycles
-system.cpu.num_busy_cycles               3059091464.117941                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.029551                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.970449                       # Percentage of idle cycles
-system.cpu.Branches                         186526742                       # Number of branches fetched
+system.cpu.kern.inst.quiesce                    16349                       # number of quiesce instructions executed
+system.cpu.committedInsts                   895045967                       # Number of instructions committed
+system.cpu.committedOps                    1051780871                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             965574423                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                 894989                       # Number of float alu accesses
+system.cpu.num_func_calls                    52935800                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts    136802593                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    965574423                       # number of integer instructions
+system.cpu.num_fp_insts                        894989                       # number of float instructions
+system.cpu.num_int_register_reads          1409614532                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          766141547                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads              1442074                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes              760100                       # number of times the floating registers were written
+system.cpu.num_cc_register_reads            235678872                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes           235085086                       # number of times the CC registers were written
+system.cpu.num_mem_refs                     320845878                       # number of memory refs
+system.cpu.num_load_insts                   168002679                       # Number of load instructions
+system.cpu.num_store_insts                  152843199                       # Number of store instructions
+system.cpu.num_idle_cycles               100472935225.830063                       # Number of idle cycles
+system.cpu.num_busy_cycles               3168853779.169939                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.030575                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.969425                       # Percentage of idle cycles
+system.cpu.Branches                         199903261                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     1      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                 680504734     69.23%     69.23% # Class of executed instruction
-system.cpu.op_class::IntMult                  2132093      0.22%     69.45% # Class of executed instruction
-system.cpu.op_class::IntDiv                     96706      0.01%     69.46% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     69.46% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     69.46% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     69.46% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     69.46% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     69.46% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     69.46% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     69.46% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     69.46% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     69.46% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     69.46% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     69.46% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     69.46% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     69.46% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     69.46% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     69.46% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     69.46% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     69.46% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   8      0.00%     69.46% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     69.46% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                  13      0.00%     69.46% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                  21      0.00%     69.46% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     69.46% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc             112297      0.01%     69.47% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     69.47% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     69.47% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     69.47% # Class of executed instruction
-system.cpu.op_class::MemRead                157292666     16.00%     85.47% # Class of executed instruction
-system.cpu.op_class::MemWrite               142786452     14.53%    100.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                 729096517     69.28%     69.28% # Class of executed instruction
+system.cpu.op_class::IntMult                  2224980      0.21%     69.49% # Class of executed instruction
+system.cpu.op_class::IntDiv                     97778      0.01%     69.50% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     69.50% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     69.50% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     69.50% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     69.50% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     69.50% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     69.50% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     69.50% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     69.50% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     69.50% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     69.50% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     69.50% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     69.50% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     69.50% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     69.50% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     69.50% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     69.50% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     69.50% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   8      0.00%     69.50% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     69.50% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                  13      0.00%     69.50% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                  21      0.00%     69.50% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     69.50% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc             110423      0.01%     69.51% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     69.51% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     69.51% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     69.51% # Class of executed instruction
+system.cpu.op_class::MemRead                168002679     15.96%     85.48% # Class of executed instruction
+system.cpu.op_class::MemWrite               152843199     14.52%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  982924991                       # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements           9370067                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.942718                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           290532688                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9370579                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             31.004774                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        5830299500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.942718                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999888                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999888                       # Average percentage of cache occupancy
+system.cpu.op_class::total                 1052375619                       # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements          10244350                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.965651                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           310416272                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs          10244862                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             30.299703                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        3504161500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.965651                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999933                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999933                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          413                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           51                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          392                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           71                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1209437211                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1209437211                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data    147248395                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       147248395                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    135579268                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      135579268                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       373548                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        373548                       # number of SoftPFReq hits
-system.cpu.dcache.WriteLineReq_hits::cpu.data       331872                       # number of WriteLineReq hits
-system.cpu.dcache.WriteLineReq_hits::total       331872                       # number of WriteLineReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      3336329                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      3336329                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data      3621011                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      3621011                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     283159535                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        283159535                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    283533083                       # number of overall hits
-system.cpu.dcache.overall_hits::total       283533083                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      4886658                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       4886658                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1993718                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1993718                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data      1137538                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total      1137538                       # number of SoftPFReq misses
-system.cpu.dcache.WriteLineReq_misses::cpu.data      1221988                       # number of WriteLineReq misses
-system.cpu.dcache.WriteLineReq_misses::total      1221988                       # number of WriteLineReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data       286320                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total       286320                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      8102364                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        8102364                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      9239902                       # number of overall misses
-system.cpu.dcache.overall_misses::total       9239902                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  84160893500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  84160893500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  69982072000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  69982072000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  48119896000                       # number of WriteLineReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::total  48119896000                       # number of WriteLineReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   4409003500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total   4409003500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       162000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       162000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 202262861500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 202262861500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 202262861500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 202262861500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    152135053                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    152135053                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    137572986                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    137572986                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data      1511086                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total      1511086                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::cpu.data      1553860                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::total      1553860                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3622649                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      3622649                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data      3621013                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      3621013                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    291261899                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    291261899                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    292772985                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    292772985                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.032121                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.032121                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.014492                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.014492                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.752795                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.752795                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.786421                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::total     0.786421                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.079036                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.079036                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.tags.tag_accesses        1293353364                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1293353364                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data    156944978                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       156944978                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    145025968                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      145025968                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       395817                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        395817                       # number of SoftPFReq hits
+system.cpu.dcache.WriteLineReq_hits::cpu.data       335163                       # number of WriteLineReq hits
+system.cpu.dcache.WriteLineReq_hits::total       335163                       # number of WriteLineReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      3689072                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      3689072                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      3994801                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      3994801                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     302306109                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        302306109                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    302701926                       # number of overall hits
+system.cpu.dcache.overall_hits::total       302701926                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      5326710                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       5326710                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2212553                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2212553                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data      1311764                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total      1311764                       # number of SoftPFReq misses
+system.cpu.dcache.WriteLineReq_misses::cpu.data      1232866                       # number of WriteLineReq misses
+system.cpu.dcache.WriteLineReq_misses::total      1232866                       # number of WriteLineReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data       307422                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total       307422                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data            3                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total            3                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      8772129                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        8772129                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     10083893                       # number of overall misses
+system.cpu.dcache.overall_misses::total      10083893                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  84631439000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  84631439000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  66820707500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  66820707500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  25293878500                       # number of WriteLineReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::total  25293878500                       # number of WriteLineReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   4522600000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total   4522600000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       197000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       197000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 176746025000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 176746025000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 176746025000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 176746025000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    162271688                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    162271688                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    147238521                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    147238521                       # number of WriteReq accesses(hits+misses)
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+system.cpu.dcache.SoftPFReq_accesses::total      1707581                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::cpu.data      1568029                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::total      1568029                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3996494                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      3996494                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data      3994804                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      3994804                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    311078238                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    311078238                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    312785819                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    312785819                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.032826                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.032826                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015027                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.015027                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.768200                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.768200                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.786252                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::total     0.786252                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.076923                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.076923                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000001                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.027818                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.027818                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.031560                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.031560                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17222.587196                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 17222.587196                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35101.289149                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 35101.289149                       # average WriteReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 39378.370328                       # average WriteLineReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::total 39378.370328                       # average WriteLineReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15398.866653                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15398.866653                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        81000                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total        81000                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 24963.438016                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 24963.438016                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 21890.152244                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 21890.152244                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.028199                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.028199                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.032239                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.032239                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15888.125879                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15888.125879                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30200.726265                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 30200.726265                       # average WriteReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 20516.324159                       # average WriteLineReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::total 20516.324159                       # average WriteLineReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14711.373942                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14711.373942                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 65666.666667                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 65666.666667                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 20148.589356                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 20148.589356                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 17527.558553                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 17527.558553                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks      7310347                       # number of writebacks
-system.cpu.dcache.writebacks::total           7310347                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        21149                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        21149                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        21212                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        21212                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        69210                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        69210                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        42361                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        42361                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        42361                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        42361                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      4865509                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      4865509                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1972506                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1972506                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1135773                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total      1135773                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1221988                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::total      1221988                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       217110                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total       217110                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      8060003                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      8060003                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      9195776                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9195776                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33702                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.ReadReq_mshr_uncacheable::total        33702                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33708                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total        33708                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67410                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total        67410                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  78024875000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  78024875000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  67036106500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  67036106500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  21307541000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  21307541000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  46897908000                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  46897908000                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   2989370500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   2989370500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       160000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       160000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191958889500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 191958889500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 213266430500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 213266430500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6199627500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6199627500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6199627500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   6199627500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.031982                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.031982                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014338                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014338                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.751627                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.751627                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.786421                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.786421                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.059931                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.059931                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.writebacks::writebacks      7906430                       # number of writebacks
+system.cpu.dcache.writebacks::total           7906430                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        21920                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        21920                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        21246                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        21246                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        70972                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        70972                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data        43166                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        43166                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        43166                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        43166                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5304790                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      5304790                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2191307                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      2191307                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1309953                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total      1309953                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1232866                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::total      1232866                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       236450                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total       236450                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            3                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total            3                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      8728963                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      8728963                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data     10038916                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total     10038916                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33706                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.ReadReq_mshr_uncacheable::total        33706                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33710                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total        33710                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67416                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total        67416                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  78748278500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  78748278500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  63964841000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  63964841000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  21083631000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  21083631000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  24061012500                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  24061012500                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3160913500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3160913500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       194000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       194000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 166774132000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 166774132000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187857763000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 187857763000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6233075000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6233075000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6233075000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   6233075000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032691                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032691                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014883                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014883                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.767140                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.767140                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.786252                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.786252                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.059164                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.059164                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000001                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.027673                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.027673                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.031409                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.031409                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16036.323229                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16036.323229                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33985.248461                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33985.248461                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18760.386979                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18760.386979                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 38378.370328                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 38378.370328                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13768.921284                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13768.921284                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        80000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        80000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23816.230527                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 23816.230527                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23191.781803                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 23191.781803                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183954.290547                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183954.290547                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91968.958611                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91968.958611                       # average overall mshr uncacheable latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements          13316326                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.820794                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           823138069                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs          13316838                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             61.811826                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       49363844500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.820794                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.999650                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.999650                       # Average percentage of cache occupancy
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.028060                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.028060                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.032095                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.032095                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14844.749462                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14844.749462                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29190.269095                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29190.269095                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16094.952262                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16094.952262                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 19516.324159                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 19516.324159                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13368.211038                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13368.211038                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 64666.666667                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 64666.666667                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19105.835596                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 19105.835596                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18712.952972                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 18712.952972                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184924.790838                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184924.790838                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92456.909339                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92456.909339                       # average overall mshr uncacheable latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements          13792548                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.891104                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           881804526                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs          13793060                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             63.931030                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       31603903500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.891104                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.999787                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.999787                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          243                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          197                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          200                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         849771755                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        849771755                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst    823138069                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       823138069                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     823138069                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        823138069                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    823138069                       # number of overall hits
-system.cpu.icache.overall_hits::total       823138069                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst     13316843                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total      13316843                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst     13316843                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total       13316843                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst     13316843                       # number of overall misses
-system.cpu.icache.overall_misses::total      13316843                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 182043679500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 182043679500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 182043679500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 182043679500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 182043679500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 182043679500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    836454912                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    836454912                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    836454912                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    836454912                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    836454912                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    836454912                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.015921                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.015921                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.015921                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.015921                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.015921                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.015921                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13670.182903                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13670.182903                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13670.182903                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13670.182903                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13670.182903                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13670.182903                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses         909390656                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        909390656                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst    881804526                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       881804526                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     881804526                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        881804526                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    881804526                       # number of overall hits
+system.cpu.icache.overall_hits::total       881804526                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst     13793065                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total      13793065                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst     13793065                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total       13793065                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst     13793065                       # number of overall misses
+system.cpu.icache.overall_misses::total      13793065                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 185289814000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 185289814000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 185289814000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 185289814000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 185289814000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 185289814000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    895597591                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    895597591                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    895597591                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    895597591                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    895597591                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    895597591                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.015401                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.015401                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.015401                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.015401                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.015401                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.015401                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13433.548961                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13433.548961                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13433.548961                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13433.548961                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13433.548961                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13433.548961                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks     13316326                       # number of writebacks
-system.cpu.icache.writebacks::total          13316326                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst     13316843                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total     13316843                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst     13316843                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total     13316843                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst     13316843                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total     13316843                       # number of overall MSHR misses
+system.cpu.icache.writebacks::writebacks     13792548                       # number of writebacks
+system.cpu.icache.writebacks::total          13792548                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst     13793065                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total     13793065                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst     13793065                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total     13793065                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst     13793065                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total     13793065                       # number of overall MSHR misses
 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        43125                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.ReadReq_mshr_uncacheable::total        43125                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        43125                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses::total        43125                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168726836500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 168726836500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168726836500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 168726836500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168726836500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 168726836500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   5436787000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   5436787000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   5436787000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total   5436787000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.015921                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.015921                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.015921                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.015921                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.015921                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.015921                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12670.182903                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12670.182903                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12670.182903                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12670.182903                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12670.182903                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12670.182903                       # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126070.423188                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.423188                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126070.423188                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126070.423188                       # average overall mshr uncacheable latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements          1029342                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65301.929117                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           41597878                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1091508                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            38.110466                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      12385503500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 38086.632918                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   236.862091                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   354.562935                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  7802.558346                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 18821.312827                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.581156                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.003614                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.005410                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.119058                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.287190                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.996428                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023          232                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        61934                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4          229                       # Occupied blocks per task id
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 171496749000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 171496749000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 171496749000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 171496749000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 171496749000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 171496749000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   3263374000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   3263374000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   3263374000                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total   3263374000                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.015401                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.015401                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.015401                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.015401                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.015401                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.015401                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12433.548961                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12433.548961                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12433.548961                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12433.548961                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12433.548961                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12433.548961                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75672.440580                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75672.440580                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75672.440580                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75672.440580                       # average overall mshr uncacheable latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.replacements          1308215                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65291.954914                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           46007809                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1371583                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            33.543584                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle       6631976500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 10023.392915                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   424.218871                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   466.075042                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  6280.682260                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 48097.585826                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.152945                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.006473                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.007112                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.095836                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.733911                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.996276                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023          271                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        63097                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4          271                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           33                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          403                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2431                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5392                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        53675                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.003540                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.945038                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        371610075                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       371610075                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       312133                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       242520                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         554653                       # number of ReadReq hits
-system.cpu.l2cache.WritebackDirty_hits::writebacks      7310347                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      7310347                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks     13314767                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total     13314767                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data         8998                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total         8998                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1590193                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1590193                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     13245839                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total     13245839                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      5993599                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      5993599                       # number of ReadSharedReq hits
-system.cpu.l2cache.InvalidateReq_hits::cpu.data       742035                       # number of InvalidateReq hits
-system.cpu.l2cache.InvalidateReq_hits::total       742035                       # number of InvalidateReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker       312133                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker       242520                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst     13245839                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      7583792                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total        21384284                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker       312133                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker       242520                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst     13245839                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      7583792                       # number of overall hits
-system.cpu.l2cache.overall_hits::total       21384284                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         2378                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         2471                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         4849                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data        33265                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total        33265                       # number of UpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       340050                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       340050                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        71004                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        71004                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       224793                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       224793                       # number of ReadSharedReq misses
-system.cpu.l2cache.InvalidateReq_misses::cpu.data       479953                       # number of InvalidateReq misses
-system.cpu.l2cache.InvalidateReq_misses::total       479953                       # number of InvalidateReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker         2378                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker         2471                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        71004                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       564843                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        640696                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker         2378                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker         2471                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        71004                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       564843                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       640696                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    324181000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    343851000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    668032000                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data   1328369000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total   1328369000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       157000                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::total       157000                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  44644302500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  44644302500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   9404933500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total   9404933500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  29984552500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  29984552500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data       542500                       # number of InvalidateReq miss cycles
-system.cpu.l2cache.InvalidateReq_miss_latency::total       542500                       # number of InvalidateReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    324181000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    343851000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   9404933500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  74628855000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  84701820500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker    324181000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    343851000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   9404933500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  74628855000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  84701820500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       314511                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       244991                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       559502                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      7310347                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total      7310347                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks     13314767                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total     13314767                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data        42263                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total        42263                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      1930243                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      1930243                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     13316843                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total     13316843                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      6218392                       # number of ReadSharedReq accesses(hits+misses)
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-system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1221988                       # number of InvalidateReq accesses(hits+misses)
-system.cpu.l2cache.InvalidateReq_accesses::total      1221988                       # number of InvalidateReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker       314511                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker       244991                       # number of demand (read+write) accesses
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-system.cpu.l2cache.demand_accesses::cpu.data      8148635                       # number of demand (read+write) accesses
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-system.cpu.l2cache.overall_accesses::cpu.dtb.walker       314511                       # number of overall (read+write) accesses
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-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.007561                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.010086                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.008667                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.787095                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.787095                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          229                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          779                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5781                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56275                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004135                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.962784                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        391701839                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       391701839                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
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+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.129833                       # miss rate for UpgradeReq accesses
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 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.176170                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.176170                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005332                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005332                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.036150                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.036150                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.392764                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::total     0.392764                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.007561                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.010086                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005332                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.069317                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.029090                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.007561                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.010086                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005332                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.069317                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.029090                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 136325.063078                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 139154.593282                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 137766.962260                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 39932.932512                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 39932.932512                       # average UpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        78500                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        78500                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 131287.465079                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 131287.465079                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132456.389781                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132456.389781                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 133387.394180                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 133387.394180                       # average ReadSharedReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data     1.130319                       # average InvalidateReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::total     1.130319                       # average InvalidateReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136325.063078                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 139154.593282                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132456.389781                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 132123.182902                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 132202.823960                       # average overall miss latency
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-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 139154.593282                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132456.389781                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 132123.182902                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 132202.823960                       # average overall miss latency
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+system.cpu.l2cache.InvalidateReq_miss_rate::total     0.413880                       # miss rate for InvalidateReq accesses
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+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 17532.229525                       # average UpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 63166.666667                       # average SCUpgradeReq miss latency
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+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83099.278415                       # average ReadCleanReq miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83046.228645                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 83088.416827                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.writebacks::writebacks       876332                       # number of writebacks
-system.cpu.l2cache.writebacks::total           876332                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         2378                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         2471                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         4849                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        33265                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total        33265                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       340050                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       340050                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        71004                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        71004                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       224793                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       224793                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       479953                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::total       479953                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         2378                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         2471                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        71004                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       564843                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       640696                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         2378                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         2471                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        71004                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       564843                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       640696                       # number of overall MSHR misses
+system.cpu.l2cache.writebacks::writebacks      1123249                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1123249                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         4188                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         4011                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         8199                       # number of ReadReq MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            1                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total            1                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         3956                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         3956                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       524003                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       524003                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        78577                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        78577                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       278865                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       278865                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       510258                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::total       510258                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         4188                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         4011                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        78577                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       802868                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       889644                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         4188                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         4011                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        78577                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       802868                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       889644                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        43125                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33702                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total        76827                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        33708                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33708                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33706                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::total        76831                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        33710                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33710                       # number of WriteReq MSHR uncacheable
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        43125                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67410                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total       110535                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    300401000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    319141000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    619542000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   2260005000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   2260005000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       137000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       137000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  41243802500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  41243802500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   8694893500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   8694893500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  27736359527                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  27736359527                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  32474021500                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  32474021500                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    300401000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    319141000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   8694893500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  68980162027                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  78294597527                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    300401000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    319141000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   8694893500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  68980162027                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  78294597527                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   4897724500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5777547500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  10675272000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   4897724500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5777547500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  10675272000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.007561                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.010086                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.008667                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.787095                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.787095                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67416                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total       110541                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    318149500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    314120500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    632270000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     75426500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     75426500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       159500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       159500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  37807398500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  37807398500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   5743922000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   5743922000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  20839044573                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  20839044573                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data   9521744500                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total   9521744500                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    318149500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    314120500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   5743922000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  58646443073                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  65022635073                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    318149500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    314120500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   5743922000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  58646443073                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  65022635073                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   2724311500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5810947000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   8535258500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   2724311500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5810947000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   8535258500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.011781                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.016831                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.013808                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.129833                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.129833                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.176170                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.176170                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005332                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005332                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.036150                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.036150                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.392764                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.392764                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.007561                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.010086                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005332                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.069317                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.029090                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.007561                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.010086                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005332                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.069317                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.029090                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126325.063078                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 129154.593282                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127766.962260                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 67939.425823                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 67939.425823                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        68500                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        68500                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 121287.465079                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 121287.465079                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122456.389781                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122456.389781                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 123386.224335                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 123386.224335                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 67660.836582                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 67660.836582                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126325.063078                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 129154.593282                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122456.389781                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 122122.717334                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 122202.413511                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126325.063078                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 129154.593282                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122456.389781                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 122122.717334                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 122202.413511                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113570.423188                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171430.404724                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138952.087157                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113570.423188                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85707.573060                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 96578.205998                       # average overall mshr uncacheable latency
-system.cpu.toL2Bus.snoop_filter.tot_requests     45899412                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests     23211953                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1753                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         2701                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2701                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.242500                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.242500                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005697                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005697                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.040703                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.040703                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.413880                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.413880                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.011781                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.016831                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005697                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.089088                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.038021                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.011781                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.016831                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005697                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.089088                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.038021                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75966.929322                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 78314.759412                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77115.501890                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19066.354904                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19066.354904                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 53166.666667                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 53166.666667                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72151.110776                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72151.110776                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73099.278415                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73099.278415                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74728.074778                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74728.074778                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 18660.647163                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 18660.647163                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75966.929322                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 78314.759412                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73099.278415                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73046.183274                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73088.375882                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75966.929322                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 78314.759412                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73099.278415                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73046.183274                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73088.375882                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63172.440580                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172400.967187                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 111091.336830                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63172.440580                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86195.369052                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 77213.509015                       # average overall mshr uncacheable latency
+system.cpu.toL2Bus.snoop_filter.tot_requests     48633709                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests     24595755                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1745                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         2030                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2030                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadReq         979874                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      20515947                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         33708                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        33708                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      8293329                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean     13316326                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      2221598                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq        42266                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp        42268                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1930243                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1930243                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq     13316843                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      6227282                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq      1328652                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateResp      1221988                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     40036262                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     28331504                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       601742                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       860807                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          69830315                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1704695316                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    989618926                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      1959928                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2516088                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         2698790258                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     1604803                       # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic              65712840                       # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples     25003730                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.019507                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.138299                       # Request fanout histogram
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadReq        1068832                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      21713957                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         33710                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        33710                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      9029679                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean     13792548                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      2522886                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq        30473                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq            3                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp        30476                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      2160837                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      2160837                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq     13793065                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      6853863                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq      1261524                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateResp      1232866                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     41464928                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     30930790                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       605749                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       980040                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          73981507                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1765651732                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1083027398                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      1906472                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2843832                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         2853429434                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1738629                       # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic              75129128                       # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples     26510522                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.020074                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.140252                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           24515981     98.05%     98.05% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             487749      1.95%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           25978363     97.99%     97.99% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             532159      2.01%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       25003730                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    43858380000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       26510522                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    46319770000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy      1560894                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy      1608386                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy   20018389500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy   20732722500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   12905646976                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   14200291468                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy     356751000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy     367440000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy     546296000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy     624561000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq                40338                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40338                       # Transaction distribution
+system.iobus.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.iobus.trans_dist::ReadReq                40312                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40312                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
 system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
@@ -1312,11 +1298,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231034                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231034                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230982                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230982                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353818                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353766                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
@@ -1331,16 +1317,16 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334568                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334568                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334360                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334360                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492488                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             42150000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7492280                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             42148500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               322000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               320500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer3.occupancy                11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
@@ -1348,9 +1334,9 @@ system.iobus.reqLayer4.occupancy                11000                       # La
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy               11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy               11000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy               11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy               11000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy               11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer15.occupancy               11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
@@ -1358,75 +1344,75 @@ system.iobus.reqLayer16.occupancy               17000                       # La
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy               11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            25729000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            25722000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            38601000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            38610500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           566926866                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           568931558                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147794000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147742000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements               115499                       # number of replacements
-system.iocache.tags.tagsinuse               10.446740                       # Cycle average of tags in use
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.replacements               115472                       # number of replacements
+system.iocache.tags.tagsinuse               10.457340                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115515                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115488                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13171623640000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     5.847996                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     4.598744                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.365500                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.287422                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.652921                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13153794616000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.511175                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.946165                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.219448                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.434135                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.653584                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1040010                       # Number of tag accesses
-system.iocache.tags.data_accesses             1040010                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.tag_accesses              1039776                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039776                       # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8853                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8890                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8827                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8864                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide       115517                       # number of demand (read+write) misses
-system.iocache.demand_misses::total            115557                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide       115491                       # number of demand (read+write) misses
+system.iocache.demand_misses::total            115531                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide       115517                       # number of overall misses
-system.iocache.overall_misses::total           115557                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5070500                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1655174117                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1660244617                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide       115491                       # number of overall misses
+system.iocache.overall_misses::total           115531                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5086000                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1606262152                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1611348152                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  13409764249                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  13409764249                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5421500                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide  15064938366                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  15070359866                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5421500                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide  15064938366                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  15070359866                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  12771737406                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  12771737406                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5437000                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide  14377999558                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  14383436558                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5437000                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide  14377999558                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total  14383436558                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8853                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8890                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8827                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8864                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide       115517                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total          115557                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide       115491                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total          115531                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide       115517                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total         115557                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide       115491                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total         115531                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -1440,53 +1426,53 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137040.540541                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 186961.947024                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 186754.175141                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 181971.468449                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 181785.666968                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125719.682826                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 125719.682826                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet 135537.500000                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 130413.171793                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 130414.945577                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet 135537.500000                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 130413.171793                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 130414.945577                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         33045                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 119738.031632                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 119738.031632                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet       135925                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 124494.545532                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 124498.503068                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet       135925                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 124494.545532                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 124498.503068                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         31144                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3376                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3368                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.788211                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.247031                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks          106631                       # number of writebacks
-system.iocache.writebacks::total               106631                       # number of writebacks
+system.iocache.writebacks::writebacks          106630                       # number of writebacks
+system.iocache.writebacks::total               106630                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8853                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8890                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8827                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8864                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide       115517                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total       115557                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide       115491                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total       115531                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide       115517                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total       115557                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3220500                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1212524117                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1215744617                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide       115491                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total       115531                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3236000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1164912152                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1168148152                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8071395398                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   8071395398                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3421500                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   9283919515                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   9287341015                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3421500                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   9283919515                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   9287341015                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7431704095                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   7431704095                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3437000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   8596616247                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   8600053247                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3437000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   8596616247                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   8600053247                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -1500,89 +1486,95 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87040.540541                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136961.947024                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 136754.175141                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 131971.468449                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 131785.666968                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75671.223637                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75671.223637                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85537.500000                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 80368.426422                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 80370.215694                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85537.500000                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 80368.426422                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 80370.215694                       # average overall mshr miss latency
-system.membus.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq               76827                       # Transaction distribution
-system.membus.trans_dist::ReadResp             386363                       # Transaction distribution
-system.membus.trans_dist::WriteReq              33708                       # Transaction distribution
-system.membus.trans_dist::WriteResp             33708                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       982963                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           160860                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            33836                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp               7                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            339489                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           339489                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        309536                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        586610                       # Transaction distribution
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69673.967740                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69673.967740                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85925                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 74435.378055                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 74439.356078                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85925                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 74435.378055                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 74439.356078                       # average overall mshr miss latency
+system.membus.snoop_filter.tot_requests       2941993                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests      1455813                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests         3308                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
+system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadReq               76831                       # Transaction distribution
+system.membus.trans_dist::ReadResp             451336                       # Transaction distribution
+system.membus.trans_dist::WriteReq              33710                       # Transaction distribution
+system.membus.trans_dist::WriteResp             33710                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1229879                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           192681                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4527                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp               8                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            523443                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           523443                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        374505                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        616914                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6930                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      2913100                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3042792                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237470                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       237470                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                3280262                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6942                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3690757                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3820461                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237403                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       237403                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4057864                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13860                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     97205216                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     97375042                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7234880                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7234880                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               104609922                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             3136                       # Total snoops (count)
-system.membus.snoopTraffic                     200256                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples           2523850                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13884                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    128940576                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    129110426                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7233920                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7233920                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               136344346                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             3126                       # Total snoops (count)
+system.membus.snoopTraffic                     199552                       # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples           1629933                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.019638                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.138754                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 2523850    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 1597924     98.04%     98.04% # Request fanout histogram
+system.membus.snoop_fanout::1                   32009      1.96%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2523850                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           106906000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             1629933                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           106906500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               41500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5727500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5804000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          6514212892                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          8036011189                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         3604018785                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         4923968289                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           44774812                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           44661763                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
 system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
 system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
 system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
 system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
 system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
@@ -1625,28 +1617,28 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
 system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500                       # Cumulative time (in ticks) in various power states
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt
index 233e6de0a..2d1d5d137 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                 51.111167                       # Nu
 sim_ticks                                51111167268500                       # Number of ticks simulated
 final_tick                               51111167268500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 810187                       # Simulator instruction rate (inst/s)
-host_op_rate                                   952145                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            42160127212                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 675168                       # Number of bytes of host memory used
-host_seconds                                  1212.31                       # Real time elapsed on the host
+host_inst_rate                                 933162                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1096667                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            48559439795                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 681072                       # Number of bytes of host memory used
+host_seconds                                  1052.55                       # Real time elapsed on the host
 sim_insts                                   982198023                       # Number of instructions simulated
 sim_ops                                    1154295627                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -16,60 +16,60 @@ system.clk_domain.clock                          1000                       # Cl
 system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu0.dtb.walker       206336                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker       188224                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          3277940                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         38030472                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          3278004                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         38031624                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.dtb.walker       207616                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.itb.walker       185152                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.inst          2205440                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         36882176                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         36882368                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide        436800                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             81620156                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      3277940                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::total             81621564                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      3278004                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::cpu1.inst      2205440                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5483380                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks    103277952                       # Number of bytes written to this memory
+system.physmem.bytes_inst_read::total         5483444                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks    103278592                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         103298532                       # Number of bytes written to this memory
+system.physmem.bytes_written::total         103299172                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu0.dtb.walker         3224                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker         2941                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             91625                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            594239                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             91626                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            594257                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.dtb.walker         3244                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.itb.walker         2893                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.inst             34460                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            576284                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            576287                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide           6825                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1315735                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1613718                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total               1315757                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1613728                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1616291                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1616301                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu0.dtb.walker          4037                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker          3683                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               64134                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              744074                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               64135                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              744096                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.dtb.walker          4062                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.itb.walker          3623                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.inst               43150                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              721607                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              721611                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide             8546                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1596914                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          64134                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1596942                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          64135                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::cpu1.inst          43150                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             107283                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2020653                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             107285                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2020666                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data                403                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2021056                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2020653                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2021069                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2020666                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.dtb.walker         4037                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker         3683                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              64134                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             744476                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              64135                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             744499                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.dtb.walker         4062                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.itb.walker         3623                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.inst              43150                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             721607                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             721611                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide            8546                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3617970                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3618010                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
@@ -338,9 +338,9 @@ system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51111167268500
 system.cpu0.dcache.ReadReq_hits::cpu0.data     85600060                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::cpu1.data     85509890                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::total      171109950                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     79543301                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data     79530135                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total     159073436                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     79551757                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data     79538240                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total     159089997                       # number of WriteReq hits
 system.cpu0.dcache.SoftPFReq_hits::cpu0.data       209327                       # number of SoftPFReq hits
 system.cpu0.dcache.SoftPFReq_hits::cpu1.data       214988                       # number of SoftPFReq hits
 system.cpu0.dcache.SoftPFReq_hits::total       424315                       # number of SoftPFReq hits
@@ -353,18 +353,18 @@ system.cpu0.dcache.LoadLockedReq_hits::total      4303549
 system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2274909                       # number of StoreCondReq hits
 system.cpu0.dcache.StoreCondReq_hits::cpu1.data      2280735                       # number of StoreCondReq hits
 system.cpu0.dcache.StoreCondReq_hits::total      4555644                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    165287591                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data    165232078                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       330519669                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    165496918                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data    165447066                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      330943984                       # number of overall hits
+system.cpu0.dcache.demand_hits::cpu0.data    165296047                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data    165240183                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       330536230                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    165505374                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data    165455171                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      330960545                       # number of overall hits
 system.cpu0.dcache.ReadReq_misses::cpu0.data      3016323                       # number of ReadReq misses
 system.cpu0.dcache.ReadReq_misses::cpu1.data      2986728                       # number of ReadReq misses
 system.cpu0.dcache.ReadReq_misses::total      6003051                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1295379                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data      1272732                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      2568111                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1286923                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data      1264627                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      2551550                       # number of WriteReq misses
 system.cpu0.dcache.SoftPFReq_misses::cpu0.data       788168                       # number of SoftPFReq misses
 system.cpu0.dcache.SoftPFReq_misses::cpu1.data       797714                       # number of SoftPFReq misses
 system.cpu0.dcache.SoftPFReq_misses::total      1585882                       # number of SoftPFReq misses
@@ -376,12 +376,12 @@ system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       127105
 system.cpu0.dcache.LoadLockedReq_misses::total       253898                       # number of LoadLockedReq misses
 system.cpu0.dcache.StoreCondReq_misses::cpu1.data            1                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      5073259                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data      4744675                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       9817934                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      5861427                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data      5542389                       # number of overall misses
-system.cpu0.dcache.overall_misses::total     11403816                       # number of overall misses
+system.cpu0.dcache.demand_misses::cpu0.data      5064803                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data      4736570                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       9801373                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      5852971                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data      5534284                       # number of overall misses
+system.cpu0.dcache.overall_misses::total     11387255                       # number of overall misses
 system.cpu0.dcache.ReadReq_accesses::cpu0.data     88616383                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.ReadReq_accesses::cpu1.data     88496618                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.ReadReq_accesses::total    177113001                       # number of ReadReq accesses(hits+misses)
@@ -409,9 +409,9 @@ system.cpu0.dcache.overall_accesses::total    342347800                       #
 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.034038                       # miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.033750                       # miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_miss_rate::total     0.033894                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.016024                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.015751                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.015888                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.015920                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.015651                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.015785                       # miss rate for WriteReq accesses
 system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.790147                       # miss rate for SoftPFReq accesses
 system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.787709                       # miss rate for SoftPFReq accesses
 system.cpu0.dcache.SoftPFReq_miss_rate::total     0.788919                       # miss rate for SoftPFReq accesses
@@ -423,20 +423,20 @@ system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.055708
 system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.055711                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000000                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.029779                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.027914                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.028848                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.034206                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.032414                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.033311                       # miss rate for overall accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.029730                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.027866                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.028799                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.034156                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.032366                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.033262                       # miss rate for overall accesses
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks      8916863                       # number of writebacks
-system.cpu0.dcache.writebacks::total          8916863                       # number of writebacks
+system.cpu0.dcache.writebacks::writebacks      8918956                       # number of writebacks
+system.cpu0.dcache.writebacks::total          8918956                       # number of writebacks
 system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 system.cpu0.icache.tags.replacements         14265255                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          511.984599                       # Cycle average of tags in use
@@ -829,138 +829,138 @@ system.iocache.avg_blocked_cycles::no_targets          nan
 system.iocache.writebacks::writebacks          106631                       # number of writebacks
 system.iocache.writebacks::total               106631                       # number of writebacks
 system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements                  1725785                       # number of replacements
-system.l2c.tags.tagsinuse                65319.566840                       # Cycle average of tags in use
-system.l2c.tags.total_refs                   46977185                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1788801                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    26.261828                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                395986000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   37198.027902                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   157.533597                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   243.219072                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3426.787378                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     9571.465720                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   153.009111                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   207.682961                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     2648.640796                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data    11713.200303                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.567597                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002404                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.003711                       # Average percentage of cache occupancy
+system.l2c.tags.replacements                  1725813                       # number of replacements
+system.l2c.tags.tagsinuse                65403.901917                       # Cycle average of tags in use
+system.l2c.tags.total_refs                   49468109                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1788889                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    27.652978                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle                395496000                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks    9615.108088                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker   224.707200                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   268.802991                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3426.785629                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data    22887.229719                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   209.300949                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   228.038258                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     2648.603044                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data    25895.326039                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.146715                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.003429                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.004102                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.inst       0.052289                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.146049                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002335                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.003169                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.040415                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.178729                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.996697                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023          315                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        62701                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          315                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          136                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          608                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2778                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         4924                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        54255                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.004807                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.956741                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                426273955                       # Number of tag accesses
-system.l2c.tags.data_accesses               426273955                       # Number of data accesses
+system.l2c.tags.occ_percent::cpu0.data       0.349231                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.003194                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.003480                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.040414                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.395131                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.997984                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023          371                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        62705                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          371                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0          110                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          329                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         1444                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         5122                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        55700                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023     0.005661                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.956802                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                423190040                       # Number of tag accesses
+system.l2c.tags.data_accesses               423190040                       # Number of data accesses
 system.l2c.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.l2c.ReadReq_hits::cpu0.dtb.walker       280712                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker       145885                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker       277418                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker       142199                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                 846214                       # number of ReadReq hits
-system.l2c.WritebackDirty_hits::writebacks      8916863                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total         8916863                       # number of WritebackDirty hits
+system.l2c.ReadReq_hits::cpu0.dtb.walker       265559                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker       135827                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker       262154                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker       132135                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                 795675                       # number of ReadReq hits
+system.l2c.WritebackDirty_hits::writebacks      8918956                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total         8918956                       # number of WritebackDirty hits
 system.l2c.WritebackClean_hits::writebacks     14263678                       # number of WritebackClean hits
 system.l2c.WritebackClean_hits::total        14263678                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data            5752                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data            5452                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               11204                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           852175                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data           837197                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total              1689372                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst       7090160                       # number of ReadCleanReq hits
+system.l2c.UpgradeReq_hits::cpu0.data           15680                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data           15013                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total               30693                       # number of UpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data           852174                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data           837196                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total              1689370                       # number of ReadExReq hits
+system.l2c.ReadCleanReq_hits::cpu0.inst       7090159                       # number of ReadCleanReq hits
 system.l2c.ReadCleanReq_hits::cpu1.inst       7092615                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total          14182775                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data      3753750                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data      3744981                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total          7498731                       # number of ReadSharedReq hits
-system.l2c.InvalidateReq_hits::cpu0.data       340284                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::cpu1.data       354276                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::total           694560                       # number of InvalidateReq hits
-system.l2c.demand_hits::cpu0.dtb.walker        280712                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker        145885                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst             7090160                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data             4605925                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker        277418                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker        142199                       # number of demand (read+write) hits
+system.l2c.ReadCleanReq_hits::total          14182774                       # number of ReadCleanReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data      3753733                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data      3744979                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total          7498712                       # number of ReadSharedReq hits
+system.l2c.InvalidateReq_hits::cpu0.data       340283                       # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::cpu1.data       354274                       # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::total           694557                       # number of InvalidateReq hits
+system.l2c.demand_hits::cpu0.dtb.walker        265559                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker        135827                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst             7090159                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data             4605907                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker        262154                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker        132135                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu1.inst             7092615                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data             4582178                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                24217092                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker       280712                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker       145885                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst            7090160                       # number of overall hits
-system.l2c.overall_hits::cpu0.data            4605925                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker       277418                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker       142199                       # number of overall hits
+system.l2c.demand_hits::cpu1.data             4582175                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                24166531                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker       265559                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker       135827                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst            7090159                       # number of overall hits
+system.l2c.overall_hits::cpu0.data            4605907                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker       262154                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker       132135                       # number of overall hits
 system.l2c.overall_hits::cpu1.inst            7092615                       # number of overall hits
-system.l2c.overall_hits::cpu1.data            4582178                       # number of overall hits
-system.l2c.overall_hits::total               24217092                       # number of overall hits
+system.l2c.overall_hits::cpu1.data            4582175                       # number of overall hits
+system.l2c.overall_hits::total               24166531                       # number of overall hits
 system.l2c.ReadReq_misses::cpu0.dtb.walker         3224                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu0.itb.walker         2941                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu1.dtb.walker         3244                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu1.itb.walker         2893                       # number of ReadReq misses
 system.l2c.ReadReq_misses::total                12302                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data         20291                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         19639                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             39930                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          1907                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data          1973                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              3880                       # number of UpgradeReq misses
 system.l2c.SCUpgradeReq_misses::cpu1.data            1                       # number of SCUpgradeReq misses
 system.l2c.SCUpgradeReq_misses::total               1                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         417161                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data         410444                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             827605                       # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst        48524                       # number of ReadCleanReq misses
+system.l2c.ReadExReq_misses::cpu0.data         417162                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data         410445                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             827607                       # number of ReadExReq misses
+system.l2c.ReadCleanReq_misses::cpu0.inst        48525                       # number of ReadCleanReq misses
 system.l2c.ReadCleanReq_misses::cpu1.inst        34473                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::total           82997                       # number of ReadCleanReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       177534                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data       166566                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         344100                       # number of ReadSharedReq misses
-system.l2c.InvalidateReq_misses::cpu0.data       421273                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::cpu1.data       130939                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::total         552212                       # number of InvalidateReq misses
+system.l2c.ReadCleanReq_misses::total           82998                       # number of ReadCleanReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data       177551                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data       166568                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total         344119                       # number of ReadSharedReq misses
+system.l2c.InvalidateReq_misses::cpu0.data       421274                       # number of InvalidateReq misses
+system.l2c.InvalidateReq_misses::cpu1.data       130941                       # number of InvalidateReq misses
+system.l2c.InvalidateReq_misses::total         552215                       # number of InvalidateReq misses
 system.l2c.demand_misses::cpu0.dtb.walker         3224                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.itb.walker         2941                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             48524                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            594695                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst             48525                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            594713                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu1.dtb.walker         3244                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu1.itb.walker         2893                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu1.inst             34473                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            577010                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1267004                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data            577013                       # number of demand (read+write) misses
+system.l2c.demand_misses::total               1267026                       # number of demand (read+write) misses
 system.l2c.overall_misses::cpu0.dtb.walker         3224                       # number of overall misses
 system.l2c.overall_misses::cpu0.itb.walker         2941                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            48524                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           594695                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst            48525                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           594713                       # number of overall misses
 system.l2c.overall_misses::cpu1.dtb.walker         3244                       # number of overall misses
 system.l2c.overall_misses::cpu1.itb.walker         2893                       # number of overall misses
 system.l2c.overall_misses::cpu1.inst            34473                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           577010                       # number of overall misses
-system.l2c.overall_misses::total              1267004                       # number of overall misses
-system.l2c.ReadReq_accesses::cpu0.dtb.walker       283936                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker       148826                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker       280662                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker       145092                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total             858516                       # number of ReadReq accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::writebacks      8916863                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total      8916863                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.overall_misses::cpu1.data           577013                       # number of overall misses
+system.l2c.overall_misses::total              1267026                       # number of overall misses
+system.l2c.ReadReq_accesses::cpu0.dtb.walker       268783                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker       138768                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker       265398                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker       135028                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total             807977                       # number of ReadReq accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::writebacks      8918956                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total      8918956                       # number of WritebackDirty accesses(hits+misses)
 system.l2c.WritebackClean_accesses::writebacks     14263678                       # number of WritebackClean accesses(hits+misses)
 system.l2c.WritebackClean_accesses::total     14263678                       # number of WritebackClean accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        26043                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data        25091                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           51134                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data        17587                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data        16986                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           34573                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::cpu1.data            1                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::total             1                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu0.data      1269336                       # number of ReadExReq accesses(hits+misses)
@@ -975,122 +975,122 @@ system.l2c.ReadSharedReq_accesses::total      7842831                       # nu
 system.l2c.InvalidateReq_accesses::cpu0.data       761557                       # number of InvalidateReq accesses(hits+misses)
 system.l2c.InvalidateReq_accesses::cpu1.data       485215                       # number of InvalidateReq accesses(hits+misses)
 system.l2c.InvalidateReq_accesses::total      1246772                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker       283936                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker       148826                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.dtb.walker       268783                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker       138768                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu0.inst         7138684                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu0.data         5200620                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker       280662                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker       145092                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker       265398                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker       135028                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu1.inst         7127088                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu1.data         5159188                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total            25484096                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker       283936                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker       148826                       # number of overall (read+write) accesses
+system.l2c.demand_accesses::total            25433557                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker       268783                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker       138768                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu0.inst        7138684                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu0.data        5200620                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker       280662                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker       145092                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker       265398                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker       135028                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu1.inst        7127088                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu1.data        5159188                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total           25484096                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.011355                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.019761                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.011558                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.019939                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.014329                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.779135                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.782711                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.780889                       # miss rate for UpgradeReq accesses
+system.l2c.overall_accesses::total           25433557                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.011995                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.021194                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.012223                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.021425                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.015226                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.108432                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.116154                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.112226                       # miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.328645                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.328976                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.328809                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.328646                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.328977                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.328810                       # miss rate for ReadExReq accesses
 system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.006797                       # miss rate for ReadCleanReq accesses
 system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.004837                       # miss rate for ReadCleanReq accesses
 system.l2c.ReadCleanReq_miss_rate::total     0.005818                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.045159                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.042583                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.043874                       # miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu0.data     0.553173                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu1.data     0.269858                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::total     0.442913                       # miss rate for InvalidateReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.011355                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.019761                       # miss rate for demand accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.045164                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.042584                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.043877                       # miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu0.data     0.553175                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu1.data     0.269862                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::total     0.442916                       # miss rate for InvalidateReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.011995                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.021194                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu0.inst       0.006797                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.114351                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.011558                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.019939                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.114354                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.012223                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.021425                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu1.inst       0.004837                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.111841                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.049717                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.011355                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.019761                       # miss rate for overall accesses
+system.l2c.demand_miss_rate::cpu1.data       0.111842                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.049817                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.011995                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.021194                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu0.inst      0.006797                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.114351                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.011558                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.019939                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.114354                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.012223                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.021425                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu1.inst      0.004837                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.111841                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.049717                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.111842                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.049817                       # miss rate for overall accesses
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.writebacks::writebacks             1507087                       # number of writebacks
-system.l2c.writebacks::total                  1507087                       # number of writebacks
-system.membus.snoop_filter.tot_requests       3814674                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests      1911370                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.l2c.writebacks::writebacks             1507097                       # number of writebacks
+system.l2c.writebacks::total                  1507097                       # number of writebacks
+system.membus.snoop_filter.tot_requests       3778676                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests      1875347                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests         2861                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadReq               76679                       # Transaction distribution
-system.membus.trans_dist::ReadResp             524928                       # Transaction distribution
+system.membus.trans_dist::ReadResp             524948                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33606                       # Transaction distribution
 system.membus.trans_dist::WriteResp             33606                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1613718                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           226292                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            40497                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1613728                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           226309                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4447                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           40498                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            827048                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           827048                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        448249                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        658869                       # Transaction distribution
-system.membus.trans_dist::InvalidateResp       658869                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4448                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            827050                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           827050                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        448269                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        658872                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp       658872                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122480                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6654                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5534223                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      5663415                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5462200                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      5591392                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       346493                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       346493                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                6009908                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5937885                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155610                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13308                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    177699296                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    177868346                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    177701344                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    177870394                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7390784                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      7390784                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               185259130                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               185261178                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
 system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples           3924959                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.009320                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.096090                       # Request fanout histogram
+system.membus.snoop_fanout::samples           3888961                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.009406                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.096529                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 3888378     99.07%     99.07% # Request fanout histogram
-system.membus.snoop_fanout::1                   36581      0.93%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 3852380     99.06%     99.06% # Request fanout histogram
+system.membus.snoop_fanout::1                   36581      0.94%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3924959                       # Request fanout histogram
+system.membus.snoop_fanout::total             3888961                       # Request fanout histogram
 system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
@@ -1171,23 +1171,23 @@ system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500
 system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests     52404582                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests     26532237                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.tot_requests     52388021                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests     26515676                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_requests         1744                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops           2693                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops         2693                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops           2694                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops         2694                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
 system.toL2Bus.trans_dist::ReadReq            1320370                       # Transaction distribution
 system.toL2Bus.trans_dist::ReadResp          23428973                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             33606                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            33606                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty      8916863                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty      8918956                       # Transaction distribution
 system.toL2Bus.trans_dist::WritebackClean     14265255                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         2689192                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           51134                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         2687099                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           34573                       # Transaction distribution
 system.toL2Bus.trans_dist::SCUpgradeReq             1                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          51135                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          34574                       # Transaction distribution
 system.toL2Bus.trans_dist::ReadExReq          2516977                       # Transaction distribution
 system.toL2Bus.trans_dist::ReadExResp         2516977                       # Transaction distribution
 system.toL2Bus.trans_dist::ReadCleanReq      14265772                       # Transaction distribution
@@ -1195,27 +1195,27 @@ system.toL2Bus.trans_dist::ReadSharedReq      7842831                       # Tr
 system.toL2Bus.trans_dist::InvalidateReq      1246772                       # Transaction distribution
 system.toL2Bus.trans_dist::InvalidateResp      1246772                       # Transaction distribution
 system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     42883049                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     35055805                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     35022683                       # Packet count per connected master and slave (bytes)
 system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       830232                       # Packet count per connected master and slave (bytes)
 system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1657150                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              80426236                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              80393114                       # Packet count per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   1826158228                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1233896614                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1234030566                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      3320928                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      6628600                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total             3070004370                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         1762480                       # Total snoops (count)
-system.toL2Bus.snoopTraffic                  96494080                       # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples         54910458                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.011218                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.105318                       # Request fanout histogram
+system.toL2Bus.pkt_size::total             3070138322                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         1762508                       # Total snoops (count)
+system.toL2Bus.snoopTraffic                  96494720                       # Total snoop traffic (bytes)
+system.toL2Bus.snoop_fanout::samples         54893925                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.011221                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.105334                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0               54294485     98.88%     98.88% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 615973      1.12%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0               54277951     98.88%     98.88% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 615974      1.12%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           54910458                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::total           54893925                       # Request fanout histogram
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
index aa5265b3e..7b0e2ea39 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
@@ -1,193 +1,193 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.316261                       # Number of seconds simulated
-sim_ticks                                51316261201000                       # Number of ticks simulated
-final_tick                               51316261201000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.316276                       # Number of seconds simulated
+sim_ticks                                51316275690000                       # Number of ticks simulated
+final_tick                               51316275690000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 303672                       # Simulator instruction rate (inst/s)
-host_op_rate                                   356843                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            18193830206                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 686184                       # Number of bytes of host memory used
-host_seconds                                  2820.53                       # Real time elapsed on the host
-sim_insts                                   856517636                       # Number of instructions simulated
-sim_ops                                    1006486660                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 326587                       # Simulator instruction rate (inst/s)
+host_op_rate                                   383768                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            19561029283                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 692584                       # Number of bytes of host memory used
+host_seconds                                  2623.39                       # Real time elapsed on the host
+sim_insts                                   856765339                       # Number of instructions simulated
+sim_ops                                    1006773904                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.dtb.walker        89408                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker        88064                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          2284980                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         19216392                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker        19648                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker        18624                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           651264                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          5282880                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker        33920                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.itb.walker        30784                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst          1695808                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          7120960                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.dtb.walker        74240                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.itb.walker        63168                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst          1609856                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.data         11459776                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        417920                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             50157692                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      2284980                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       651264                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst      1695808                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst      1609856                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         6241908                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     69878272                       # Number of bytes written to this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu0.dtb.walker        86272                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker        86656                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          2383476                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         19569480                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker        22528                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker        19008                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           645440                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          5197376                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker        31936                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.itb.walker        29376                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst          1640192                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          6901376                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.dtb.walker        81152                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.itb.walker        66816                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst          1624448                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.data         11589312                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        437504                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             50412348                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      2383476                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       645440                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst      1640192                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst      1624448                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         6293556                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     70023744                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          69898852                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         1397                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         1376                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             76110                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            300269                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker          307                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker          291                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             10176                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             82545                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker          530                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.itb.walker          481                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst             26497                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data            111265                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.dtb.walker         1160                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.itb.walker          987                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst             25154                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.data            179059                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6530                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                824134                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1091848                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          70044324                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         1348                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         1354                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             77649                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            305786                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker          352                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker          297                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             10085                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             81209                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker          499                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.itb.walker          459                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst             25628                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data            107834                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.dtb.walker         1268                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.itb.walker         1044                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst             25382                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.data            181083                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6836                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                828113                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1094121                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1094421                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          1742                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          1716                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               44527                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              374470                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           383                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker           363                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               12691                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              102947                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker           661                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.itb.walker           600                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst               33046                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data              138766                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.dtb.walker          1447                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.itb.walker          1231                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst               31371                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data              223317                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8144                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                  977423                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          44527                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          12691                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst          33046                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst          31371                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             121636                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1361718                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1096694                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          1681                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          1689                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               46447                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              381350                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           439                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker           370                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               12578                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              101281                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker           622                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.itb.walker           572                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst               31962                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data              134487                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.dtb.walker          1581                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.itb.walker          1302                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst               31656                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data              225841                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8526                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                  982385                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          46447                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          12578                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst          31962                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst          31656                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             122642                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1364552                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data                401                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1362119                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1361718                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         1742                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         1716                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              44527                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             374871                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          383                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker          363                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              12691                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             102947                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker          661                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.itb.walker          600                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst              33046                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data             138766                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.dtb.walker         1447                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.itb.walker         1231                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst              31371                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data             223317                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8144                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2339542                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        438929                       # Number of read requests accepted
-system.physmem.writeReqs                       487711                       # Number of write requests accepted
-system.physmem.readBursts                      438929                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     487711                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 28073280                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     18176                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  31211968                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  28091456                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               31213504                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      284                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_write::total                1364953                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1364552                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         1681                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         1689                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              46447                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             381751                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          439                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker          370                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              12578                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             101281                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker          622                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.itb.walker          572                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst              31962                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data             134487                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.dtb.walker         1581                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.itb.walker         1302                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst              31656                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data             225841                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8526                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2347339                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        435200                       # Number of read requests accepted
+system.physmem.writeReqs                       483804                       # Number of write requests accepted
+system.physmem.readBursts                      435200                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     483804                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 27836736                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     16064                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  30961600                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  27852800                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               30963456                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      251                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               25285                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               29259                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               26350                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               25668                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               27357                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               30719                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               26473                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               28031                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               25079                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               30131                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              27758                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              30805                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              27043                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              27394                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              24672                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              26621                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               26756                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               29816                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               28574                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               30074                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               31364                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               33348                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               29983                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               32184                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               30191                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               34064                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              29741                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              31916                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              29919                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              30461                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              29114                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              30182                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               27905                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               28763                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               27094                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               24985                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               26681                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               30728                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               26238                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               28208                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               24817                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               29447                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              28003                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              29718                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              26417                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              26875                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              23221                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25849                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               29439                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               30169                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               29222                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               30308                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               30582                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               32929                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               29622                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               32397                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               29255                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               32999                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              30308                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              31541                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              29215                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              29346                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              27349                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              29094                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           9                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51315260920500                       # Total gap between requests
+system.physmem.numWrRetry                          19                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51315275469000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  438929                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  435200                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 487711                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    342866                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     67593                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     19478                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      8245                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        94                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                        44                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                        61                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                        41                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                        89                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        20                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       30                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       13                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                       14                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        9                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        9                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        9                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        9                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        9                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        8                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 483804                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    339047                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     67972                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     19489                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      8325                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        61                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                        12                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                         5                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                         4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                        12                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                         2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
@@ -199,185 +199,191 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                       578                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                       575                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                       569                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                       568                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                       563                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                       564                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                       560                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                       555                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                       581                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                       572                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                       571                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                       567                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                       560                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                       559                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                       559                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                       556                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::8                       556                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                       554                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                      551                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                      549                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                       555                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                      554                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                      551                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::12                      549                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                      544                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                      543                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    10806                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    12800                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    21548                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    23833                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    26317                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    27236                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    28042                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    28569                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    29592                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    29655                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    30940                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    31802                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    30047                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    29665                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    30409                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    27749                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    27223                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    26642                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      679                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      528                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      429                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      404                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::38                      245                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::41                      278                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      215                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::44                      204                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::16                    12645                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    21314                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    23642                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    26112                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    26953                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    27836                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    28305                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    29478                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    29464                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    30830                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    31587                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    29857                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    29451                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    30076                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    27393                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    27014                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    26345                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      722                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      584                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      508                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      402                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      313                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      249                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      289                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      212                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      207                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      218                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      227                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      203                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::45                      176                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      211                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      222                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      193                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      206                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      189                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      190                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      178                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      177                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      115                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      107                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      116                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      102                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       75                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       72                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       74                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       18                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       279155                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      212.371879                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     133.666378                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     251.561006                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         134237     48.09%     48.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        73368     26.28%     74.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        25102      8.99%     83.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        12608      4.52%     87.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         8433      3.02%     90.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         5025      1.80%     92.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         3984      1.43%     94.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         2939      1.05%     95.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        13459      4.82%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         279155                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         26191                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        16.746211                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev       10.447790                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-15             9423     35.98%     35.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::16-31           15107     57.68%     93.66% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::32-47            1332      5.09%     98.74% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::48-63             231      0.88%     99.63% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::64-79              66      0.25%     99.88% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::80-95              23      0.09%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::96-111              3      0.01%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::112-127             2      0.01%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::128-143             1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::144-159             1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::256-271             1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::384-399             1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           26191                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         26191                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        18.620404                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.778521                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        9.884507                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-7                23      0.09%      0.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-15               48      0.18%      0.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23           24431     93.28%     93.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31             637      2.43%     95.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39             499      1.91%     97.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47             119      0.45%     98.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55              74      0.28%     98.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63              52      0.20%     98.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71             187      0.71%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79              21      0.08%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87              13      0.05%     99.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-95               5      0.02%     99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103              5      0.02%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111            20      0.08%     99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-119             7      0.03%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-127             6      0.02%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135            18      0.07%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-143             7      0.03%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-151             1      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-159             4      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-167             2      0.01%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183             4      0.02%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-191             1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::232-239             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrQLenPdf::46                      187                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      151                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      184                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      164                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      145                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      118                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      110                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      110                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      133                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      110                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      128                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      119                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      111                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       80                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       73                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       45                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       59                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       275230                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      213.631363                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     134.345796                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     252.466079                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         131747     47.87%     47.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        72284     26.26%     74.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        24873      9.04%     83.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        12745      4.63%     87.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         8355      3.04%     90.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         4904      1.78%     92.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         4003      1.45%     94.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         2900      1.05%     95.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        13419      4.88%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         275230                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         25971                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        16.744908                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev       10.064212                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-7              4094     15.76%     15.76% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::8-15             5177     19.93%     35.70% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::16-23           12484     48.07%     83.77% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::24-31            2573      9.91%     93.67% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::32-39             911      3.51%     97.18% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::40-47             410      1.58%     98.76% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::48-55             151      0.58%     99.34% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::56-63              87      0.33%     99.68% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::64-71              41      0.16%     99.83% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::72-79              17      0.07%     99.90% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::80-87              14      0.05%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::88-95               7      0.03%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::96-103              1      0.00%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::136-143             2      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::144-151             1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::208-215             1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           25971                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         25971                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        18.627508                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.774611                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        9.820731                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-7                27      0.10%      0.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-15               58      0.22%      0.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23           24184     93.12%     93.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31             657      2.53%     95.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39             512      1.97%     97.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47             109      0.42%     98.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55              61      0.23%     98.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63              50      0.19%     98.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71             187      0.72%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79              29      0.11%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87              13      0.05%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95               6      0.02%     99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103              4      0.02%     99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111            13      0.05%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119             7      0.03%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127             7      0.03%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135            17      0.07%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143             7      0.03%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151             5      0.02%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167             4      0.02%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175             1      0.00%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183             1      0.00%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191             1      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215             2      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231             1      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-239             1      0.00%     99.97% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::240-247             1      0.00%     99.98% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::248-255             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-263             2      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-311             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::488-495             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           26191                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     8271276046                       # Total ticks spent queuing
-system.physmem.totMemAccLat               16495869796                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2193225000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       18856.42                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::256-263             3      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-279             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::312-319             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           25971                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     8284996307                       # Total ticks spent queuing
+system.physmem.totMemAccLat               16440290057                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2174745000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       19048.20                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  37606.42                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           0.55                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           0.61                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        0.55                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.61                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  37798.20                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           0.54                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           0.60                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        0.54                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        0.60                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.01                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.00                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         7.58                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     320460                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    326715                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   73.06                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  66.99                       # Row buffer hit rate for writes
-system.physmem.avgGap                     55377774.45                       # Average gap between requests
-system.physmem.pageHitRate                      69.86                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 1063933920                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  578980875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1709237400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               1568801520                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3313030902480                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1175120467920                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           30458927805750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34952000129865                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              665.969400                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   48914934224726                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1693778580000                       # Time in different power states
+system.physmem.avgWrQLen                         8.48                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     317706                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    325786                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   73.04                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  67.34                       # Row buffer hit rate for writes
+system.physmem.avgGap                     55837923.96                       # Average gap between requests
+system.physmem.pageHitRate                      70.04                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 1063034280                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  578527125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1720625400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               1585448640                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3313031919600                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1176100438995                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29681595659250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34175675653290                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              667.640087                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   48913549174000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1693779100000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    115598736274                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    116961174250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 1046477880                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  569311875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1712123400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               1591410240                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3313030902480                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1175283684855                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29689572406500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34182806317230                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              667.621570                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   48914700007992                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1693778580000                       # Time in different power states
+system.physmem_1.actEnergy                 1017704520                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  553591500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1671906600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               1549413360                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3313031919600                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1173827506995                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29683698941250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34175350983825                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              667.631365                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   48916914851742                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1693779100000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    115815403258                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    113597968758                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
 system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
@@ -394,9 +400,9 @@ system.realview.nvmem.bw_inst_read::total            2                       # I
 system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total               3                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
@@ -404,7 +410,7 @@ system.cf0.dma_write_full_pages                  1666                       # Nu
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -434,49 +440,49 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dtb.walker.walks                    91599                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong                91599                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walkWaitTime::samples        91599                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0          91599    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total        91599                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walksPending::samples 396804151420                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     1.489246                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0   -194134706080    -48.92%    -48.92% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1   590938857500    148.92%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 396804151420                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        67399     85.01%     85.01% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M        11889     14.99%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total        79288                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        91599                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.walker.walks                    90923                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong                90923                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walkWaitTime::samples        90923                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0          90923    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total        90923                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walksPending::samples 396801198420                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     1.489265                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0   -194140819580    -48.93%    -48.93% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1   590942018000    148.93%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 396801198420                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        66800     85.03%     85.03% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        11762     14.97%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total        78562                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        90923                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        91599                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        79288                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        90923                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        78562                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        79288                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       170887                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        78562                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       169485                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    64302418                       # DTB read hits
-system.cpu0.dtb.read_misses                     69160                       # DTB read misses
-system.cpu0.dtb.write_hits                   58215557                       # DTB write hits
-system.cpu0.dtb.write_misses                    22439                       # DTB write misses
+system.cpu0.dtb.read_hits                    64271568                       # DTB read hits
+system.cpu0.dtb.read_misses                     68949                       # DTB read misses
+system.cpu0.dtb.write_hits                   58335276                       # DTB write hits
+system.cpu0.dtb.write_misses                    21974                       # DTB write misses
 system.cpu0.dtb.flush_tlb                        1189                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              16108                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                    410                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   41969                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_tlb_mva_asid              16131                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                    408                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   41721                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  2769                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                  2805                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                     7637                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                64371578                       # DTB read accesses
-system.cpu0.dtb.write_accesses               58237996                       # DTB write accesses
+system.cpu0.dtb.perms_faults                     7542                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                64340517                       # DTB read accesses
+system.cpu0.dtb.write_accesses               58357250                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        122517975                       # DTB hits
-system.cpu0.dtb.misses                          91599                       # DTB misses
-system.cpu0.dtb.accesses                    122609574                       # DTB accesses
-system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.hits                        122606844                       # DTB hits
+system.cpu0.dtb.misses                          90923                       # DTB misses
+system.cpu0.dtb.accesses                    122697767                       # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -506,54 +512,54 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.cpu0.itb.walker.walks                    53904                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong                53904                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walkWaitTime::samples        53904                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0          53904    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        53904                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walksPending::samples 396804151420                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     1.489341                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0   -194172707080    -48.93%    -48.93% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1   590976858500    148.93%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 396804151420                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        47053     95.04%     95.04% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M         2454      4.96%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        49507                       # Table walker page sizes translated
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.cpu0.itb.walker.walks                    54169                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                54169                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walkWaitTime::samples        54169                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0          54169    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        54169                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walksPending::samples 396801198420                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     1.489353                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0   -194175666580    -48.94%    -48.94% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1   590976865000    148.94%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 396801198420                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K        47334     95.01%     95.01% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M         2486      4.99%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        49820                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        53904                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        53904                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        54169                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        54169                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        49507                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        49507                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       103411                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   341562377                       # ITB inst hits
-system.cpu0.itb.inst_misses                     53904                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        49820                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        49820                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       103989                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   341484641                       # ITB inst hits
+system.cpu0.itb.inst_misses                     54169                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                        1189                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              16108                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                    410                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   29855                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              16131                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                    408                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   29832                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               341616281                       # ITB inst accesses
-system.cpu0.itb.hits                        341562377                       # DTB hits
-system.cpu0.itb.misses                          53904                       # DTB misses
-system.cpu0.itb.accesses                    341616281                       # DTB accesses
-system.cpu0.numPwrStateTransitions              12142                       # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples         6071                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean    8248096077.910065                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev   210376306672.099670                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::underflows         2573     42.38%     42.38% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10         3474     57.22%     99.60% # Distribution of time spent in the clock gated state
+system.cpu0.itb.inst_accesses               341538810                       # ITB inst accesses
+system.cpu0.itb.hits                        341484641                       # DTB hits
+system.cpu0.itb.misses                          54169                       # DTB misses
+system.cpu0.itb.accesses                    341538810                       # DTB accesses
+system.cpu0.numPwrStateTransitions              12198                       # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples         6099                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean    8210231821.367437                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev   209893503926.618408                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows         2601     42.65%     42.65% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10         3474     56.96%     99.61% # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::5e+10-1e+11            5      0.08%     99.69% # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11            1      0.02%     99.70% # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11            4      0.07%     99.77% # Distribution of time spent in the clock gated state
@@ -563,652 +569,652 @@ system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11            1      0.02%     99.84
 system.cpu0.pwrStateClkGateDist::8.5e+11-9e+11            1      0.02%     99.85% # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::overflows            9      0.15%    100.00% # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::max_value 7947193303500                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total           6071                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON   1242069912008                       # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 50074191288992                       # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles                       412426852                       # number of cpu cycles simulated
+system.cpu0.pwrStateClkGateDist::max_value 7947193321500                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total           6099                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON   1242071811480                       # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 50074203878520                       # Cumulative time (in ticks) in various power states
+system.cpu0.numCycles                       412415124                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   16568                       # number of quiesce instructions executed
-system.cpu0.committedInsts                  341412971                       # Number of instructions committed
-system.cpu0.committedOps                    401608369                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            368837990                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                362244                       # Number of float alu accesses
-system.cpu0.num_func_calls                   20461819                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     51941822                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   368837990                       # number of integer instructions
-system.cpu0.num_fp_insts                       362244                       # number of float instructions
-system.cpu0.num_int_register_reads          539535569                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         292940682                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads              578749                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             318148                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads            89683557                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           89472336                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                    122593410                       # number of memory refs
-system.cpu0.num_load_insts                   64360945                       # Number of load instructions
-system.cpu0.num_store_insts                  58232465                       # Number of store instructions
-system.cpu0.num_idle_cycles              402405334.403935                       # Number of idle cycles
-system.cpu0.num_busy_cycles              10021517.596065                       # Number of busy cycles
+system.cpu0.kern.inst.quiesce                   16566                       # number of quiesce instructions executed
+system.cpu0.committedInsts                  341336485                       # Number of instructions committed
+system.cpu0.committedOps                    401580232                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            368861574                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                359512                       # Number of float alu accesses
+system.cpu0.num_func_calls                   20525784                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     51873404                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   368861574                       # number of integer instructions
+system.cpu0.num_fp_insts                       359512                       # number of float instructions
+system.cpu0.num_int_register_reads          539079221                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         292860354                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads              571011                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes             323488                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads            89499549                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           89284497                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                    122681510                       # number of memory refs
+system.cpu0.num_load_insts                   64329809                       # Number of load instructions
+system.cpu0.num_store_insts                  58351701                       # Number of store instructions
+system.cpu0.num_idle_cycles              402393876.753300                       # Number of idle cycles
+system.cpu0.num_busy_cycles              10021247.246700                       # Number of busy cycles
 system.cpu0.not_idle_fraction                0.024299                       # Percentage of non-idle cycles
 system.cpu0.idle_fraction                    0.975701                       # Percentage of idle cycles
-system.cpu0.Branches                         76142746                       # Number of branches fetched
+system.cpu0.Branches                         76154036                       # Number of branches fetched
 system.cpu0.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                278290201     69.25%     69.25% # Class of executed instruction
-system.cpu0.op_class::IntMult                  876142      0.22%     69.47% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    42968      0.01%     69.48% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc             47686      0.01%     69.49% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.49% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.49% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.49% # Class of executed instruction
-system.cpu0.op_class::MemRead                64360945     16.02%     85.51% # Class of executed instruction
-system.cpu0.op_class::MemWrite               58232465     14.49%    100.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                278201506     69.24%     69.24% # Class of executed instruction
+system.cpu0.op_class::IntMult                  848038      0.21%     69.45% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    41846      0.01%     69.46% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  1      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc             48432      0.01%     69.47% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.47% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.47% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.47% # Class of executed instruction
+system.cpu0.op_class::MemRead                64329809     16.01%     85.48% # Class of executed instruction
+system.cpu0.op_class::MemWrite               58351701     14.52%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 401850407                       # Class of executed instruction
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements          9785258                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.999715                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          296102427                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          9785770                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            30.258470                       # Average number of references to valid blocks.
+system.cpu0.op_class::total                 401821333                       # Class of executed instruction
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.tags.replacements          9787095                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.999716                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          296232659                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          9787607                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            30.266097                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         33050500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   496.924139                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data     4.613790                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data     5.156237                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu3.data     5.305549                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.970555                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.009011                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.010071                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu3.data     0.010362                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   496.142011                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data     4.386995                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data     5.164772                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu3.data     6.305937                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.969027                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.008568                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data     0.010087                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu3.data     0.012316                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          175                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          320                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          173                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          318                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           21                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses       1254458148                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses      1254458148                       # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data     60043274                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     19451230                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data     26515970                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu3.data     46522470                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total      152532944                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     55058218                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data     17868348                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data     23514922                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu3.data     39147049                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total     135588537                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       161685                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data        47989                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu2.data        79490                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu3.data       113267                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       402431                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       128215                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu1.data        43197                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu2.data        56794                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu3.data       101554                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       329760                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1440792                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       445911                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data       586217                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu3.data       965735                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      3438655                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1532117                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data       486268                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu2.data       631716                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu3.data      1115803                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      3765904                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    115229707                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data     37362775                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data     50087686                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu3.data     85771073                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       288451241                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    115391392                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data     37410764                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data     50167176                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu3.data     85884340                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      288853672                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      2089317                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       638437                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data       880712                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu3.data      3494222                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      7102688                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       831050                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data       249767                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data       653536                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu3.data      3486415                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      5220768                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       516569                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data       133434                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu2.data       215040                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu3.data       331304                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total      1196347                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       659058                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu1.data       109033                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu2.data       156389                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu3.data       303598                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total      1228078                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        91970                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        40583                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu2.data        45717                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu3.data       183696                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       361966                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu3.data           11                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total           11                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      3579425                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data       997237                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data      1690637                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu3.data      7284235                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total      13551534                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      4095994                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data      1130671                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data      1905677                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu3.data      7615539                       # number of overall misses
-system.cpu0.dcache.overall_misses::total     14747881                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   9935057500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  14094035000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu3.data  51705605000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  75734697500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   6989560000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  18192565500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu3.data  96246799337                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 121428924837                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data   1815402000                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data   2628863500                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu3.data   5749220797                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total  10193486297                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    588884000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    647558500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data   2284034500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   3520477000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data       238500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total       238500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data  18740019500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data  34915464000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu3.data 153701625134                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 207357108634                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data  18740019500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data  34915464000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu3.data 153701625134                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 207357108634                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     62132591                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     20089667                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data     27396682                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu3.data     50016692                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total    159635632                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     55889268                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data     18118115                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data     24168458                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu3.data     42633464                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total    140809305                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       678254                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       181423                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       294530                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu3.data       444571                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total      1598778                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       787273                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       152230                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu2.data       213183                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu3.data       405152                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total      1557838                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1532762                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       486494                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data       631934                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data      1149431                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      3800621                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1532117                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       486268                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu2.data       631716                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu3.data      1115814                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      3765915                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    118809132                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data     38360012                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data     51778323                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu3.data     93055308                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    302002775                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    119487386                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data     38541435                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data     52072853                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu3.data     93499879                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    303601553                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.033627                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.031779                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.032147                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu3.data     0.069861                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.044493                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.014870                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.013785                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.027041                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu3.data     0.081776                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.037077                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.761616                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.735486                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.730112                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data     0.745222                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.748288                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.837140                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.716239                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data     0.733590                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu3.data     0.749343                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.788322                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.060003                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.083419                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.072345                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data     0.159815                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.095239                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data     0.000010                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000003                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.030128                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.025997                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.032651                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu3.data     0.078279                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.044872                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.034280                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.029337                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.036596                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu3.data     0.081450                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.048576                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15561.531522                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16003.000981                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 14797.458490                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 10662.821949                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 27984.321388                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 27837.128330                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 27606.237163                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 23258.824149                       # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 16650.023387                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 16809.772426                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 18936.952144                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total  8300.357385                       # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14510.607890                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14164.501170                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 12433.773735                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  9725.988076                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 21681.818182                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21681.818182                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18791.941635                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 20652.253559                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 21100.585735                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 15301.375374                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16574.246178                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 18321.816341                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 20182.632527                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 14060.128952                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs      9910258                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets         8881                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs           889663                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets            270                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    11.139339                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    32.892593                       # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks      7576706                       # number of writebacks
-system.cpu0.dcache.writebacks::total          7576706                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data         2565                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data        39446                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data      1918307                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total      1960318                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data           33                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       288880                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data      2890218                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      3179131                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data           17                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu3.data         2227                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::total         2244                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         9010                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data        10983                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data       113640                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total       133633                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data         2598                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data       328343                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu3.data      4810752                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      5141693                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data         2598                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data       328343                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu3.data      4810752                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      5141693                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       635872                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       841266                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data      1575915                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      3053053                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       249734                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       364656                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data       596197                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1210587                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       133434                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       214937                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data       326698                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       675069                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       109033                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data       156372                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu3.data       301371                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total       566776                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data        31573                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data        34734                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data        70056                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       136363                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data           11                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total           11                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       994639                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data      1362294                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu3.data      2473483                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      4830416                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data      1128073                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data      1577231                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu3.data      2800181                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      5505485                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         5165                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         4559                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data         4594                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        14318                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         4682                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         4068                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data         4289                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        13039                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data         9847                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data         8627                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data         8883                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        27357                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   9259931500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data  12493159000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data  23820252500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  45573343000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   6737865000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   9614650500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data  17374860004                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  33727375504                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   2271729000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   3143350500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data   4907861500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  10322941000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data   1706369000                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data   2472082000                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data   5367328797                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total   9545779797                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    413953500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data    450661000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data    926981000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1791595500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data       227500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       227500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  17704165500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  24579891500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data  46562441301                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  88846498301                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  19975894500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  27723242000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data  51470302801                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  99169439301                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    937823500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data    818983500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data    848897000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2605704000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data    937823500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data    818983500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data    848897000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   2605704000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.031652                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.030707                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.031508                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.019125                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.013784                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.015088                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.013984                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.008597                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.735486                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.729763                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data     0.734861                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.422241                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.716239                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data     0.733511                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data     0.743847                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.363822                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.064899                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.054965                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data     0.060948                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.035879                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data     0.000010                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000003                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.025929                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.026310                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data     0.026581                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.015995                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.029269                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.030289                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data     0.029948                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.018134                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14562.571555                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14850.426619                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15115.188636                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14927.137852                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26980.166898                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26366.357608                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 29142.816894                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27860.348330                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17025.113539                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14624.520208                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15022.624871                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15291.682776                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 15650.023387                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 15808.981148                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 17809.705635                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 16842.244197                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13110.996738                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12974.635804                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 13232.000114                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13138.428313                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 20681.818182                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20681.818182                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17799.589097                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18043.015311                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 18824.645773                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18393.135974                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17707.980335                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17577.160226                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 18381.062796                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18012.843428                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 181572.797677                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 179641.039702                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 184783.848498                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 181987.987149                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95239.514573                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 94932.595340                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 95564.223798                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 95248.163176                       # average overall mshr uncacheable latency
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements         15885620                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.975044                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          560402159                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs         15886132                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            35.276187                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       9934044500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   471.724807                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst     2.897260                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst    29.967538                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu3.inst     7.385439                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.921338                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.005659                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.058530                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu3.inst     0.014425                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.tag_accesses       1255111411                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses      1255111411                       # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.ReadReq_hits::cpu0.data     60046999                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data     19454301                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data     26463320                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu3.data     46623681                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total      152588301                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     55195720                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data     17791665                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu2.data     23636838                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu3.data     39052226                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total     135676449                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       163106                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data        47592                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu2.data        79678                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu3.data       112887                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       403263                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       128728                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu1.data        43000                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu2.data        56036                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu3.data       102004                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       329768                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1435392                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       439802                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu2.data       587328                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu3.data       976810                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      3439332                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1527210                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data       478716                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu2.data       634274                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu3.data      1126445                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      3766645                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    115371447                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data     37288966                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu2.data     50156194                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu3.data     85777911                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       288594518                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    115534553                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data     37336558                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu2.data     50235872                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu3.data     85890798                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      288997781                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      2061230                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data       642663                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu2.data       875897                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu3.data      3581810                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      7161600                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       820986                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data       258023                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu2.data       651148                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu3.data      3449880                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      5180037                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       513166                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data       142485                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu2.data       214232                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu3.data       325164                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total      1195047                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       655346                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu1.data       113890                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu2.data       151535                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu3.data       307504                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total      1228275                       # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        92447                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        39128                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu2.data        47209                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu3.data       183438                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       362222                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu3.data            7                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total            7                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      3537562                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data      1014576                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu2.data      1678580                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu3.data      7339194                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total      13569912                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      4050728                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data      1157061                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu2.data      1892812                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu3.data      7664358                       # number of overall misses
+system.cpu0.dcache.overall_misses::total     14764959                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   9992794500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  13884394000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu3.data  52878438500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  76755627000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   6954335000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  17889776000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu3.data  96530515223                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 121374626223                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data   1854766500                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data   2567644000                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu3.data   5803246814                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total  10225657314                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    554773000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    665492500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data   2279898500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   3500164000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data       188500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total       188500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data  18801896000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data  34341814000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu3.data 155212200537                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 208355910537                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data  18801896000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data  34341814000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu3.data 155212200537                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 208355910537                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     62108229                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data     20096964                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data     27339217                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu3.data     50205491                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total    159749901                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     56016706                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data     18049688                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data     24287986                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu3.data     42502106                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total    140856486                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       676272                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       190077                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       293910                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu3.data       438051                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total      1598310                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       784074                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       156890                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu2.data       207571                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu3.data       409508                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total      1558043                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1527839                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       478930                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data       634537                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data      1160248                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      3801554                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1527210                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       478716                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu2.data       634274                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu3.data      1126452                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      3766652                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    118909009                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data     38303542                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data     51834774                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu3.data     93117105                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    302164430                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    119585281                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data     38493619                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data     52128684                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu3.data     93555156                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    303762740                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.033188                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.031978                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.032038                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu3.data     0.071343                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.044830                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.014656                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.014295                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.026809                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu3.data     0.081170                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.036775                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.758816                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.749617                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.728903                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data     0.742297                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.747694                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.835822                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.725923                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data     0.730039                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu3.data     0.750911                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.788345                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.060508                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.081699                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.074399                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data     0.158102                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.095283                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data     0.000006                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000002                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.029750                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.026488                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.032383                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu3.data     0.078817                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.044909                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.033873                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.030059                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.036310                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu3.data     0.081923                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.048607                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15549.042811                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15851.628673                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 14763.049548                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 10717.664628                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 26952.384090                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 27474.208628                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 27980.832731                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 23431.227658                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 16285.595750                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 16944.230706                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 18872.101872                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total  8325.218143                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14178.414435                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14096.729437                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 12428.714334                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  9663.035376                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 26928.571429                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26928.571429                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18531.776821                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 20458.848551                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 21148.398658                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 15354.256574                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16249.701615                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 18143.277832                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 20251.167878                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 14111.512977                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs      9947101                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets         9301                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs           883316                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets            261                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    11.261090                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    35.636015                       # average number of cycles each access was blocked
+system.cpu0.dcache.writebacks::writebacks      7580739                       # number of writebacks
+system.cpu0.dcache.writebacks::total          7580739                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data         2342                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data        38832                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data      1981448                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total      2022622                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data           31                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       288487                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data      2860546                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      3149064                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data           16                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu3.data         2230                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::total         2246                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         8708                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data        10679                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data       112790                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total       132177                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data         2373                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data       327335                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu3.data      4844224                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      5173932                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data         2373                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data       327335                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu3.data      4844224                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      5173932                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       640321                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       837065                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data      1600362                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      3077748                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       257992                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       362661                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data       589334                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1209987                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       142485                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       214116                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data       320624                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       677225                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       113890                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data       151519                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu3.data       305274                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total       570683                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data        30420                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data        36530                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data        70648                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       137598                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data            7                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total            7                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data      1012203                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data      1351245                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu3.data      2494970                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      4858418                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data      1154688                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data      1565361                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu3.data      2815594                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      5535643                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         5039                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         4577                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data         4597                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        14213                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         4567                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         4089                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data         4315                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        12971                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data         9606                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data         8666                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data         8912                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        27184                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   9316912500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data  12310511500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data  24145682500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  45773106500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   6694367500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   9409306500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data  17283283287                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  33386957287                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   2351295000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   3106665500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data   4848120000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  10306080500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data   1740876500                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data   2415825500                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data   5418758314                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total   9575460314                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    393499000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data    471106000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data    934011000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1798616000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data       181500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       181500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  17752156500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  24135643500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data  46847724101                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  88735524101                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  20103451500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  27242309000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data  51695844101                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  99041604601                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    916274500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data    823963000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data    848646500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2588884000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data    916274500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data    823963000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data    848646500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   2588884000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.031862                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.030618                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.031876                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.019266                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014293                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.014932                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.013866                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.008590                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.749617                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.728509                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data     0.731933                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.423713                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.725923                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data     0.729962                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data     0.745465                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.366282                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.063517                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.057570                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data     0.060890                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.036195                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data     0.000006                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.026426                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.026068                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data     0.026794                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.016079                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.029997                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.030029                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data     0.030096                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.018224                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14550.377857                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14706.756942                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15087.637984                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14872.272356                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25947.965441                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25945.184346                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 29326.804982                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27592.823135                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16502.052848                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14509.263670                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15120.889266                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15218.104027                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 15285.595750                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 15944.043321                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 17750.474374                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 16778.947882                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12935.535832                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12896.413906                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 13220.629034                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13071.527202                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 25928.571429                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25928.571429                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17538.138595                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17861.781912                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 18776.868700                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18264.283580                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17410.288753                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17403.211783                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 18360.546336                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17891.617035                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 181836.574717                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 180022.503823                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 184608.766587                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 182149.018504                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95385.644389                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 95079.967690                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 95225.145871                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 95235.579753                       # average overall mshr uncacheable latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.tags.replacements         15900081                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.975051                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          560800301                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs         15900593                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            35.269144                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle       9932119500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   471.881688                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst     2.899404                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst    30.014484                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu3.inst     7.179475                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.921644                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.005663                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst     0.058622                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu3.inst     0.014022                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.999951                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          145                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          315                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           52                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          157                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          292                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           63                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        592540078                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       592540078                       # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst    336114841                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst    108439877                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst     66818852                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu3.inst     49028589                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      560402159                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    336114841                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst    108439877                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst     66818852                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu3.inst     49028589                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       560402159                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    336114841                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst    108439877                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst     66818852                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu3.inst     49028589                       # number of overall hits
-system.cpu0.icache.overall_hits::total      560402159                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      5497043                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst      1722599                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst      3878852                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu3.inst      5153185                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total     16251679                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      5497043                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst      1722599                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst      3878852                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu3.inst      5153185                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total      16251679                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      5497043                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst      1722599                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst      3878852                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu3.inst      5153185                       # number of overall misses
-system.cpu0.icache.overall_misses::total     16251679                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  23158585000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst  52412047500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu3.inst  67562221360                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 143132853860                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst  23158585000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst  52412047500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu3.inst  67562221360                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 143132853860                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst  23158585000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst  52412047500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu3.inst  67562221360                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 143132853860                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    341611884                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst    110162476                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst     70697704                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu3.inst     54181774                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    576653838                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    341611884                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst    110162476                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst     70697704                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu3.inst     54181774                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    576653838                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    341611884                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst    110162476                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst     70697704                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu3.inst     54181774                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    576653838                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016091                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015637                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.054865                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu3.inst     0.095109                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.028183                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016091                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015637                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst     0.054865                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu3.inst     0.095109                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.028183                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016091                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015637                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst     0.054865                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu3.inst     0.095109                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.028183                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13443.979127                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13512.257622                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13110.769623                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  8807.265628                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13443.979127                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13512.257622                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13110.769623                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  8807.265628                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13443.979127                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13512.257622                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13110.769623                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  8807.265628                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs        37944                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses        592967136                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       592967136                       # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.ReadReq_hits::cpu0.inst    336023230                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst    108879045                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst     66719955                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu3.inst     49178071                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      560800301                       # number of ReadReq hits
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+system.cpu0.icache.demand_hits::cpu2.inst     66719955                       # number of demand (read+write) hits
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+system.cpu0.icache.demand_hits::total       560800301                       # number of demand (read+write) hits
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+system.cpu0.icache.overall_hits::cpu1.inst    108879045                       # number of overall hits
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+system.cpu0.icache.overall_hits::total      560800301                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      5511231                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst      1701578                       # number of ReadReq misses
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+system.cpu0.icache.ReadReq_misses::total     16266135                       # number of ReadReq misses
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+system.cpu0.icache.overall_misses::total     16266135                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  22882569500                       # number of ReadReq miss cycles
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+system.cpu0.icache.ReadReq_miss_latency::total 143090193346                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst  22882569500                       # number of demand (read+write) miss cycles
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+system.cpu0.icache.demand_miss_latency::total 143090193346                       # number of demand (read+write) miss cycles
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+system.cpu0.icache.overall_miss_latency::cpu3.inst  67452926346                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 143090193346                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    341534461                       # number of ReadReq accesses(hits+misses)
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+system.cpu0.icache.overall_accesses::cpu2.inst     70629466                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu3.inst     54321886                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    577066436                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016137                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015388                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.055352                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu3.inst     0.094691                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.028188                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016137                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015388                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst     0.055352                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu3.inst     0.094691                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.028188                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016137                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015388                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst     0.055352                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu3.inst     0.094691                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.028188                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13447.852229                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13493.937605                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13113.404418                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  8796.815798                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13447.852229                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13493.937605                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13113.404418                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  8796.815798                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13447.852229                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13493.937605                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13113.404418                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  8796.815798                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs        37904                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs             3053                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs             3068                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    12.428431                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    12.354628                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks     15885620                       # number of writebacks
-system.cpu0.icache.writebacks::total         15885620                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst       365439                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total       365439                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu3.inst       365439                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total       365439                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu3.inst       365439                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total       365439                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      1722599                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst      3878852                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst      4787746                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total     10389197                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst      1722599                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst      3878852                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu3.inst      4787746                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total     10389197                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst      1722599                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst      3878852                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu3.inst      4787746                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total     10389197                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  21435986000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst  48533195500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst  59905132390                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 129874313890                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  21435986000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst  48533195500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst  59905132390                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 129874313890                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  21435986000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst  48533195500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst  59905132390                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 129874313890                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015637                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.054865                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.088365                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.018016                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015637                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.054865                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst     0.088365                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.018016                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015637                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.054865                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst     0.088365                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.018016                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12443.979127                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12512.257622                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12512.178464                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12500.900107                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12443.979127                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12512.257622                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12512.178464                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12500.900107                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12443.979127                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12512.257622                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12512.178464                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12500.900107                       # average overall mshr miss latency
-system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.writebacks::writebacks     15900081                       # number of writebacks
+system.cpu0.icache.writebacks::total         15900081                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst       365435                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total       365435                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu3.inst       365435                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total       365435                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu3.inst       365435                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total       365435                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      1701578                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst      3909511                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst      4778380                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total     10389469                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst      1701578                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst      3909511                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu3.inst      4778380                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total     10389469                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst      1701578                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst      3909511                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu3.inst      4778380                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total     10389469                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  21180991500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst  48845186500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst  59808862373                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 129835040373                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  21180991500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst  48845186500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst  59808862373                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 129835040373                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  21180991500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst  48845186500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst  59808862373                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 129835040373                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015388                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.055352                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.087964                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.018004                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015388                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.055352                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst     0.087964                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.018004                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015388                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.055352                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst     0.087964                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.018004                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12447.852229                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12493.937605                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12516.556317                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12496.792702                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12447.852229                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12493.937605                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12516.556317                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12496.792702                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12447.852229                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12493.937605                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12516.556317                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12496.792702                       # average overall mshr miss latency
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1238,69 +1244,65 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dtb.walker.walks                    31142                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong                31142                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         4562                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        22714                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore            4                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples        31138                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0          31138    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total        31138                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples        27280                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 24555.205279                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 21409.224401                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 12983.742991                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-32767        17842     65.40%     65.40% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-65535         9287     34.04%     99.45% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-98303           82      0.30%     99.75% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::98304-131071           48      0.18%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-163839            1      0.00%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::163840-196607            6      0.02%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-229375            4      0.01%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::229376-262143            4      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-294911            3      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-360447            1      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::360448-393215            2      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total        27280                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples   2381232620                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.574632                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.494399                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0     1012901000     42.54%     42.54% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1     1368331620     57.46%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total   2381232620                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        22714     83.27%     83.27% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M         4562     16.73%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total        27276                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        31142                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.walker.walks                    31190                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong                31190                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         4602                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        22894                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore            2                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples        31188                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0          31188    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total        31188                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples        27498                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 23439.468325                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 20168.956165                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 13617.892423                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535        27307     99.31%     99.31% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071          167      0.61%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607           10      0.04%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143            9      0.03%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679            2      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215            2      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total        27498                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples   2364440120                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.573010                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.494641                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0     1009591500     42.70%     42.70% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1     1354848620     57.30%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total   2364440120                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        22894     83.26%     83.26% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M         4602     16.74%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total        27496                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        31190                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        31142                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        27276                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        31190                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        27496                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        27276                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total        58418                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        27496                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        58686                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    20762749                       # DTB read hits
-system.cpu1.dtb.read_misses                     23873                       # DTB read misses
-system.cpu1.dtb.write_hits                   18763804                       # DTB write hits
-system.cpu1.dtb.write_misses                     7269                       # DTB write misses
+system.cpu1.dtb.read_hits                    20771010                       # DTB read hits
+system.cpu1.dtb.read_misses                     23692                       # DTB read misses
+system.cpu1.dtb.write_hits                   18692480                       # DTB write hits
+system.cpu1.dtb.write_misses                     7498                       # DTB write misses
 system.cpu1.dtb.flush_tlb                        1182                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid               5192                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                    138                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   17777                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid               5140                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                    135                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   17937                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   955                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                  1005                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                     2493                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                20786622                       # DTB read accesses
-system.cpu1.dtb.write_accesses               18771073                       # DTB write accesses
+system.cpu1.dtb.perms_faults                     2603                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                20794702                       # DTB read accesses
+system.cpu1.dtb.write_accesses               18699978                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         39526553                       # DTB hits
-system.cpu1.dtb.misses                          31142                       # DTB misses
-system.cpu1.dtb.accesses                     39557695                       # DTB accesses
-system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.hits                         39463490                       # DTB hits
+system.cpu1.dtb.misses                          31190                       # DTB misses
+system.cpu1.dtb.accesses                     39494680                       # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1330,154 +1332,155 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.cpu1.itb.walker.walks                    19936                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong                19936                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2          932                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        17656                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples        19936                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0          19936    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        19936                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        18588                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 27393.103077                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 24671.512984                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 13247.215063                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-32767        10003     53.81%     53.81% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-65535         8429     45.35%     99.16% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-98303           57      0.31%     99.47% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::98304-131071           80      0.43%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-163839            2      0.01%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::163840-196607            6      0.03%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-229375            2      0.01%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::229376-262143            4      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-294911            3      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::294912-327679            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::360448-393215            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        18588                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.cpu1.itb.walker.walks                    19592                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                19592                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2          942                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        17338                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples        19592                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0          19592    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        19592                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        18280                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 26364.633479                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 23452.518551                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 14371.838603                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-32767        10663     58.33%     58.33% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-65535         7451     40.76%     99.09% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-98303           65      0.36%     99.45% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::98304-131071           75      0.41%     99.86% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-163839            1      0.01%     99.86% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::163840-196607           10      0.05%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-229375            1      0.01%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::229376-262143            7      0.04%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-294911            1      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::294912-327679            3      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-360447            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::360448-393215            2      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        18280                       # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walksPending::samples   1000000500                       # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::0     1000000500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::total   1000000500                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        17656     94.99%     94.99% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M          932      5.01%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        18588                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::4K        17338     94.85%     94.85% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M          942      5.15%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        18280                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        19936                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total        19936                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        19592                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        19592                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        18588                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        18588                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total        38524                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   110162476                       # ITB inst hits
-system.cpu1.itb.inst_misses                     19936                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        18280                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        18280                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total        37872                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   110580623                       # ITB inst hits
+system.cpu1.itb.inst_misses                     19592                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                        1182                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid               5192                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                    138                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   13192                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid               5140                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                    135                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   13235                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               110182412                       # ITB inst accesses
-system.cpu1.itb.hits                        110162476                       # DTB hits
-system.cpu1.itb.misses                          19936                       # DTB misses
-system.cpu1.itb.accesses                    110182412                       # DTB accesses
-system.cpu1.numPwrStateTransitions               6038                       # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples         3019                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean    4031562886.362703                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev   205285027256.597076                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::underflows          926     30.67%     30.67% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1000-5e+10         2090     69.23%     99.90% # Distribution of time spent in the clock gated state
+system.cpu1.itb.inst_accesses               110600215                       # ITB inst accesses
+system.cpu1.itb.hits                        110580623                       # DTB hits
+system.cpu1.itb.misses                          19592                       # DTB misses
+system.cpu1.itb.accesses                    110600215                       # DTB accesses
+system.cpu1.numPwrStateTransitions               6016                       # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples         3008                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean    4046290699.440825                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev   205659188461.921204                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows          915     30.42%     30.42% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10         2090     69.48%     99.90% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11            1      0.03%     99.93% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11            1      0.03%     99.97% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::overflows            1      0.03%    100.00% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::max_value 11261576634501                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total           3019                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON   39144972847071                       # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 12171288353929                       # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles                      1182097366                       # number of cpu cycles simulated
+system.cpu1.pwrStateClkGateDist::max_value 11261531014001                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total           3008                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON   39145033266082                       # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 12171242423918                       # Cumulative time (in ticks) in various power states
+system.cpu1.numCycles                      1182100228                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu1.committedInsts                  110088686                       # Number of instructions committed
-system.cpu1.committedOps                    129237809                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses            118887794                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                113577                       # Number of float alu accesses
-system.cpu1.num_func_calls                    6597658                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts     16662523                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                   118887794                       # number of integer instructions
-system.cpu1.num_fp_insts                       113577                       # number of float instructions
-system.cpu1.num_int_register_reads          170702989                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          94155610                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads              183331                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes              96228                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            28150227                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes           28060459                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                     39523640                       # number of memory refs
-system.cpu1.num_load_insts                   20761578                       # Number of load instructions
-system.cpu1.num_store_insts                  18762062                       # Number of store instructions
-system.cpu1.num_idle_cycles              1155305857.273267                       # Number of idle cycles
-system.cpu1.num_busy_cycles              26791508.726733                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.022664                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.977336                       # Percentage of idle cycles
-system.cpu1.Branches                         24572277                       # Number of branches fetched
+system.cpu1.committedInsts                  110507936                       # Number of instructions committed
+system.cpu1.committedOps                    129543713                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses            119008832                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                107333                       # Number of float alu accesses
+system.cpu1.num_func_calls                    6516685                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts     16787846                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                   119008832                       # number of integer instructions
+system.cpu1.num_fp_insts                       107333                       # number of float instructions
+system.cpu1.num_int_register_reads          172055074                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          94356642                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads              176403                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes              83340                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads            28608279                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           28519816                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                     39460487                       # number of memory refs
+system.cpu1.num_load_insts                   20769710                       # Number of load instructions
+system.cpu1.num_store_insts                  18690777                       # Number of store instructions
+system.cpu1.num_idle_cycles              1155308161.927193                       # Number of idle cycles
+system.cpu1.num_busy_cycles              26792066.072807                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.022665                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.977335                       # Percentage of idle cycles
+system.cpu1.Branches                         24662743                       # Number of branches fetched
 system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 89498355     69.21%     69.21% # Class of executed instruction
-system.cpu1.op_class::IntMult                  266792      0.21%     69.42% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    10604      0.01%     69.43% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc             12166      0.01%     69.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.44% # Class of executed instruction
-system.cpu1.op_class::MemRead                20761578     16.06%     85.49% # Class of executed instruction
-system.cpu1.op_class::MemWrite               18762062     14.51%    100.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 89857347     69.33%     69.33% # Class of executed instruction
+system.cpu1.op_class::IntMult                  277190      0.21%     69.54% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    11015      0.01%     69.55% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                 20      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.55% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc             10320      0.01%     69.56% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.56% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.56% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.56% # Class of executed instruction
+system.cpu1.op_class::MemRead                20769710     16.02%     85.58% # Class of executed instruction
+system.cpu1.op_class::MemWrite               18690777     14.42%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                 129311599                       # Class of executed instruction
-system.cpu2.branchPred.lookups               40882537                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted         28404958                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect          2018640                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups            29949697                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits               20329283                       # Number of BTB hits
+system.cpu1.op_class::total                 129616400                       # Class of executed instruction
+system.cpu2.branchPred.lookups               40854703                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted         28349635                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect          2013069                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups            29873482                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits               20268490                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            67.878092                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                4945381                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect            329320                       # Number of incorrect RAS predictions.
-system.cpu2.branchPred.indirectLookups        1144842                       # Number of indirect predictor lookups.
-system.cpu2.branchPred.indirectHits            797183                       # Number of indirect target hits.
-system.cpu2.branchPred.indirectMisses          347659                       # Number of indirect misses.
-system.cpu2.branchPredindirectMispredicted       143486                       # Number of mispredicted indirect branches.
-system.cpu2.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
+system.cpu2.branchPred.BTBHitPct            67.847765                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                4987413                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect            331344                       # Number of incorrect RAS predictions.
+system.cpu2.branchPred.indirectLookups        1163100                       # Number of indirect predictor lookups.
+system.cpu2.branchPred.indirectHits            806401                       # Number of indirect target hits.
+system.cpu2.branchPred.indirectMisses          356699                       # Number of indirect misses.
+system.cpu2.branchPredindirectMispredicted       146740                       # Number of mispredicted indirect branches.
+system.cpu2.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
 system.cpu2.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1507,66 +1510,66 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu2.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu2.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu2.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu2.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.cpu2.dtb.walker.walks                    93219                       # Table walker walks requested
-system.cpu2.dtb.walker.walksLong                93219                       # Table walker walks initiated with long descriptors
-system.cpu2.dtb.walker.walksLongTerminationLevel::Level2         7034                       # Level at which table walker walks with long descriptors terminate
-system.cpu2.dtb.walker.walksLongTerminationLevel::Level3        30340                       # Level at which table walker walks with long descriptors terminate
-system.cpu2.dtb.walker.walkWaitTime::samples        93219                       # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::0          93219    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::total        93219                       # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkCompletionTime::samples        37374                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::mean 25165.904104                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::gmean 22274.336205                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::stdev 12675.748220                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::0-32767        24476     65.49%     65.49% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::32768-65535        12701     33.98%     99.47% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::65536-98303          113      0.30%     99.78% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::98304-131071           53      0.14%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::131072-163839            2      0.01%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::163840-196607           11      0.03%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::196608-229375            2      0.01%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::229376-262143            5      0.01%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::262144-294911            6      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.cpu2.dtb.walker.walks                    93799                       # Table walker walks requested
+system.cpu2.dtb.walker.walksLong                93799                       # Table walker walks initiated with long descriptors
+system.cpu2.dtb.walker.walksLongTerminationLevel::Level2         7024                       # Level at which table walker walks with long descriptors terminate
+system.cpu2.dtb.walker.walksLongTerminationLevel::Level3        30187                       # Level at which table walker walks with long descriptors terminate
+system.cpu2.dtb.walker.walkWaitTime::samples        93799                       # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::0          93799    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::total        93799                       # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkCompletionTime::samples        37211                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::mean 23608.785037                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::gmean 20477.524093                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::stdev 12702.189700                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::0-32767        25796     69.32%     69.32% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::32768-65535        11234     30.19%     99.51% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::65536-98303           97      0.26%     99.77% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::98304-131071           57      0.15%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::131072-163839            1      0.00%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::163840-196607           11      0.03%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::196608-229375            2      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::229376-262143            5      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::262144-294911            3      0.01%     99.99% # Table walker service (enqueue to completion) latency
 system.cpu2.dtb.walker.walkCompletionTime::294912-327679            2      0.01%     99.99% # Table walker service (enqueue to completion) latency
 system.cpu2.dtb.walker.walkCompletionTime::327680-360447            2      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::total        37374                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::360448-393215            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::total        37211                       # Table walker service (enqueue to completion) latency
 system.cpu2.dtb.walker.walksPending::samples   2000359000                       # Table walker pending requests distribution
 system.cpu2.dtb.walker.walksPending::0     2000359000    100.00%    100.00% # Table walker pending requests distribution
 system.cpu2.dtb.walker.walksPending::total   2000359000                       # Table walker pending requests distribution
-system.cpu2.dtb.walker.walkPageSizes::4K        30340     81.18%     81.18% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::2M         7034     18.82%    100.00% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::total        37374                       # Table walker page sizes translated
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data        93219                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkPageSizes::4K        30187     81.12%     81.12% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::2M         7024     18.88%    100.00% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::total        37211                       # Table walker page sizes translated
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data        93799                       # Table walker requests started/completed, data/inst
 system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::total        93219                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data        37374                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::total        93799                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data        37211                       # Table walker requests started/completed, data/inst
 system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::total        37374                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin::total       130593                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::total        37211                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin::total       131010                       # Table walker requests started/completed, data/inst
 system.cpu2.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu2.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu2.dtb.read_hits                    28583495                       # DTB read hits
-system.cpu2.dtb.read_misses                     77825                       # DTB read misses
-system.cpu2.dtb.write_hits                   25112772                       # DTB write hits
-system.cpu2.dtb.write_misses                    15394                       # DTB write misses
-system.cpu2.dtb.flush_tlb                        1182                       # Number of times complete TLB was flushed
+system.cpu2.dtb.read_hits                    28529245                       # DTB read hits
+system.cpu2.dtb.read_misses                     78357                       # DTB read misses
+system.cpu2.dtb.write_hits                   25227275                       # DTB write hits
+system.cpu2.dtb.write_misses                    15442                       # DTB write misses
+system.cpu2.dtb.flush_tlb                        1183                       # Number of times complete TLB was flushed
 system.cpu2.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu2.dtb.flush_tlb_mva_asid               7038                       # Number of times TLB was flushed by MVA & ASID
-system.cpu2.dtb.flush_tlb_asid                    188                       # Number of times TLB was flushed by ASID
-system.cpu2.dtb.flush_entries                   22760                       # Number of entries that have been flushed from TLB
+system.cpu2.dtb.flush_tlb_mva_asid               7123                       # Number of times TLB was flushed by MVA & ASID
+system.cpu2.dtb.flush_tlb_asid                    191                       # Number of times TLB was flushed by ASID
+system.cpu2.dtb.flush_entries                   22552                       # Number of entries that have been flushed from TLB
 system.cpu2.dtb.align_faults                       83                       # Number of TLB faults due to alignment restrictions
-system.cpu2.dtb.prefetch_faults                  2252                       # Number of TLB faults due to prefetch
+system.cpu2.dtb.prefetch_faults                  2182                       # Number of TLB faults due to prefetch
 system.cpu2.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.dtb.perms_faults                     3984                       # Number of TLB faults due to permissions restrictions
-system.cpu2.dtb.read_accesses                28661320                       # DTB read accesses
-system.cpu2.dtb.write_accesses               25128166                       # DTB write accesses
+system.cpu2.dtb.perms_faults                     3958                       # Number of TLB faults due to permissions restrictions
+system.cpu2.dtb.read_accesses                28607602                       # DTB read accesses
+system.cpu2.dtb.write_accesses               25242717                       # DTB write accesses
 system.cpu2.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu2.dtb.hits                         53696267                       # DTB hits
-system.cpu2.dtb.misses                          93219                       # DTB misses
-system.cpu2.dtb.accesses                     53789486                       # DTB accesses
-system.cpu2.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
+system.cpu2.dtb.hits                         53756520                       # DTB hits
+system.cpu2.dtb.misses                          93799                       # DTB misses
+system.cpu2.dtb.accesses                     53850319                       # DTB accesses
+system.cpu2.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
 system.cpu2.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1596,149 +1599,147 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu2.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu2.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu2.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu2.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.cpu2.itb.walker.walks                    27359                       # Table walker walks requested
-system.cpu2.itb.walker.walksLong                27359                       # Table walker walks initiated with long descriptors
-system.cpu2.itb.walker.walksLongTerminationLevel::Level2         1819                       # Level at which table walker walks with long descriptors terminate
-system.cpu2.itb.walker.walksLongTerminationLevel::Level3        22616                       # Level at which table walker walks with long descriptors terminate
-system.cpu2.itb.walker.walkWaitTime::samples        27359                       # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::0          27359    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::total        27359                       # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkCompletionTime::samples        24435                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::mean 28370.002046                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::gmean 25752.666599                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::stdev 13391.544423                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::0-32767        12572     51.45%     51.45% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::32768-65535        11615     47.53%     98.99% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::65536-98303           92      0.38%     99.36% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::98304-131071          132      0.54%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::131072-163839            2      0.01%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::163840-196607            9      0.04%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::196608-229375            5      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.cpu2.itb.walker.walks                    27208                       # Table walker walks requested
+system.cpu2.itb.walker.walksLong                27208                       # Table walker walks initiated with long descriptors
+system.cpu2.itb.walker.walksLongTerminationLevel::Level2         1843                       # Level at which table walker walks with long descriptors terminate
+system.cpu2.itb.walker.walksLongTerminationLevel::Level3        22528                       # Level at which table walker walks with long descriptors terminate
+system.cpu2.itb.walker.walkWaitTime::samples        27208                       # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::0          27208    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::total        27208                       # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkCompletionTime::samples        24371                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::mean 26858.233146                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::gmean 23932.181675                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::stdev 13621.050617                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::0-32767        13667     56.08%     56.08% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::32768-65535        10461     42.92%     99.00% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::65536-98303           87      0.36%     99.36% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::98304-131071          133      0.55%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::131072-163839            3      0.01%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::163840-196607           12      0.05%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::196608-229375            1      0.00%     99.97% # Table walker service (enqueue to completion) latency
 system.cpu2.itb.walker.walkCompletionTime::229376-262143            2      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::262144-294911            1      0.00%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::294912-327679            2      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::327680-360447            2      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::360448-393215            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::total        24435                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::262144-294911            3      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::360448-393215            2      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::total        24371                       # Table walker service (enqueue to completion) latency
 system.cpu2.itb.walker.walksPending::samples   2000327000                       # Table walker pending requests distribution
 system.cpu2.itb.walker.walksPending::0     2000327000    100.00%    100.00% # Table walker pending requests distribution
 system.cpu2.itb.walker.walksPending::total   2000327000                       # Table walker pending requests distribution
-system.cpu2.itb.walker.walkPageSizes::4K        22616     92.56%     92.56% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::2M         1819      7.44%    100.00% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::total        24435                       # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::4K        22528     92.44%     92.44% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::2M         1843      7.56%    100.00% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::total        24371                       # Table walker page sizes translated
 system.cpu2.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst        27359                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::total        27359                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst        27208                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::total        27208                       # Table walker requests started/completed, data/inst
 system.cpu2.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst        24435                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::total        24435                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin::total        51794                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.inst_hits                    70751081                       # ITB inst hits
-system.cpu2.itb.inst_misses                     27359                       # ITB inst misses
+system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst        24371                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Completed::total        24371                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin::total        51579                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.inst_hits                    70683304                       # ITB inst hits
+system.cpu2.itb.inst_misses                     27208                       # ITB inst misses
 system.cpu2.itb.read_hits                           0                       # DTB read hits
 system.cpu2.itb.read_misses                         0                       # DTB read misses
 system.cpu2.itb.write_hits                          0                       # DTB write hits
 system.cpu2.itb.write_misses                        0                       # DTB write misses
-system.cpu2.itb.flush_tlb                        1182                       # Number of times complete TLB was flushed
+system.cpu2.itb.flush_tlb                        1183                       # Number of times complete TLB was flushed
 system.cpu2.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu2.itb.flush_tlb_mva_asid               7038                       # Number of times TLB was flushed by MVA & ASID
-system.cpu2.itb.flush_tlb_asid                    188                       # Number of times TLB was flushed by ASID
-system.cpu2.itb.flush_entries                   17251                       # Number of entries that have been flushed from TLB
+system.cpu2.itb.flush_tlb_mva_asid               7123                       # Number of times TLB was flushed by MVA & ASID
+system.cpu2.itb.flush_tlb_asid                    191                       # Number of times TLB was flushed by ASID
+system.cpu2.itb.flush_entries                   16893                       # Number of entries that have been flushed from TLB
 system.cpu2.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu2.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu2.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.itb.perms_faults                    50621                       # Number of TLB faults due to permissions restrictions
+system.cpu2.itb.perms_faults                    51118                       # Number of TLB faults due to permissions restrictions
 system.cpu2.itb.read_accesses                       0                       # DTB read accesses
 system.cpu2.itb.write_accesses                      0                       # DTB write accesses
-system.cpu2.itb.inst_accesses                70778440                       # ITB inst accesses
-system.cpu2.itb.hits                         70751081                       # DTB hits
-system.cpu2.itb.misses                          27359                       # DTB misses
-system.cpu2.itb.accesses                     70778440                       # DTB accesses
-system.cpu2.numPwrStateTransitions               7068                       # Number of power state transitions
-system.cpu2.pwrStateClkGateDist::samples         3534                       # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::mean    14278760224.142614                       # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::stdev   128952650694.550415                       # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::underflows         1173     33.19%     33.19% # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::1000-5e+10         2324     65.76%     98.95% # Distribution of time spent in the clock gated state
+system.cpu2.itb.inst_accesses                70710512                       # ITB inst accesses
+system.cpu2.itb.hits                         70683304                       # DTB hits
+system.cpu2.itb.misses                          27208                       # DTB misses
+system.cpu2.itb.accesses                     70710512                       # DTB accesses
+system.cpu2.numPwrStateTransitions               7024                       # Number of power state transitions
+system.cpu2.pwrStateClkGateDist::samples         3512                       # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::mean    14368150694.236048                       # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::stdev   129350965742.418961                       # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::underflows         1152     32.80%     32.80% # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::1000-5e+10         2323     66.14%     98.95% # Distribution of time spent in the clock gated state
 system.cpu2.pwrStateClkGateDist::5e+10-1e+11            6      0.17%     99.12% # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::1e+11-1.5e+11            3      0.08%     99.21% # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::1e+11-1.5e+11            3      0.09%     99.20% # Distribution of time spent in the clock gated state
 system.cpu2.pwrStateClkGateDist::1.5e+11-2e+11            2      0.06%     99.26% # Distribution of time spent in the clock gated state
 system.cpu2.pwrStateClkGateDist::2e+11-2.5e+11            2      0.06%     99.32% # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::2.5e+11-3e+11            2      0.06%     99.38% # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::3e+11-3.5e+11            1      0.03%     99.41% # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::2.5e+11-3e+11            2      0.06%     99.37% # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::3e+11-3.5e+11            1      0.03%     99.40% # Distribution of time spent in the clock gated state
 system.cpu2.pwrStateClkGateDist::4.5e+11-5e+11            1      0.03%     99.43% # Distribution of time spent in the clock gated state
 system.cpu2.pwrStateClkGateDist::5e+11-5.5e+11            1      0.03%     99.46% # Distribution of time spent in the clock gated state
 system.cpu2.pwrStateClkGateDist::7e+11-7.5e+11            1      0.03%     99.49% # Distribution of time spent in the clock gated state
 system.cpu2.pwrStateClkGateDist::overflows           18      0.51%    100.00% # Distribution of time spent in the clock gated state
 system.cpu2.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::max_value 1988791938500                       # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::total           3534                       # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateResidencyTicks::ON   855122568880                       # Cumulative time (in ticks) in various power states
-system.cpu2.pwrStateResidencyTicks::CLK_GATED 50461138632120                       # Cumulative time (in ticks) in various power states
-system.cpu2.numCycles                      1176514820                       # number of cpu cycles simulated
+system.cpu2.pwrStateClkGateDist::max_value 1988791978000                       # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateClkGateDist::total           3512                       # Distribution of time spent in the clock gated state
+system.cpu2.pwrStateResidencyTicks::ON   855330451843                       # Cumulative time (in ticks) in various power states
+system.cpu2.pwrStateResidencyTicks::CLK_GATED 50460945238157                       # Cumulative time (in ticks) in various power states
+system.cpu2.numCycles                      1176516719                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.committedInsts                  148015275                       # Number of instructions committed
-system.cpu2.committedOps                    173576253                       # Number of ops (including micro ops) committed
-system.cpu2.discardedOps                     15019689                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu2.numFetchSuspends                     1599                       # Number of times Execute suspended instruction fetching
-system.cpu2.quiesceCycles                     5679254                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.cpi                              7.948604                       # CPI: cycles per instruction
-system.cpu2.ipc                              0.125808                       # IPC: instructions per cycle
+system.cpu2.committedInsts                  147979887                       # Number of instructions committed
+system.cpu2.committedOps                    173747082                       # Number of ops (including micro ops) committed
+system.cpu2.discardedOps                     15034502                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu2.numFetchSuspends                     1577                       # Number of times Execute suspended instruction fetching
+system.cpu2.quiesceCycles                     5675627                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.cpi                              7.950518                       # CPI: cycles per instruction
+system.cpu2.ipc                              0.125778                       # IPC: instructions per cycle
 system.cpu2.op_class_0::No_OpClass                  0      0.00%      0.00% # Class of committed instruction
-system.cpu2.op_class_0::IntAlu              120466035     69.40%     69.40% # Class of committed instruction
-system.cpu2.op_class_0::IntMult                363809      0.21%     69.61% # Class of committed instruction
-system.cpu2.op_class_0::IntDiv                  14931      0.01%     69.62% # Class of committed instruction
-system.cpu2.op_class_0::FloatAdd                    0      0.00%     69.62% # Class of committed instruction
-system.cpu2.op_class_0::FloatCmp                    0      0.00%     69.62% # Class of committed instruction
-system.cpu2.op_class_0::FloatCvt                    0      0.00%     69.62% # Class of committed instruction
-system.cpu2.op_class_0::FloatMult                   0      0.00%     69.62% # Class of committed instruction
-system.cpu2.op_class_0::FloatDiv                    0      0.00%     69.62% # Class of committed instruction
-system.cpu2.op_class_0::FloatSqrt                   0      0.00%     69.62% # Class of committed instruction
-system.cpu2.op_class_0::SimdAdd                     0      0.00%     69.62% # Class of committed instruction
-system.cpu2.op_class_0::SimdAddAcc                  0      0.00%     69.62% # Class of committed instruction
-system.cpu2.op_class_0::SimdAlu                     0      0.00%     69.62% # Class of committed instruction
-system.cpu2.op_class_0::SimdCmp                     0      0.00%     69.62% # Class of committed instruction
-system.cpu2.op_class_0::SimdCvt                     0      0.00%     69.62% # Class of committed instruction
-system.cpu2.op_class_0::SimdMisc                    0      0.00%     69.62% # Class of committed instruction
-system.cpu2.op_class_0::SimdMult                    0      0.00%     69.62% # Class of committed instruction
-system.cpu2.op_class_0::SimdMultAcc                 0      0.00%     69.62% # Class of committed instruction
-system.cpu2.op_class_0::SimdShift                   0      0.00%     69.62% # Class of committed instruction
-system.cpu2.op_class_0::SimdShiftAcc                0      0.00%     69.62% # Class of committed instruction
-system.cpu2.op_class_0::SimdSqrt                    0      0.00%     69.62% # Class of committed instruction
-system.cpu2.op_class_0::SimdFloatAdd                0      0.00%     69.62% # Class of committed instruction
-system.cpu2.op_class_0::SimdFloatAlu                0      0.00%     69.62% # Class of committed instruction
-system.cpu2.op_class_0::SimdFloatCmp                0      0.00%     69.62% # Class of committed instruction
-system.cpu2.op_class_0::SimdFloatCvt                0      0.00%     69.62% # Class of committed instruction
-system.cpu2.op_class_0::SimdFloatDiv                0      0.00%     69.62% # Class of committed instruction
-system.cpu2.op_class_0::SimdFloatMisc           14962      0.01%     69.63% # Class of committed instruction
-system.cpu2.op_class_0::SimdFloatMult               0      0.00%     69.63% # Class of committed instruction
-system.cpu2.op_class_0::SimdFloatMultAcc            0      0.00%     69.63% # Class of committed instruction
-system.cpu2.op_class_0::SimdFloatSqrt               0      0.00%     69.63% # Class of committed instruction
-system.cpu2.op_class_0::MemRead              27697831     15.96%     85.59% # Class of committed instruction
-system.cpu2.op_class_0::MemWrite             25018685     14.41%    100.00% # Class of committed instruction
+system.cpu2.op_class_0::IntAlu              120575025     69.40%     69.40% # Class of committed instruction
+system.cpu2.op_class_0::IntMult                357276      0.21%     69.60% # Class of committed instruction
+system.cpu2.op_class_0::IntDiv                  14709      0.01%     69.61% # Class of committed instruction
+system.cpu2.op_class_0::FloatAdd                    0      0.00%     69.61% # Class of committed instruction
+system.cpu2.op_class_0::FloatCmp                    0      0.00%     69.61% # Class of committed instruction
+system.cpu2.op_class_0::FloatCvt                    0      0.00%     69.61% # Class of committed instruction
+system.cpu2.op_class_0::FloatMult                   0      0.00%     69.61% # Class of committed instruction
+system.cpu2.op_class_0::FloatDiv                    0      0.00%     69.61% # Class of committed instruction
+system.cpu2.op_class_0::FloatSqrt                   0      0.00%     69.61% # Class of committed instruction
+system.cpu2.op_class_0::SimdAdd                     0      0.00%     69.61% # Class of committed instruction
+system.cpu2.op_class_0::SimdAddAcc                  0      0.00%     69.61% # Class of committed instruction
+system.cpu2.op_class_0::SimdAlu                     0      0.00%     69.61% # Class of committed instruction
+system.cpu2.op_class_0::SimdCmp                     0      0.00%     69.61% # Class of committed instruction
+system.cpu2.op_class_0::SimdCvt                     0      0.00%     69.61% # Class of committed instruction
+system.cpu2.op_class_0::SimdMisc                    0      0.00%     69.61% # Class of committed instruction
+system.cpu2.op_class_0::SimdMult                    0      0.00%     69.61% # Class of committed instruction
+system.cpu2.op_class_0::SimdMultAcc                 0      0.00%     69.61% # Class of committed instruction
+system.cpu2.op_class_0::SimdShift                   0      0.00%     69.61% # Class of committed instruction
+system.cpu2.op_class_0::SimdShiftAcc                0      0.00%     69.61% # Class of committed instruction
+system.cpu2.op_class_0::SimdSqrt                    0      0.00%     69.61% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatAdd                0      0.00%     69.61% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatAlu                0      0.00%     69.61% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatCmp                0      0.00%     69.61% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatCvt                0      0.00%     69.61% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatDiv                0      0.00%     69.61% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatMisc           16361      0.01%     69.62% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatMult               0      0.00%     69.62% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatMultAcc            0      0.00%     69.62% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatSqrt               0      0.00%     69.62% # Class of committed instruction
+system.cpu2.op_class_0::MemRead              27648708     15.91%     85.53% # Class of committed instruction
+system.cpu2.op_class_0::MemWrite             25135003     14.47%    100.00% # Class of committed instruction
 system.cpu2.op_class_0::IprAccess                   0      0.00%    100.00% # Class of committed instruction
 system.cpu2.op_class_0::InstPrefetch                0      0.00%    100.00% # Class of committed instruction
-system.cpu2.op_class_0::total               173576253                       # Class of committed instruction
+system.cpu2.op_class_0::total               173747082                       # Class of committed instruction
 system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu2.tickCycles                      278505998                       # Number of cycles that the object actually ticked
-system.cpu2.idleCycles                      898008822                       # Total number of cycles that the object has spent stopped
-system.cpu3.branchPred.lookups               76056401                       # Number of BP lookups
-system.cpu3.branchPred.condPredicted         50755289                       # Number of conditional branches predicted
-system.cpu3.branchPred.condIncorrect          3415271                       # Number of conditional branches incorrect
-system.cpu3.branchPred.BTBLookups            50793125                       # Number of BTB lookups
-system.cpu3.branchPred.BTBHits               34573256                       # Number of BTB hits
+system.cpu2.tickCycles                      278731731                       # Number of cycles that the object actually ticked
+system.cpu2.idleCycles                      897784988                       # Total number of cycles that the object has spent stopped
+system.cpu3.branchPred.lookups               76144884                       # Number of BP lookups
+system.cpu3.branchPred.condPredicted         50917651                       # Number of conditional branches predicted
+system.cpu3.branchPred.condIncorrect          3425676                       # Number of conditional branches incorrect
+system.cpu3.branchPred.BTBLookups            51078726                       # Number of BTB lookups
+system.cpu3.branchPred.BTBHits               34631446                       # Number of BTB hits
 system.cpu3.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.branchPred.BTBHitPct            68.066802                       # BTB Hit Percentage
-system.cpu3.branchPred.usedRAS                9840520                       # Number of times the RAS was used to get a target.
-system.cpu3.branchPred.RASInCorrect            107050                       # Number of incorrect RAS predictions.
-system.cpu3.branchPred.indirectLookups        3054055                       # Number of indirect predictor lookups.
-system.cpu3.branchPred.indirectHits           1548215                       # Number of indirect target hits.
-system.cpu3.branchPred.indirectMisses         1505840                       # Number of indirect misses.
-system.cpu3.branchPredindirectMispredicted       248236                       # Number of mispredicted indirect branches.
-system.cpu3.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
+system.cpu3.branchPred.BTBHitPct            67.800137                       # BTB Hit Percentage
+system.cpu3.branchPred.usedRAS                9824308                       # Number of times the RAS was used to get a target.
+system.cpu3.branchPred.RASInCorrect            106925                       # Number of incorrect RAS predictions.
+system.cpu3.branchPred.indirectLookups        2992006                       # Number of indirect predictor lookups.
+system.cpu3.branchPred.indirectHits           1537953                       # Number of indirect target hits.
+system.cpu3.branchPred.indirectMisses         1454053                       # Number of indirect misses.
+system.cpu3.branchPredindirectMispredicted       245625                       # Number of mispredicted indirect branches.
+system.cpu3.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
 system.cpu3.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1768,95 +1769,89 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu3.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu3.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu3.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu3.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.cpu3.dtb.walker.walks                   519832                       # Table walker walks requested
-system.cpu3.dtb.walker.walksLong               519832                       # Table walker walks initiated with long descriptors
-system.cpu3.dtb.walker.walksLongTerminationLevel::Level2         8563                       # Level at which table walker walks with long descriptors terminate
-system.cpu3.dtb.walker.walksLongTerminationLevel::Level3        50762                       # Level at which table walker walks with long descriptors terminate
-system.cpu3.dtb.walker.walksSquashedBefore       324579                       # Table walks squashed before starting
-system.cpu3.dtb.walker.walkWaitTime::samples       195253                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::mean  2247.443061                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::stdev 12961.897479                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::0-32767       191171     97.91%     97.91% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::32768-65535         2882      1.48%     99.39% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::65536-98303          501      0.26%     99.64% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::98304-131071          350      0.18%     99.82% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::131072-163839          155      0.08%     99.90% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::163840-196607           49      0.03%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::196608-229375           39      0.02%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::229376-262143           21      0.01%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::262144-294911           33      0.02%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::294912-327679           19      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::327680-360447            2      0.00%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::360448-393215            6      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::393216-425983           10      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::425984-458751           14      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::458752-491519            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::total       195253                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkCompletionTime::samples       240674                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::mean 22283.310619                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::gmean 18185.362858                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::stdev 16504.392629                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::0-65535       236088     98.09%     98.09% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::65536-131071         4155      1.73%     99.82% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::131072-196607          185      0.08%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::196608-262143          125      0.05%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::262144-327679           40      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::327680-393215           50      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::393216-458751           22      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::458752-524287            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::total       240674                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walksPending::samples -21483315588                       # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::mean     0.617433                       # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::0-3 -22069775588    102.73%    102.73% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::4-7    326975000     -1.52%    101.21% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::8-11    109953500     -0.51%    100.70% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::12-15     66787000     -0.31%    100.39% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::16-19     27414500     -0.13%    100.26% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::20-23     14643500     -0.07%    100.19% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::24-27     14038500     -0.07%    100.12% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::28-31     22874000     -0.11%    100.02% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::32-35      3351000     -0.02%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::36-39       112000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::40-43        25000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::44-47        22000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::48-51        17000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::52-55       205500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::56-59        41500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::total -21483315588                       # Table walker pending requests distribution
-system.cpu3.dtb.walker.walkPageSizes::4K        50762     85.57%     85.57% # Table walker page sizes translated
-system.cpu3.dtb.walker.walkPageSizes::2M         8563     14.43%    100.00% # Table walker page sizes translated
-system.cpu3.dtb.walker.walkPageSizes::total        59325                       # Table walker page sizes translated
-system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data       519832                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.cpu3.dtb.walker.walks                   512874                       # Table walker walks requested
+system.cpu3.dtb.walker.walksLong               512874                       # Table walker walks initiated with long descriptors
+system.cpu3.dtb.walker.walksLongTerminationLevel::Level2         8606                       # Level at which table walker walks with long descriptors terminate
+system.cpu3.dtb.walker.walksLongTerminationLevel::Level3        51328                       # Level at which table walker walks with long descriptors terminate
+system.cpu3.dtb.walker.walksSquashedBefore       316923                       # Table walks squashed before starting
+system.cpu3.dtb.walker.walkWaitTime::samples       195951                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::mean  2195.235033                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::stdev 13338.016362                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::0-65535       194716     99.37%     99.37% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::65536-131071          870      0.44%     99.81% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::131072-196607          208      0.11%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::196608-262143           62      0.03%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::262144-327679           47      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::327680-393215           18      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::393216-458751           23      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::458752-524287            5      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::524288-589823            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::total       195951                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkCompletionTime::samples       235338                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::mean 21271.290654                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::gmean 17097.378529                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::stdev 15945.708212                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::0-32767       189296     80.44%     80.44% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::32768-65535        41383     17.58%     98.02% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::65536-98303         3580      1.52%     99.54% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::98304-131071          595      0.25%     99.79% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::131072-163839          139      0.06%     99.85% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::163840-196607          148      0.06%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::196608-229375           80      0.03%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::229376-262143           73      0.03%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::262144-294911           24      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::327680-360447            5      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::360448-393215           11      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::393216-425983            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::458752-491519            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::total       235338                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walksPending::samples -21468826588                       # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::mean     0.564464                       # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::0-3 -22023506588    102.58%    102.58% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::4-7    315278500     -1.47%    101.12% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::8-11    105205000     -0.49%    100.63% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::12-15     64047000     -0.30%    100.33% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::16-19     24089000     -0.11%    100.21% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::20-23     11371500     -0.05%    100.16% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::24-27     12408500     -0.06%    100.10% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::28-31     18570000     -0.09%    100.02% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::32-35      3540000     -0.02%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::36-39       163500     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::40-43         7000     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::total -21468826588                       # Table walker pending requests distribution
+system.cpu3.dtb.walker.walkPageSizes::4K        51328     85.64%     85.64% # Table walker page sizes translated
+system.cpu3.dtb.walker.walkPageSizes::2M         8606     14.36%    100.00% # Table walker page sizes translated
+system.cpu3.dtb.walker.walkPageSizes::total        59934                       # Table walker page sizes translated
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data       512874                       # Table walker requests started/completed, data/inst
 system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Requested::total       519832                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data        59325                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::total       512874                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data        59934                       # Table walker requests started/completed, data/inst
 system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Completed::total        59325                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin::total       579157                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Completed::total        59934                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin::total       572808                       # Table walker requests started/completed, data/inst
 system.cpu3.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu3.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu3.dtb.read_hits                    59705170                       # DTB read hits
-system.cpu3.dtb.read_misses                    356680                       # DTB read misses
-system.cpu3.dtb.write_hits                   46676545                       # DTB write hits
-system.cpu3.dtb.write_misses                   163152                       # DTB write misses
-system.cpu3.dtb.flush_tlb                        1183                       # Number of times complete TLB was flushed
+system.cpu3.dtb.read_hits                    59857088                       # DTB read hits
+system.cpu3.dtb.read_misses                    352696                       # DTB read misses
+system.cpu3.dtb.write_hits                   46573459                       # DTB write hits
+system.cpu3.dtb.write_misses                   160178                       # DTB write misses
+system.cpu3.dtb.flush_tlb                        1182                       # Number of times complete TLB was flushed
 system.cpu3.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu3.dtb.flush_tlb_mva_asid              11749                       # Number of times TLB was flushed by MVA & ASID
-system.cpu3.dtb.flush_tlb_asid                    293                       # Number of times TLB was flushed by ASID
-system.cpu3.dtb.flush_entries                   29163                       # Number of entries that have been flushed from TLB
-system.cpu3.dtb.align_faults                       78                       # Number of TLB faults due to alignment restrictions
-system.cpu3.dtb.prefetch_faults                  4872                       # Number of TLB faults due to prefetch
+system.cpu3.dtb.flush_tlb_mva_asid              11696                       # Number of times TLB was flushed by MVA & ASID
+system.cpu3.dtb.flush_tlb_asid                    295                       # Number of times TLB was flushed by ASID
+system.cpu3.dtb.flush_entries                   29518                       # Number of entries that have been flushed from TLB
+system.cpu3.dtb.align_faults                       76                       # Number of TLB faults due to alignment restrictions
+system.cpu3.dtb.prefetch_faults                  5036                       # Number of TLB faults due to prefetch
 system.cpu3.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu3.dtb.perms_faults                    30504                       # Number of TLB faults due to permissions restrictions
-system.cpu3.dtb.read_accesses                60061850                       # DTB read accesses
-system.cpu3.dtb.write_accesses               46839697                       # DTB write accesses
+system.cpu3.dtb.perms_faults                    30761                       # Number of TLB faults due to permissions restrictions
+system.cpu3.dtb.read_accesses                60209784                       # DTB read accesses
+system.cpu3.dtb.write_accesses               46733637                       # DTB write accesses
 system.cpu3.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu3.dtb.hits                        106381715                       # DTB hits
-system.cpu3.dtb.misses                         519832                       # DTB misses
-system.cpu3.dtb.accesses                    106901547                       # DTB accesses
-system.cpu3.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
+system.cpu3.dtb.hits                        106430547                       # DTB hits
+system.cpu3.dtb.misses                         512874                       # DTB misses
+system.cpu3.dtb.accesses                    106943421                       # DTB accesses
+system.cpu3.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
 system.cpu3.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1886,393 +1881,401 @@ system.cpu3.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu3.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu3.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu3.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu3.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.cpu3.itb.walker.walks                    58984                       # Table walker walks requested
-system.cpu3.itb.walker.walksLong                58984                       # Table walker walks initiated with long descriptors
-system.cpu3.itb.walker.walksLongTerminationLevel::Level2         2019                       # Level at which table walker walks with long descriptors terminate
-system.cpu3.itb.walker.walksLongTerminationLevel::Level3        40730                       # Level at which table walker walks with long descriptors terminate
-system.cpu3.itb.walker.walksSquashedBefore         8213                       # Table walks squashed before starting
-system.cpu3.itb.walker.walkWaitTime::samples        50771                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::mean  1255.214591                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::stdev  7667.557499                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::0-32767        50302     99.08%     99.08% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::32768-65535          327      0.64%     99.72% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::65536-98303           93      0.18%     99.90% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::98304-131071           33      0.06%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::131072-163839            8      0.02%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::163840-196607            3      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::196608-229375            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::229376-262143            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::294912-327679            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.cpu3.itb.walker.walks                    59319                       # Table walker walks requested
+system.cpu3.itb.walker.walksLong                59319                       # Table walker walks initiated with long descriptors
+system.cpu3.itb.walker.walksLongTerminationLevel::Level2         2009                       # Level at which table walker walks with long descriptors terminate
+system.cpu3.itb.walker.walksLongTerminationLevel::Level3        40532                       # Level at which table walker walks with long descriptors terminate
+system.cpu3.itb.walker.walksSquashedBefore         8154                       # Table walks squashed before starting
+system.cpu3.itb.walker.walkWaitTime::samples        51165                       # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::mean  1195.836998                       # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::stdev  7646.415303                       # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::0-32767        50755     99.20%     99.20% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::32768-65535          251      0.49%     99.69% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::65536-98303           94      0.18%     99.87% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::98304-131071           39      0.08%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::131072-163839           13      0.03%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::163840-196607            9      0.02%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::196608-229375            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::229376-262143            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu3.itb.walker.walkWaitTime::327680-360447            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::360448-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::total        50771                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkCompletionTime::samples        50962                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::mean 27876.584514                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::gmean 23887.788397                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::stdev 16739.526598                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::0-65535        49958     98.03%     98.03% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::65536-131071          889      1.74%     99.77% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::131072-196607           72      0.14%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::196608-262143           26      0.05%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::262144-327679            9      0.02%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::327680-393215            7      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::total        50962                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walksPending::samples -21485924088                       # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::mean     1.063775                       # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::0     1402683284     -6.53%     -6.53% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::1   -22917683872    106.66%    100.14% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::2       26044500     -0.12%    100.01% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::3        2758500     -0.01%    100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::4         237000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::5          36500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::total -21485924088                       # Table walker pending requests distribution
-system.cpu3.itb.walker.walkPageSizes::4K        40730     95.28%     95.28% # Table walker page sizes translated
-system.cpu3.itb.walker.walkPageSizes::2M         2019      4.72%    100.00% # Table walker page sizes translated
-system.cpu3.itb.walker.walkPageSizes::total        42749                       # Table walker page sizes translated
+system.cpu3.itb.walker.walkWaitTime::total        51165                       # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkCompletionTime::samples        50695                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::mean 26787.010553                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::gmean 22469.536393                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::stdev 17840.810022                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::0-32767        30103     59.38%     59.38% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::32768-65535        19510     38.49%     97.87% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::65536-98303          511      1.01%     98.87% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::98304-131071          427      0.84%     99.72% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::131072-163839           38      0.07%     99.79% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::163840-196607           57      0.11%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::196608-229375           19      0.04%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::229376-262143            7      0.01%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::262144-294911            8      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::294912-327679            3      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::327680-360447            4      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::360448-393215            5      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::458752-491519            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::total        50695                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walksPending::samples -25766386884                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::mean     0.899092                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::stdev     0.296211                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::0    -2567658104      9.97%      9.97% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::1   -23226705280     90.14%    100.11% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::2       24531500     -0.10%    100.01% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::3        2936500     -0.01%    100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::4         267500     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::5          75500     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::6         120000     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::7          45500     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::total -25766386884                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walkPageSizes::4K        40532     95.28%     95.28% # Table walker page sizes translated
+system.cpu3.itb.walker.walkPageSizes::2M         2009      4.72%    100.00% # Table walker page sizes translated
+system.cpu3.itb.walker.walkPageSizes::total        42541                       # Table walker page sizes translated
 system.cpu3.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst        58984                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Requested::total        58984                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst        59319                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Requested::total        59319                       # Table walker requests started/completed, data/inst
 system.cpu3.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst        42749                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Completed::total        42749                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin::total       101733                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.inst_hits                    54309249                       # ITB inst hits
-system.cpu3.itb.inst_misses                     58984                       # ITB inst misses
+system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst        42541                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Completed::total        42541                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin::total       101860                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.inst_hits                    54449151                       # ITB inst hits
+system.cpu3.itb.inst_misses                     59319                       # ITB inst misses
 system.cpu3.itb.read_hits                           0                       # DTB read hits
 system.cpu3.itb.read_misses                         0                       # DTB read misses
 system.cpu3.itb.write_hits                          0                       # DTB write hits
 system.cpu3.itb.write_misses                        0                       # DTB write misses
-system.cpu3.itb.flush_tlb                        1183                       # Number of times complete TLB was flushed
+system.cpu3.itb.flush_tlb                        1182                       # Number of times complete TLB was flushed
 system.cpu3.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu3.itb.flush_tlb_mva_asid              11749                       # Number of times TLB was flushed by MVA & ASID
-system.cpu3.itb.flush_tlb_asid                    293                       # Number of times TLB was flushed by ASID
-system.cpu3.itb.flush_entries                   22226                       # Number of entries that have been flushed from TLB
+system.cpu3.itb.flush_tlb_mva_asid              11696                       # Number of times TLB was flushed by MVA & ASID
+system.cpu3.itb.flush_tlb_asid                    295                       # Number of times TLB was flushed by ASID
+system.cpu3.itb.flush_entries                   22325                       # Number of entries that have been flushed from TLB
 system.cpu3.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu3.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu3.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu3.itb.perms_faults                   110359                       # Number of TLB faults due to permissions restrictions
+system.cpu3.itb.perms_faults                   110276                       # Number of TLB faults due to permissions restrictions
 system.cpu3.itb.read_accesses                       0                       # DTB read accesses
 system.cpu3.itb.write_accesses                      0                       # DTB write accesses
-system.cpu3.itb.inst_accesses                54368233                       # ITB inst accesses
-system.cpu3.itb.hits                         54309249                       # DTB hits
-system.cpu3.itb.misses                          58984                       # DTB misses
-system.cpu3.itb.accesses                     54368233                       # DTB accesses
-system.cpu3.numPwrStateTransitions               7050                       # Number of power state transitions
-system.cpu3.pwrStateClkGateDist::samples         3525                       # Distribution of time spent in the clock gated state
-system.cpu3.pwrStateClkGateDist::mean    48150318.502695                       # Distribution of time spent in the clock gated state
-system.cpu3.pwrStateClkGateDist::stdev   1097902153.303432                       # Distribution of time spent in the clock gated state
-system.cpu3.pwrStateClkGateDist::underflows         2138     60.65%     60.65% # Distribution of time spent in the clock gated state
-system.cpu3.pwrStateClkGateDist::1000-5e+10         1387     39.35%    100.00% # Distribution of time spent in the clock gated state
+system.cpu3.itb.inst_accesses                54508470                       # ITB inst accesses
+system.cpu3.itb.hits                         54449151                       # DTB hits
+system.cpu3.itb.misses                          59319                       # DTB misses
+system.cpu3.itb.accesses                     54508470                       # DTB accesses
+system.cpu3.numPwrStateTransitions               7056                       # Number of power state transitions
+system.cpu3.pwrStateClkGateDist::samples         3528                       # Distribution of time spent in the clock gated state
+system.cpu3.pwrStateClkGateDist::mean    48263626.625000                       # Distribution of time spent in the clock gated state
+system.cpu3.pwrStateClkGateDist::stdev   1100096495.861649                       # Distribution of time spent in the clock gated state
+system.cpu3.pwrStateClkGateDist::underflows         2141     60.69%     60.69% # Distribution of time spent in the clock gated state
+system.cpu3.pwrStateClkGateDist::1000-5e+10         1387     39.31%    100.00% # Distribution of time spent in the clock gated state
 system.cpu3.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu3.pwrStateClkGateDist::max_value  36013437604                       # Distribution of time spent in the clock gated state
-system.cpu3.pwrStateClkGateDist::total           3525                       # Distribution of time spent in the clock gated state
-system.cpu3.pwrStateResidencyTicks::ON   51146531328278                       # Cumulative time (in ticks) in various power states
-system.cpu3.pwrStateResidencyTicks::CLK_GATED 169729872722                       # Cumulative time (in ticks) in various power states
-system.cpu3.numCycles                       361675800                       # number of cpu cycles simulated
+system.cpu3.pwrStateClkGateDist::max_value  36012902604                       # Distribution of time spent in the clock gated state
+system.cpu3.pwrStateClkGateDist::total           3528                       # Distribution of time spent in the clock gated state
+system.cpu3.pwrStateResidencyTicks::ON   51146001615267                       # Cumulative time (in ticks) in various power states
+system.cpu3.pwrStateResidencyTicks::CLK_GATED 170274074733                       # Cumulative time (in ticks) in various power states
+system.cpu3.numCycles                       360624311                       # number of cpu cycles simulated
 system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.fetch.icacheStallCycles         142734990                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts                     337553362                       # Number of instructions fetch has processed
-system.cpu3.fetch.Branches                   76056401                       # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches          45961991                       # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles                    197659540                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles                7720824                       # Number of cycles fetch has spent squashing
-system.cpu3.fetch.TlbCycles                   1399327                       # Number of cycles fetch has spent waiting for tlb
-system.cpu3.fetch.MiscStallCycles                5628                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu3.fetch.PendingDrainCycles             1517                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu3.fetch.PendingTrapStallCycles      2684967                       # Number of stall cycles due to pending traps
-system.cpu3.fetch.PendingQuiesceStallCycles        90171                       # Number of stall cycles due to pending quiesce instructions
-system.cpu3.fetch.IcacheWaitRetryStallCycles         3829                       # Number of stall cycles due to full MSHR
-system.cpu3.fetch.CacheLines                 54181818                       # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes              2125134                       # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.ItlbSquashes                  22298                       # Number of outstanding ITLB misses that were squashed
-system.cpu3.fetch.rateDist::samples         348440253                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean             1.132379                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev            2.378502                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.icacheStallCycles         142734409                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts                     337961407                       # Number of instructions fetch has processed
+system.cpu3.fetch.Branches                   76144884                       # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches          45993707                       # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles                    196711593                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles                7739189                       # Number of cycles fetch has spent squashing
+system.cpu3.fetch.TlbCycles                   1372744                       # Number of cycles fetch has spent waiting for tlb
+system.cpu3.fetch.MiscStallCycles                5006                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu3.fetch.PendingDrainCycles             1830                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu3.fetch.PendingTrapStallCycles      2692575                       # Number of stall cycles due to pending traps
+system.cpu3.fetch.PendingQuiesceStallCycles        88196                       # Number of stall cycles due to pending quiesce instructions
+system.cpu3.fetch.IcacheWaitRetryStallCycles         3852                       # Number of stall cycles due to full MSHR
+system.cpu3.fetch.CacheLines                 54321925                       # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes              2128480                       # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.ItlbSquashes                  22518                       # Number of outstanding ITLB misses that were squashed
+system.cpu3.fetch.rateDist::samples         347479672                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean             1.136573                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev            2.381700                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0               265738138     76.27%     76.27% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1                10408686      2.99%     79.25% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2                10350946      2.97%     82.22% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3                 7718330      2.22%     84.44% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4                15611358      4.48%     88.92% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5                 5061575      1.45%     90.37% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6                 5537323      1.59%     91.96% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7                 4787480      1.37%     93.33% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8                23226417      6.67%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0               264664577     76.17%     76.17% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1                10448751      3.01%     79.17% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2                10389657      2.99%     82.16% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3                 7726776      2.22%     84.39% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4                15569597      4.48%     88.87% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5                 5085732      1.46%     90.33% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6                 5566487      1.60%     91.93% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7                 4803146      1.38%     93.32% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8                23224949      6.68%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total           348440253                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate                 0.210289                       # Number of branch fetches per cycle
-system.cpu3.fetch.rate                       0.933304                       # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles               116402482                       # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles            160353660                       # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles                 61341979                       # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles              7283918                       # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles               3056510                       # Number of cycles decode is squashing
-system.cpu3.decode.BranchResolved            11212857                       # Number of times decode resolved a branch
-system.cpu3.decode.BranchMispred               815162                       # Number of times decode detected a branch misprediction
-system.cpu3.decode.DecodedInsts             368532981                       # Number of instructions handled by decode
-system.cpu3.decode.SquashedInsts              2520228                       # Number of squashed instructions handled by decode
-system.cpu3.rename.SquashCycles               3056510                       # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles               120624207                       # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles               11509026                       # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles     131064171                       # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles                 64320905                       # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles             17863677                       # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts             359702121                       # Number of instructions processed by rename
-system.cpu3.rename.ROBFullEvents                43833                       # Number of times rename has blocked due to ROB full
-system.cpu3.rename.IQFullEvents                968665                       # Number of times rename has blocked due to IQ full
-system.cpu3.rename.LQFullEvents                780315                       # Number of times rename has blocked due to LQ full
-system.cpu3.rename.SQFullEvents               7689356                       # Number of times rename has blocked due to SQ full
-system.cpu3.rename.FullRegisterEvents            2098                       # Number of times there has been no free registers
-system.cpu3.rename.RenamedOperands          342552995                       # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups            547002223                       # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups       423527131                       # Number of integer rename lookups
-system.cpu3.rename.fp_rename_lookups           526597                       # Number of floating rename lookups
-system.cpu3.rename.CommittedMaps            286388562                       # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps                56164428                       # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts           8049002                       # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts       6906783                       # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts                 40039981                       # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads            58078564                       # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores           48988354                       # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads          7585006                       # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores         8037000                       # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded                 341408601                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded            8081994                       # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued                340240717                       # Number of instructions issued
-system.cpu3.iq.iqSquashedInstsIssued           497823                       # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined       47426361                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined     29768333                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved        191877                       # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples    348440253                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean        0.976468                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev       1.690233                       # Number of insts issued each cycle
+system.cpu3.fetch.rateDist::total           347479672                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate                 0.211147                       # Number of branch fetches per cycle
+system.cpu3.fetch.rate                       0.937156                       # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles               116319092                       # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles            159338087                       # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles                 61493208                       # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles              7257195                       # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles               3070348                       # Number of cycles decode is squashing
+system.cpu3.decode.BranchResolved            11216097                       # Number of times decode resolved a branch
+system.cpu3.decode.BranchMispred               810528                       # Number of times decode detected a branch misprediction
+system.cpu3.decode.DecodedInsts             368877230                       # Number of instructions handled by decode
+system.cpu3.decode.SquashedInsts              2502393                       # Number of squashed instructions handled by decode
+system.cpu3.rename.SquashCycles               3070348                       # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles               120537316                       # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles               11607372                       # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles     129961960                       # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles                 64445904                       # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles             17854957                       # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts             360009684                       # Number of instructions processed by rename
+system.cpu3.rename.ROBFullEvents                40582                       # Number of times rename has blocked due to ROB full
+system.cpu3.rename.IQFullEvents                995330                       # Number of times rename has blocked due to IQ full
+system.cpu3.rename.LQFullEvents                792465                       # Number of times rename has blocked due to LQ full
+system.cpu3.rename.SQFullEvents               7726817                       # Number of times rename has blocked due to SQ full
+system.cpu3.rename.FullRegisterEvents            2104                       # Number of times there has been no free registers
+system.cpu3.rename.RenamedOperands          342963420                       # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups            547080576                       # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups       423978365                       # Number of integer rename lookups
+system.cpu3.rename.fp_rename_lookups           517857                       # Number of floating rename lookups
+system.cpu3.rename.CommittedMaps            286215822                       # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps                56747593                       # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts           7972839                       # count of serializing insts renamed
+system.cpu3.rename.tempSerializingInsts       6835897                       # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts                 39855447                       # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads            58319848                       # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores           48888042                       # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads          7618365                       # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores         8042184                       # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded                 341704043                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded            8022599                       # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued                340232336                       # Number of instructions issued
+system.cpu3.iq.iqSquashedInstsIssued           497337                       # Number of squashed instructions issued
+system.cpu3.iq.iqSquashedInstsExamined       47823760                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined     30164946                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedNonSpecRemoved        192380                       # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.issued_per_cycle::samples    347479672                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean        0.979143                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev       1.691890                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0          216890475     62.25%     62.25% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1           53877096     15.46%     77.71% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2           24807816      7.12%     84.83% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3           17922235      5.14%     89.97% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4           13075143      3.75%     93.72% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5            9287871      2.67%     96.39% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6            6359964      1.83%     98.22% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::7            3675651      1.05%     99.27% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::8            2544002      0.73%    100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0          216057167     62.18%     62.18% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1           53646928     15.44%     77.62% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2           24868918      7.16%     84.77% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3           17968855      5.17%     89.95% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4           13078366      3.76%     93.71% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5            9279622      2.67%     96.38% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6            6367435      1.83%     98.21% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7            3674225      1.06%     99.27% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::8            2538156      0.73%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total      348440253                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total      347479672                       # Number of insts issued each cycle
 system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu                1734447     26.04%     26.04% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult                 17043      0.26%     26.30% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv                   1093      0.02%     26.31% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd                    0      0.00%     26.31% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp                    0      0.00%     26.31% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt                    0      0.00%     26.31% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult                   0      0.00%     26.31% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv                    0      0.00%     26.31% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%     26.31% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd                     0      0.00%     26.31% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%     26.31% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu                     0      0.00%     26.31% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp                     0      0.00%     26.31% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt                     0      0.00%     26.31% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc                    0      0.00%     26.31% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult                    0      0.00%     26.31% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%     26.31% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift                   0      0.00%     26.31% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%     26.31% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%     26.31% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%     26.31% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%     26.31% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%     26.31% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%     26.31% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%     26.31% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%     26.31% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%     26.31% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%     26.31% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%     26.31% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead               2643216     39.68%     66.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite              2264697     34.00%    100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu                1739394     26.12%     26.12% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult                 17216      0.26%     26.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv                   1075      0.02%     26.40% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd                    0      0.00%     26.40% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp                    0      0.00%     26.40% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt                    0      0.00%     26.40% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult                   0      0.00%     26.40% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv                    0      0.00%     26.40% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%     26.40% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd                     0      0.00%     26.40% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%     26.40% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu                     0      0.00%     26.40% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp                     0      0.00%     26.40% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt                     0      0.00%     26.40% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc                    0      0.00%     26.40% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult                    0      0.00%     26.40% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%     26.40% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift                   0      0.00%     26.40% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%     26.40% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%     26.40% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%     26.40% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%     26.40% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%     26.40% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%     26.40% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%     26.40% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%     26.40% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%     26.40% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%     26.40% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%     26.40% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead               2643113     39.69%     66.09% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite              2258125     33.91%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu3.iq.FU_type_0::No_OpClass               10      0.00%      0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu            231030792     67.90%     67.90% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult              845869      0.25%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntDiv                38944      0.01%     68.16% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatAdd                198      0.00%     68.16% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     68.16% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     68.16% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     68.16% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     68.16% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     68.16% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     68.16% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     68.16% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     68.16% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     68.16% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     68.16% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     68.16% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     68.16% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     68.16% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     68.16% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.16% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     68.16% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.16% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.16% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.16% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.16% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.16% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc         42651      0.01%     68.17% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     68.17% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.17% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.17% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead            61002567     17.93%     86.10% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite           47279686     13.90%    100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::No_OpClass                5      0.00%      0.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu            230928850     67.87%     67.87% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntMult              888251      0.26%     68.13% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntDiv                40201      0.01%     68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd                204      0.00%     68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc         42408      0.01%     68.16% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     68.16% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.16% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.16% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead            61160195     17.98%     86.14% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite           47172222     13.86%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total             340240717                       # Type of FU issued
-system.cpu3.iq.rate                          0.940734                       # Inst issue rate
-system.cpu3.iq.fu_busy_cnt                    6660496                       # FU busy when requested
-system.cpu3.iq.fu_busy_rate                  0.019576                       # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads        1035420885                       # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes        396967626                       # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses    327898797                       # Number of integer instruction queue wakeup accesses
-system.cpu3.iq.fp_inst_queue_reads             659121                       # Number of floating instruction queue reads
-system.cpu3.iq.fp_inst_queue_writes            337856                       # Number of floating instruction queue writes
-system.cpu3.iq.fp_inst_queue_wakeup_accesses       293479                       # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses             346548979                       # Number of integer alu accesses
-system.cpu3.iq.fp_alu_accesses                 352224                       # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads         2687529                       # Number of loads that had data forwarded from stores
+system.cpu3.iq.FU_type_0::total             340232336                       # Type of FU issued
+system.cpu3.iq.rate                          0.943454                       # Inst issue rate
+system.cpu3.iq.fu_busy_cnt                    6658923                       # FU busy when requested
+system.cpu3.iq.fu_busy_rate                  0.019572                       # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads        1034449548                       # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes        397601121                       # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses    327921647                       # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.fp_inst_queue_reads             651056                       # Number of floating instruction queue reads
+system.cpu3.iq.fp_inst_queue_writes            333937                       # Number of floating instruction queue writes
+system.cpu3.iq.fp_inst_queue_wakeup_accesses       289983                       # Number of floating instruction queue wakeup accesses
+system.cpu3.iq.int_alu_accesses             346543457                       # Number of integer alu accesses
+system.cpu3.iq.fp_alu_accesses                 347797                       # Number of floating point alu accesses
+system.cpu3.iew.lsq.thread0.forwLoads         2684612                       # Number of loads that had data forwarded from stores
 system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads      9720232                       # Number of loads squashed
-system.cpu3.iew.lsq.thread0.ignoredResponses        11871                       # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation       394856                       # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores      4837016                       # Number of stores squashed
+system.cpu3.iew.lsq.thread0.squashedLoads      9848030                       # Number of loads squashed
+system.cpu3.iew.lsq.thread0.ignoredResponses        12099                       # Number of memory responses ignored because the instruction is squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation       390855                       # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores      4852885                       # Number of stores squashed
 system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu3.iew.lsq.thread0.rescheduledLoads      2125891                       # Number of loads that were rescheduled
-system.cpu3.iew.lsq.thread0.cacheBlocked      3923806                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu3.iew.lsq.thread0.rescheduledLoads      2121686                       # Number of loads that were rescheduled
+system.cpu3.iew.lsq.thread0.cacheBlocked      3886704                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles               3056510                       # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles                7986555                       # Number of cycles IEW is blocking
-system.cpu3.iew.iewUnblockCycles              2673304                       # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts          349575098                       # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts          1017291                       # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts             58078564                       # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts            48988354                       # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts           6756692                       # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents                121038                       # Number of times the IQ has become full, causing a stall
-system.cpu3.iew.iewLSQFullEvents              2506923                       # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents        394856                       # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect       1446513                       # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect      1609649                       # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts             3056162                       # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts            336167665                       # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts             59696171                       # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts          3560031                       # Number of squashed instructions skipped in execute
+system.cpu3.iew.iewSquashCycles               3070348                       # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles                8044361                       # Number of cycles IEW is blocking
+system.cpu3.iew.iewUnblockCycles              2703635                       # Number of cycles IEW is unblocking
+system.cpu3.iew.iewDispatchedInsts          349811697                       # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts          1019337                       # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts             58319848                       # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts            48888042                       # Number of dispatched store instructions
+system.cpu3.iew.iewDispNonSpecInsts           6684338                       # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewIQFullEvents                123262                       # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewLSQFullEvents              2534169                       # Number of times the LSQ has become full, causing a stall
+system.cpu3.iew.memOrderViolationEvents        390855                       # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect       1464138                       # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect      1603865                       # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts             3068003                       # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts            336172243                       # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts             59848506                       # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts          3553985                       # Number of squashed instructions skipped in execute
 system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu3.iew.exec_nop                        84503                       # number of nop insts executed
-system.cpu3.iew.exec_refs                   106371515                       # number of memory reference insts executed
-system.cpu3.iew.exec_branches                62288679                       # Number of branches executed
-system.cpu3.iew.exec_stores                  46675344                       # Number of stores executed
-system.cpu3.iew.exec_rate                    0.929472                       # Inst execution rate
-system.cpu3.iew.wb_sent                     329005088                       # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count                    328192276                       # cumulative count of insts written-back
-system.cpu3.iew.wb_producers                162018804                       # num instructions producing a value
-system.cpu3.iew.wb_consumers                281033502                       # num instructions consuming a value
-system.cpu3.iew.wb_rate                      0.907421                       # insts written-back per cycle
-system.cpu3.iew.wb_fanout                    0.576511                       # average fanout of values written-back
-system.cpu3.commit.commitSquashedInsts       47454465                       # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls        7890117                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.branchMispredicts          2611241                       # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples    340404707                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean     0.887368                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev     1.879512                       # Number of insts commited each cycle
+system.cpu3.iew.exec_nop                        85055                       # number of nop insts executed
+system.cpu3.iew.exec_refs                   106421072                       # number of memory reference insts executed
+system.cpu3.iew.exec_branches                62316621                       # Number of branches executed
+system.cpu3.iew.exec_stores                  46572566                       # Number of stores executed
+system.cpu3.iew.exec_rate                    0.932195                       # Inst execution rate
+system.cpu3.iew.wb_sent                     329026261                       # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count                    328211630                       # cumulative count of insts written-back
+system.cpu3.iew.wb_producers                162144042                       # num instructions producing a value
+system.cpu3.iew.wb_consumers                281134898                       # num instructions consuming a value
+system.cpu3.iew.wb_rate                      0.910121                       # insts written-back per cycle
+system.cpu3.iew.wb_fanout                    0.576748                       # average fanout of values written-back
+system.cpu3.commit.commitSquashedInsts       47849721                       # The number of squashed insts skipped by commit
+system.cpu3.commit.commitNonSpecStalls        7830219                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.branchMispredicts          2626302                       # The number of times a branch was mispredicted
+system.cpu3.commit.committed_per_cycle::samples    339381548                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean     0.889568                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev     1.882377                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0    230935782     67.84%     67.84% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1     52807469     15.51%     83.35% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2     18991951      5.58%     88.93% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3      8773061      2.58%     91.51% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4      6429800      1.89%     93.40% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5      3748451      1.10%     94.50% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6      3528982      1.04%     95.54% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7      2195360      0.64%     96.18% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::8     12993851      3.82%    100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0    230141242     67.81%     67.81% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1     52578609     15.49%     83.30% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2     18989562      5.60%     88.90% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3      8770494      2.58%     91.48% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4      6420925      1.89%     93.38% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5      3757747      1.11%     94.48% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6      3513397      1.04%     95.52% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7      2195731      0.65%     96.17% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::8     13013841      3.83%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total    340404707                       # Number of insts commited each cycle
-system.cpu3.commit.committedInsts           257000704                       # Number of instructions committed
-system.cpu3.commit.committedOps             302064229                       # Number of ops (including micro ops) committed
+system.cpu3.commit.committed_per_cycle::total    339381548                       # Number of insts commited each cycle
+system.cpu3.commit.committedInsts           256941031                       # Number of instructions committed
+system.cpu3.commit.committedOps             301902877                       # Number of ops (including micro ops) committed
 system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu3.commit.refs                      92509669                       # Number of memory references committed
-system.cpu3.commit.loads                     48358331                       # Number of loads committed
-system.cpu3.commit.membars                    2078465                       # Number of memory barriers committed
-system.cpu3.commit.branches                  57378073                       # Number of branches committed
-system.cpu3.commit.fp_insts                    281556                       # Number of committed floating point instructions.
-system.cpu3.commit.int_insts                277690269                       # Number of committed integer instructions.
-system.cpu3.commit.function_calls             7642177                       # Number of function calls committed.
+system.cpu3.commit.refs                      92506974                       # Number of memory references committed
+system.cpu3.commit.loads                     48471817                       # Number of loads committed
+system.cpu3.commit.membars                    2097304                       # Number of memory barriers committed
+system.cpu3.commit.branches                  57364518                       # Number of branches committed
+system.cpu3.commit.fp_insts                    278173                       # Number of committed floating point instructions.
+system.cpu3.commit.int_insts                277550130                       # Number of committed integer instructions.
+system.cpu3.commit.function_calls             7627094                       # Number of function calls committed.
 system.cpu3.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntAlu       208831181     69.13%     69.13% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntMult         657786      0.22%     69.35% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntDiv           28932      0.01%     69.36% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     69.36% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     69.36% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     69.36% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatMult            0      0.00%     69.36% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     69.36% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     69.36% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     69.36% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     69.36% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     69.36% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     69.36% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     69.36% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     69.36% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMult             0      0.00%     69.36% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     69.36% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShift            0      0.00%     69.36% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     69.36% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     69.36% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     69.36% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     69.36% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     69.36% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     69.36% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     69.36% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMisc        36661      0.01%     69.37% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     69.37% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.37% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.37% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemRead       48358331     16.01%     85.38% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemWrite      44151338     14.62%    100.00% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntAlu       208647320     69.11%     69.11% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntMult         682317      0.23%     69.34% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntDiv           29904      0.01%     69.35% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     69.35% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     69.35% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     69.35% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatMult            0      0.00%     69.35% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     69.35% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     69.35% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     69.35% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     69.35% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     69.35% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     69.35% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     69.35% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     69.35% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMult             0      0.00%     69.35% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     69.35% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShift            0      0.00%     69.35% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     69.35% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     69.35% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     69.35% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     69.35% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     69.35% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     69.35% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     69.35% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMisc        36362      0.01%     69.36% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     69.36% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.36% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.36% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemRead       48471817     16.06%     85.41% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemWrite      44035157     14.59%    100.00% # Class of committed instruction
 system.cpu3.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu3.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::total        302064229                       # Class of committed instruction
-system.cpu3.commit.bw_lim_events             12993851                       # number cycles where commit BW limit reached
-system.cpu3.rob.rob_reads                   674816220                       # The number of ROB reads
-system.cpu3.rob.rob_writes                  707084678                       # The number of ROB writes
-system.cpu3.timesIdled                        2433054                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles                       13235547                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu3.quiesceCycles                 98724531811                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts                  257000704                       # Number of Instructions Simulated
-system.cpu3.committedOps                    302064229                       # Number of Ops (including micro ops) Simulated
-system.cpu3.cpi                              1.407295                       # CPI: Cycles Per Instruction
-system.cpu3.cpi_total                        1.407295                       # CPI: Total CPI of All Threads
-system.cpu3.ipc                              0.710583                       # IPC: Instructions Per Cycle
-system.cpu3.ipc_total                        0.710583                       # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads               395540710                       # number of integer regfile reads
-system.cpu3.int_regfile_writes              235084371                       # number of integer regfile writes
-system.cpu3.fp_regfile_reads                   573493                       # number of floating regfile reads
-system.cpu3.fp_regfile_writes                  349924                       # number of floating regfile writes
-system.cpu3.cc_regfile_reads                 70842645                       # number of cc regfile reads
-system.cpu3.cc_regfile_writes                71511543                       # number of cc regfile writes
-system.cpu3.misc_regfile_reads              658562640                       # number of misc regfile reads
-system.cpu3.misc_regfile_writes               7924534                       # number of misc regfile writes
-system.iobus.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq                40262                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40262                       # Transaction distribution
+system.cpu3.commit.op_class_0::total        301902877                       # Class of committed instruction
+system.cpu3.commit.bw_lim_events             13013841                       # number cycles where commit BW limit reached
+system.cpu3.rob.rob_reads                   673991782                       # The number of ROB reads
+system.cpu3.rob.rob_writes                  707616779                       # The number of ROB writes
+system.cpu3.timesIdled                        2425895                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.idleCycles                       13144639                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.quiesceCycles                 98725614751                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu3.committedInsts                  256941031                       # Number of Instructions Simulated
+system.cpu3.committedOps                    301902877                       # Number of Ops (including micro ops) Simulated
+system.cpu3.cpi                              1.403529                       # CPI: Cycles Per Instruction
+system.cpu3.cpi_total                        1.403529                       # CPI: Total CPI of All Threads
+system.cpu3.ipc                              0.712489                       # IPC: Instructions Per Cycle
+system.cpu3.ipc_total                        0.712489                       # IPC: Total IPC of All Threads
+system.cpu3.int_regfile_reads               395604640                       # number of integer regfile reads
+system.cpu3.int_regfile_writes              235195836                       # number of integer regfile writes
+system.cpu3.fp_regfile_reads                   565870                       # number of floating regfile reads
+system.cpu3.fp_regfile_writes                  351196                       # number of floating regfile writes
+system.cpu3.cc_regfile_reads                 70807437                       # number of cc regfile reads
+system.cpu3.cc_regfile_writes                71493240                       # number of cc regfile writes
+system.cpu3.misc_regfile_reads              657110629                       # number of misc regfile reads
+system.cpu3.misc_regfile_writes               7862543                       # number of misc regfile writes
+system.iobus.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.iobus.trans_dist::ReadReq                40272                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40272                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136539                       # Transaction distribution
 system.iobus.trans_dist::WriteResp             136539                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47694                       # Packet count per connected master and slave (bytes)
@@ -2289,11 +2292,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122576                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230946                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230946                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230966                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230966                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353602                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353622                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47714                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
@@ -2308,22 +2311,22 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155706                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334216                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334216                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334296                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334296                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492008                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             13479500                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7492088                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             13499000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                 5000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                 5500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                17000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy                17500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer3.occupancy                11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy                 9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy                9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer13.occupancy               11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
@@ -2335,68 +2338,68 @@ system.iobus.reqLayer16.occupancy                5000                       # La
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy               11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            10717000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            10442000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            21643000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            21712500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           229106103                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           227539905                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            40091000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            39848000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            47420000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            45034000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements               115455                       # number of replacements
-system.iocache.tags.tagsinuse               10.425438                       # Cycle average of tags in use
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.replacements               115465                       # number of replacements
+system.iocache.tags.tagsinuse               10.425444                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115471                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115481                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13087296764009                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.544648                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.880790                       # Average occupied blocks per requestor
+system.iocache.tags.warmup_cycle         13087293844009                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.544651                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.880792                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::realview.ethernet     0.221541                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.430049                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.430050                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.651590                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039614                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039614                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.tag_accesses              1039704                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039704                       # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8809                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8846                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8819                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8856                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide       115473                       # number of demand (read+write) misses
-system.iocache.demand_misses::total            115513                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide       115483                       # number of demand (read+write) misses
+system.iocache.demand_misses::total            115523                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide       115473                       # number of overall misses
-system.iocache.overall_misses::total           115513                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide    148237434                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    148237434                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   5184314669                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   5184314669                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide   5332552103                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   5332552103                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide   5332552103                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   5332552103                       # number of overall miss cycles
+system.iocache.overall_misses::realview.ide       115483                       # number of overall misses
+system.iocache.overall_misses::total           115523                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide     61770218                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     61770218                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   5167926687                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   5167926687                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide   5229696905                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   5229696905                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide   5229696905                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   5229696905                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8809                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8846                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8819                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8856                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide       115473                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total          115513                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide       115483                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total          115523                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide       115473                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total         115513                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide       115483                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total         115523                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -2410,861 +2413,862 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 16827.952549                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 16757.566584                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 48604.165126                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 48604.165126                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 46180.077620                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 46164.086319                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 46180.077620                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 46164.086319                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs          2296                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide  7004.220206                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total  6974.956865                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 48450.523954                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 48450.523954                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 45285.426470                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 45269.746328                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 45285.426470                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 45269.746328                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs           417                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                  267                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                   40                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     8.599251                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    10.425000                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.writebacks::writebacks          106631                       # number of writebacks
 system.iocache.writebacks::total               106631                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ide          910                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          910                       # number of ReadReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::realview.ide        43872                       # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total        43872                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide        44782                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        44782                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide        44782                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        44782                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide    102737434                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total    102737434                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2987814984                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2987814984                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   3090552418                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   3090552418                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   3090552418                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   3090552418                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::realview.ide     0.103303                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total     0.102871                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.411310                       # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total     0.411310                       # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::realview.ide     0.387814                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     0.387679                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::realview.ide     0.387814                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     0.387679                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112898.279121                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 112898.279121                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68103.003829                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68103.003829                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 69013.273592                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 69013.273592                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 69013.273592                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 69013.273592                       # average overall mshr miss latency
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements                  1178177                       # number of replacements
-system.l2c.tags.tagsinuse                65299.544871                       # Cycle average of tags in use
-system.l2c.tags.total_refs                   47783107                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1240954                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    38.505140                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                395986000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   36300.809857                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   130.329243                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   195.620388                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3095.266131                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data    10240.571353                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker    40.874592                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker    51.867132                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     1035.336911                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     2451.400254                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker    46.677403                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.itb.walker    75.693349                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst     2509.241112                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data     3335.896210                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.dtb.walker    90.056966                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.itb.walker   140.583636                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst     1763.583672                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data     3795.736663                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.553906                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001989                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.002985                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.047230                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.156259                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000624                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.000791                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.015798                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.037405                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000712                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.itb.walker     0.001155                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.038288                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.050902                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.dtb.walker     0.001374                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.itb.walker     0.002145                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst       0.026910                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.data       0.057918                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.996392                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023          349                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        62428                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          348                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          102                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          625                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2851                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5174                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        53676                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.005325                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.952576                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                423034153                       # Number of tag accesses
-system.l2c.tags.data_accesses               423034153                       # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.l2c.ReadReq_hits::cpu0.dtb.walker       166077                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker       112464                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker        54587                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker        40813                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.dtb.walker       152672                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.itb.walker        58108                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.dtb.walker       295679                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.itb.walker       104923                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                 985323                       # number of ReadReq hits
-system.l2c.WritebackDirty_hits::writebacks      7576706                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total         7576706                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks     15883082                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total        15883082                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data            3816                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data            1201                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data            1641                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu3.data            2839                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                9497                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu3.data             9                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                 9                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           631099                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data           192720                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data           285985                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu3.data           475632                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total              1585436                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst       5464021                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst       1712423                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu2.inst       3852354                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu3.inst       4762402                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total          15791200                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data      2579009                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       769324                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu2.data      1050953                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu3.data      1900864                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total          6300150                       # number of ReadSharedReq hits
-system.l2c.InvalidateReq_hits::cpu0.data       286592                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::cpu1.data        87209                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::cpu2.data       126708                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::cpu3.data       229462                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::total           729971                       # number of InvalidateReq hits
-system.l2c.demand_hits::cpu0.dtb.walker        166077                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker        112464                       # number of demand (read+write) hits
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-system.l2c.demand_hits::cpu1.dtb.walker         54587                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker         40813                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst             1712423                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              962044                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.dtb.walker        152672                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.itb.walker         58108                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst             3852354                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data             1336938                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.dtb.walker        295679                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.itb.walker        104923                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.inst             4762402                       # number of demand (read+write) hits
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-system.l2c.demand_hits::total                24662109                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker       166077                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker       112464                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst            5464021                       # number of overall hits
-system.l2c.overall_hits::cpu0.data            3210108                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker        54587                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker        40813                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst            1712423                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             962044                       # number of overall hits
-system.l2c.overall_hits::cpu2.dtb.walker       152672                       # number of overall hits
-system.l2c.overall_hits::cpu2.itb.walker        58108                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst            3852354                       # number of overall hits
-system.l2c.overall_hits::cpu2.data            1336938                       # number of overall hits
-system.l2c.overall_hits::cpu3.dtb.walker       295679                       # number of overall hits
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-system.l2c.overall_hits::cpu3.inst            4762402                       # number of overall hits
-system.l2c.overall_hits::cpu3.data            2376496                       # number of overall hits
-system.l2c.overall_hits::total               24662109                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker         1397                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker         1376                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker          307                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker          291                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.dtb.walker          530                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.itb.walker          481                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.dtb.walker         1161                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.itb.walker          997                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                 6540                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data         13913                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          4659                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data          5652                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3.data         10300                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             34524                       # number of UpgradeReq misses
+system.iocache.ReadReq_mshr_misses::realview.ide          453                       # number of ReadReq MSHR misses
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+system.iocache.WriteLineReq_mshr_misses::realview.ide        43744                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total        43744                       # number of WriteLineReq MSHR misses
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+system.iocache.overall_mshr_misses::total        44197                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     39120218                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     39120218                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2977819124                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2977819124                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   3016939342                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   3016939342                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   3016939342                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   3016939342                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::realview.ide     0.051366                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total     0.051152                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.410110                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total     0.410110                       # mshr miss rate for WriteLineReq accesses
+system.iocache.demand_mshr_miss_rate::realview.ide     0.382714                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     0.382582                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::realview.ide     0.382714                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     0.382582                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 86358.097130                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 86358.097130                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68073.772952                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68073.772952                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 68261.179311                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 68261.179311                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 68261.179311                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 68261.179311                       # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.l2c.tags.replacements                  1182494                       # number of replacements
+system.l2c.tags.tagsinuse                65447.621193                       # Cycle average of tags in use
+system.l2c.tags.total_refs                   49776356                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1245426                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    39.967333                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle                395496000                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   10450.326675                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker   193.502647                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   222.666592                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3323.622390                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data    21949.117178                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker    56.686764                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker    60.274211                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      949.191230                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     6589.162943                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.dtb.walker    69.129700                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.itb.walker    76.155286                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst     2308.881020                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data     7819.148817                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.dtb.walker   140.556158                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.itb.walker   161.169200                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.inst     1712.244141                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.data     9365.786241                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.159459                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002953                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.003398                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.050714                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.334917                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000865                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.000920                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.014484                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.100543                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.dtb.walker     0.001055                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.itb.walker     0.001162                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst       0.035231                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data       0.119311                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.dtb.walker     0.002145                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.itb.walker     0.002459                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.inst       0.026127                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.data       0.142911                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.998651                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023          384                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        62548                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          384                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0          106                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          328                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         1131                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         5605                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        55378                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023     0.005859                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.954407                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                420660189                       # Number of tag accesses
+system.l2c.tags.data_accesses               420660189                       # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.l2c.ReadReq_hits::cpu0.dtb.walker       148411                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker       102905                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker        50987                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker        37863                       # number of ReadReq hits
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+system.l2c.ReadReq_hits::cpu2.itb.walker        53387                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu3.dtb.walker       286140                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu3.itb.walker        98751                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                 924113                       # number of ReadReq hits
+system.l2c.WritebackDirty_hits::writebacks      7580739                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total         7580739                       # number of WritebackDirty hits
+system.l2c.WritebackClean_hits::writebacks     15897541                       # number of WritebackClean hits
+system.l2c.WritebackClean_hits::total        15897541                       # number of WritebackClean hits
+system.l2c.UpgradeReq_hits::cpu0.data           10116                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data            3190                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu2.data            4337                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu3.data            7288                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total               24931                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu3.data             5                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                 5                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data           624653                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data           203950                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu2.data           287508                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu3.data           472182                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total              1588293                       # number of ReadExReq hits
+system.l2c.ReadCleanReq_hits::cpu0.inst       5476670                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu1.inst       1691493                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu2.inst       3883882                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu3.inst       4752795                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::total          15804840                       # number of ReadCleanReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data      2544942                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data       782243                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu2.data      1049975                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu3.data      1919039                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total          6296199                       # number of ReadSharedReq hits
+system.l2c.InvalidateReq_hits::cpu0.data       281232                       # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::cpu1.data        93381                       # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::cpu2.data       121660                       # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::cpu3.data       233276                       # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::total           729549                       # number of InvalidateReq hits
+system.l2c.demand_hits::cpu0.dtb.walker        148411                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker        102905                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst             5476670                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data             3169595                       # number of demand (read+write) hits
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+system.l2c.demand_hits::cpu1.data              986193                       # number of demand (read+write) hits
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+system.l2c.demand_hits::cpu3.dtb.walker        286140                       # number of demand (read+write) hits
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+system.l2c.demand_hits::cpu3.inst             4752795                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.data             2391221                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                24613445                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker       148411                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker       102905                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst            5476670                       # number of overall hits
+system.l2c.overall_hits::cpu0.data            3169595                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker        50987                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker        37863                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst            1691493                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             986193                       # number of overall hits
+system.l2c.overall_hits::cpu2.dtb.walker       145669                       # number of overall hits
+system.l2c.overall_hits::cpu2.itb.walker        53387                       # number of overall hits
+system.l2c.overall_hits::cpu2.inst            3883882                       # number of overall hits
+system.l2c.overall_hits::cpu2.data            1337483                       # number of overall hits
+system.l2c.overall_hits::cpu3.dtb.walker       286140                       # number of overall hits
+system.l2c.overall_hits::cpu3.itb.walker        98751                       # number of overall hits
+system.l2c.overall_hits::cpu3.inst            4752795                       # number of overall hits
+system.l2c.overall_hits::cpu3.data            2391221                       # number of overall hits
+system.l2c.overall_hits::total               24613445                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.dtb.walker         1348                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.itb.walker         1354                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.dtb.walker          352                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.itb.walker          297                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.dtb.walker          499                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.itb.walker          459                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu3.dtb.walker         1269                       # number of ReadReq misses
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+system.l2c.ReadReq_misses::total                 6633                       # number of ReadReq misses
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+system.l2c.UpgradeReq_misses::cpu2.data           628                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu3.data          1231                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              3860                       # number of UpgradeReq misses
 system.l2c.SCUpgradeReq_misses::cpu3.data            2                       # number of SCUpgradeReq misses
 system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         182222                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          51154                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data          71437                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3.data         110233                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             415046                       # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst        33022                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu1.inst        10176                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu2.inst        26498                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu3.inst        25154                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::total           94850                       # number of ReadCleanReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       118847                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data        31555                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu2.data        39925                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu3.data        68999                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         259326                       # number of ReadSharedReq misses
-system.l2c.InvalidateReq_misses::cpu0.data       372466                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::cpu1.data        21824                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::cpu2.data        29664                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::cpu3.data        71909                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::total         495863                       # number of InvalidateReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         1397                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         1376                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             33022                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            301069                       # number of demand (read+write) misses
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-system.l2c.demand_misses::cpu1.inst             10176                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             82709                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.dtb.walker          530                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.itb.walker          481                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst             26498                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data            111362                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.dtb.walker         1161                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.itb.walker          997                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.inst             25154                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.data            179232                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                775762                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         1397                       # number of overall misses
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-system.l2c.overall_misses::cpu0.inst            33022                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           301069                       # number of overall misses
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-system.l2c.overall_misses::cpu1.inst            10176                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            82709                       # number of overall misses
-system.l2c.overall_misses::cpu2.dtb.walker          530                       # number of overall misses
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-system.l2c.overall_misses::cpu2.inst            26498                       # number of overall misses
-system.l2c.overall_misses::cpu2.data           111362                       # number of overall misses
-system.l2c.overall_misses::cpu3.dtb.walker         1161                       # number of overall misses
-system.l2c.overall_misses::cpu3.itb.walker          997                       # number of overall misses
-system.l2c.overall_misses::cpu3.inst            25154                       # number of overall misses
-system.l2c.overall_misses::cpu3.data           179232                       # number of overall misses
-system.l2c.overall_misses::total               775762                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker     26478000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.itb.walker     25172000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.dtb.walker     46384500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.itb.walker     43234500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3.dtb.walker    105741000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3.itb.walker     88236000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total      335246000                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data     69679500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu2.data     85116000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu3.data    155511500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total    310307000                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu3.data        82000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total        82000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   4186019500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data   5878341000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3.data  10990816000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  21055176500                       # number of ReadExReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu1.inst    836780000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu2.inst   2229220500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu3.inst   2175672500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::total   5241673000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data   2656686500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu2.data   3377903000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu3.data   6243441000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total  12278030500                       # number of ReadSharedReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu2.data       260500                       # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu3.data      1010500                       # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::total      1271000                       # number of InvalidateReq miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker     26478000                       # number of demand (read+write) miss cycles
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-system.l2c.demand_miss_latency::cpu2.inst   2229220500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data   9256244000                       # number of demand (read+write) miss cycles
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-system.l2c.demand_miss_latency::total     38910126000                       # number of demand (read+write) miss cycles
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-system.l2c.overall_miss_latency::cpu2.data   9256244000                       # number of overall miss cycles
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-system.l2c.overall_miss_latency::cpu3.itb.walker     88236000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.inst   2175672500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.data  17234257000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    38910126000                       # number of overall miss cycles
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-system.l2c.ReadReq_accesses::total             991863                       # number of ReadReq accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::writebacks      7576706                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total      7576706                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackClean_accesses::writebacks     15883082                       # number of WritebackClean accesses(hits+misses)
-system.l2c.WritebackClean_accesses::total     15883082                       # number of WritebackClean accesses(hits+misses)
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-system.l2c.UpgradeReq_accesses::cpu2.data         7293                       # number of UpgradeReq accesses(hits+misses)
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-system.l2c.ReadCleanReq_accesses::cpu2.inst      3878852                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu3.inst      4787556                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::total      15886050                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data      2697856                       # number of ReadSharedReq accesses(hits+misses)
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-system.l2c.ReadSharedReq_accesses::cpu3.data      1969863                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      6559476                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu0.data       659058                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu1.data       109033                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu2.data       156372                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu3.data       301371                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::total      1225834                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker       167474                       # number of demand (read+write) accesses
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-system.l2c.demand_accesses::cpu1.inst         1722599                       # number of demand (read+write) accesses
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-system.l2c.demand_accesses::cpu2.dtb.walker       153202                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.itb.walker        58589                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst         3878852                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data         1448300                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.dtb.walker       296840                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.itb.walker       105920                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.inst         4787556                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.data         2555728                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total            25437871                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker       167474                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker       113840                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst        5497043                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        3511177                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker        54894                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker        41104                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst        1722599                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data        1044753                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.dtb.walker       153202                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.itb.walker        58589                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst        3878852                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data        1448300                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.dtb.walker       296840                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.itb.walker       105920                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.inst        4787556                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.data        2555728                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total           25437871                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.008342                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.012087                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.005593                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.007080                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.003459                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.itb.walker     0.008210                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.dtb.walker     0.003911                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.itb.walker     0.009413                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.006594                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.784759                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.795051                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data     0.774990                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3.data     0.783926                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.784262                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu3.data     0.181818                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.181818                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.224047                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.209756                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data     0.199867                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3.data     0.188154                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.207473                       # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.006007                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.005907                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.006831                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.005254                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.005971                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.044052                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.039400                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.036599                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.035027                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.039535                       # miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu0.data     0.565149                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu1.data     0.200160                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu2.data     0.189701                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu3.data     0.238606                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::total     0.404511                       # miss rate for InvalidateReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.008342                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.012087                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.006007                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.085746                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.005593                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.007080                       # miss rate for demand accesses
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-system.l2c.demand_miss_rate::cpu1.data       0.079166                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.dtb.walker     0.003459                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.itb.walker     0.008210                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.006831                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.076892                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.dtb.walker     0.003911                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.itb.walker     0.009413                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst       0.005254                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.data       0.070130                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.030496                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.008342                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.012087                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.006007                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.085746                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.005593                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.007080                       # miss rate for overall accesses
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-system.l2c.overall_miss_rate::cpu1.data      0.079166                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.dtb.walker     0.003459                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.itb.walker     0.008210                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.006831                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.076892                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.dtb.walker     0.003911                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.itb.walker     0.009413                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst      0.005254                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.data      0.070130                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.030496                       # miss rate for overall accesses
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-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 86501.718213                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 87517.924528                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 89884.615385                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 91077.519380                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.itb.walker 88501.504514                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 51260.856269                       # average ReadReq miss latency
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-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 15059.447983                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 15098.203883                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  8988.153169                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu3.data        41000                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total        41000                       # average SCUpgradeReq miss latency
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-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 82287.064126                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3.data 99705.315105                       # average ReadExReq miss latency
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-system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 84127.877576                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 86494.096366                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 55262.762256                       # average ReadCleanReq miss latency
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-system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 84606.211647                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 90485.963565                       # average ReadSharedReq miss latency
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-system.l2c.InvalidateReq_avg_miss_latency::cpu2.data     8.781688                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu3.data    14.052483                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::total     2.563208                       # average InvalidateReq miss latency
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+system.l2c.UpgradeReq_miss_latency::cpu2.data     11493000                       # number of UpgradeReq miss cycles
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+system.l2c.InvalidateReq_accesses::cpu2.data       151519                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu3.data       305274                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::total      1226027                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker       149759                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker       104259                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst         5511231                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data         3476196                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker        51339                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker        38160                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst         1701578                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data         1067546                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.dtb.walker       146168                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.itb.walker        53846                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst         3909511                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data         1445407                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.dtb.walker       287409                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.itb.walker        99806                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.inst         4778177                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.data         2572451                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total            25392843                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker       149759                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker       104259                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst        5511231                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data        3476196                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker        51339                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker        38160                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst        1701578                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data        1067546                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.dtb.walker       146168                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.itb.walker        53846                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst        3909511                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data        1445407                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.dtb.walker       287409                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.itb.walker        99806                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.inst        4778177                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.data        2572451                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total           25392843                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.009001                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.012987                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.006856                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.007783                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.003414                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.itb.walker     0.008524                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.dtb.walker     0.004415                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.itb.walker     0.010571                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.007127                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.130554                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.131264                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data     0.126485                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu3.data     0.144501                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.134070                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu3.data     0.285714                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.285714                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.228207                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.198058                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data     0.196303                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu3.data     0.191022                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.207866                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.006271                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.005927                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.006556                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.005312                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.006016                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.045710                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.038099                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.034661                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.035064                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.039704                       # miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu0.data     0.570864                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu1.data     0.180077                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu2.data     0.197064                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu3.data     0.235847                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::total     0.404949                       # miss rate for InvalidateReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.009001                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.012987                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.006271                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.088200                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.006856                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.007783                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.005927                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.076206                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.dtb.walker     0.003414                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.itb.walker     0.008524                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst       0.006556                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data       0.074667                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.dtb.walker     0.004415                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.itb.walker     0.010571                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.inst       0.005312                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.data       0.070450                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.030694                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.009001                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.012987                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.006271                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.088200                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.006856                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.007783                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.005927                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.076206                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.dtb.walker     0.003414                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.itb.walker     0.008524                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst      0.006556                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data      0.074667                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.dtb.walker     0.004415                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.itb.walker     0.010571                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.inst      0.005312                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.data      0.070450                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.030694                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 83532.670455                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89208.754209                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 87850.701403                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 88091.503268                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 88847.517730                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu3.itb.walker 88914.218009                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52272.274989                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 18808.091286                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 18300.955414                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 17498.375305                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 10906.476684                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu3.data        43000                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total        43000                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81639.259480                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 82271.039815                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu3.data 100198.757792                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 50532.119370                       # average ReadExReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 82645.761031                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 84468.492723                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 86479.631235                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 54291.390071                       # average ReadCleanReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 84522.302553                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 84759.801061                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 90237.678354                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 46508.028611                       # average ReadSharedReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu1.data     2.779268                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu2.data     1.975954                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu3.data     3.236201                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::total     0.702952                       # average InvalidateReq miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 83532.670455                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89208.754209                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 82645.761031                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 82737.256155                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 87850.701403                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.itb.walker 88091.503268                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 84468.492723                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 83140.413624                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 88847.517730                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.itb.walker 88914.218009                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.inst 86479.631235                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.data 96365.861061                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 49664.264599                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 83532.670455                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89208.754209                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 82645.761031                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 82737.256155                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 87850.701403                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.itb.walker 88091.503268                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 84468.492723                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 83140.413624                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.dtb.walker 88847.517730                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.itb.walker 88914.218009                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.inst 86479.631235                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.data 96365.861061                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 49664.264599                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.writebacks::writebacks              985217                       # number of writebacks
-system.l2c.writebacks::total                   985217                       # number of writebacks
+system.l2c.writebacks::writebacks              987490                       # number of writebacks
+system.l2c.writebacks::total                   987490                       # number of writebacks
 system.l2c.ReadReq_mshr_hits::cpu3.dtb.walker            1                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu3.itb.walker           10                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                11                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu3.itb.walker           11                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                12                       # number of ReadReq MSHR hits
 system.l2c.ReadCleanReq_mshr_hits::cpu2.inst            1                       # number of ReadCleanReq MSHR hits
 system.l2c.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu2.data            3                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu2.data            2                       # number of ReadSharedReq MSHR hits
 system.l2c.ReadSharedReq_mshr_hits::cpu3.data            3                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total            6                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total            5                       # number of ReadSharedReq MSHR hits
 system.l2c.demand_mshr_hits::cpu2.inst              1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu2.data              3                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu2.data              2                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu3.dtb.walker            1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3.itb.walker           10                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu3.itb.walker           11                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu3.data              3                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::total                 18                       # number of demand (read+write) MSHR hits
 system.l2c.overall_mshr_hits::cpu2.inst             1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu2.data             3                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu2.data             2                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu3.dtb.walker            1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3.itb.walker           10                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu3.itb.walker           11                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu3.data             3                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::total                18                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker          307                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.itb.walker          291                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker          530                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.itb.walker          481                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu3.dtb.walker         1160                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu3.itb.walker          987                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total            3756                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker          352                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.itb.walker          297                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker          499                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.itb.walker          459                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu3.dtb.walker         1268                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu3.itb.walker         1044                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total            3919                       # number of ReadReq MSHR misses
 system.l2c.CleanEvict_mshr_misses::writebacks            1                       # number of CleanEvict MSHR misses
 system.l2c.CleanEvict_mshr_misses::total            1                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         4659                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data         5652                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu3.data        10300                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        20611                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data          482                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2.data          628                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu3.data         1231                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         2341                       # number of UpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::cpu3.data            2                       # number of SCUpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        51154                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data        71437                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu3.data       110233                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        232824                       # number of ReadExReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu1.inst        10176                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu2.inst        26497                       # number of ReadCleanReq MSHR misses
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+system.l2c.demand_mshr_miss_latency::cpu1.inst    732632500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   5917387513                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker     38847500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.itb.walker     35844000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst   1908425001                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data   7893535001                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker     99977501                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.itb.walker     82668000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.inst   1941197018                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.data  15651893556                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  34351816090                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker     25883500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker     23525000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    732632500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   5917387513                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker     38847500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.itb.walker     35844000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst   1908425001                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data   7893535001                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker     99977501                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.itb.walker     82668000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.inst   1941197018                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.data  15651893556                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  34351816090                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    853214500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data    766744000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data    791147500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   2411106000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    853214500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data    766744000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu3.data    791147500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   2411106000                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.006856                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.007783                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.003414                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker     0.008524                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker     0.004412                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3.itb.walker     0.010460                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.004211                       # mshr miss rate for ReadReq accesses
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.795051                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.774990                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data     0.783926                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.468208                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data     0.181818                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.181818                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.209756                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.199867                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu3.data     0.188154                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.116384                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.005907                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.006831                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.005254                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.003892                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.039400                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.036596                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.035026                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.021415                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.200160                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data     0.189701                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu3.data     0.238606                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::total     0.100664                       # mshr miss rate for InvalidateReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.005593                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.007080                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005907                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.079166                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.003459                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.itb.walker     0.008210                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.006831                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.076889                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker     0.003908                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.itb.walker     0.009318                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.inst     0.005254                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.data     0.070128                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.017253                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.005593                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.007080                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005907                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.079166                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.003459                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.itb.walker     0.008210                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.006831                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.076889                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker     0.003908                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.itb.walker     0.009318                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.inst     0.005254                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.data     0.070128                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.017253                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76247.557003                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76501.718213                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 77517.924528                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 79884.615385                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 81078.018966                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 78567.376900                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 79013.712194                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18913.608070                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 18989.561217                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 18998.883495                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18977.051089                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data        46250                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        46250                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71831.714040                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 72287.057141                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 89705.287954                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 80433.859946                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72230.738994                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 74128.467374                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 76493.778962                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 74778.438482                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74192.030233                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 74608.649517                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 80486.688431                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 77402.173905                       # average ReadSharedReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 18735.566349                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 19463.878776                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 20265.380550                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19802.140652                       # average InvalidateReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76247.557003                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76501.718213                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72230.738994                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72732.217945                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 77517.924528                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 79884.615385                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 74128.467374                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 73119.343807                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 81078.018966                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 78567.376900                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 76493.778962                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 86156.495668                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 78654.645010                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76247.557003                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76501.718213                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72230.738994                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72732.217945                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 77517.924528                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 79884.615385                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 74128.467374                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 73119.343807                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 81078.018966                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 78567.376900                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 76493.778962                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 86156.495668                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 78654.645010                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169058.180058                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 167139.504277                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 172277.427079                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 169480.164827                       # average ReadReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 88675.281812                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 88326.069317                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 89096.307554                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 88701.867895                       # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests       2714288                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests      1358609                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests         3170                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.131264                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.126485                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data     0.144501                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.081310                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data     0.285714                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.285714                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.198058                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.196303                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3.data     0.191022                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.115750                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.005927                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.006555                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.005312                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.003842                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.038099                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.034659                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.035063                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.021111                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.180077                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data     0.197064                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu3.data     0.235847                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::total     0.099807                       # mshr miss rate for InvalidateReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.006856                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.007783                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005927                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.076206                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.003414                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.itb.walker     0.008524                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.006555                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.074665                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker     0.004412                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.itb.walker     0.010460                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.inst     0.005312                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.data     0.070449                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.017151                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.006856                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.007783                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005927                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.076206                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.003414                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.itb.walker     0.008524                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.006555                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.074665                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker     0.004412                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.itb.walker     0.010460                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.inst     0.005312                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.data     0.070449                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.017151                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 73532.670455                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 79208.754209                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 77850.701403                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 78091.503268                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 78846.609621                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 79183.908046                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 78271.370503                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18983.402490                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 18979.299363                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 18993.907392                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18987.825716                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data        47750                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        47750                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71639.259480                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 72271.039815                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 90198.708570                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 80746.334432                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72645.761031                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 74466.403972                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 76479.277362                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 75002.119961                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74522.093180                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 74761.883946                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 80238.463604                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 77467.290341                       # average ReadSharedReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 18745.477595                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 19446.900432                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 20257.972444                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19806.559829                       # average InvalidateReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 73532.670455                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79208.754209                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72645.761031                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72737.176416                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 77850.701403                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 78091.503268                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 74466.403972                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 73141.111182                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 78846.609621                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 79183.908046                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 76479.277362                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 86366.234369                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 78876.128753                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 73532.670455                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79208.754209                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72645.761031                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72737.176416                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 77850.701403                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 78091.503268                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 74466.403972                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 73141.111182                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 78846.609621                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 79183.908046                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 76479.277362                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 86366.234369                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 78876.128753                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169322.186942                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 167521.083679                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 172100.826626                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 169640.892141                       # average ReadReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 88820.997293                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 88477.267482                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 88773.283214                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 88695.776928                       # average overall mshr uncacheable latency
+system.membus.snoop_filter.tot_requests       2692221                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests      1332095                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests         2857                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadReq               76739                       # Transaction distribution
-system.membus.trans_dist::ReadResp             446283                       # Transaction distribution
+system.membus.trans_dist::ReadResp             448186                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33648                       # Transaction distribution
 system.membus.trans_dist::WriteResp             33648                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1091848                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           200785                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            35184                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1094121                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           202838                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4443                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           14271                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            414448                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           414448                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        369544                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        602468                       # Transaction distribution
-system.membus.trans_dist::InvalidateResp       435243                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            1867                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            416227                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           416227                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        371447                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        603124                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp       437026                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122576                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6762                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3736384                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      3865780                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       302176                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       302176                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4167956                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3707227                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      3836623                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       302374                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       302374                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4138997                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155706                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13524                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    112845536                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    113014898                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7362816                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7362816                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               120377714                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              603                       # Total snoops (count)
-system.membus.snoopTraffic                      38528                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples           2230474                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.016353                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.126827                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    113227104                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    113396466                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7366016                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7366016                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               120762482                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              546                       # Total snoops (count)
+system.membus.snoopTraffic                      34880                       # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples           2213347                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.016167                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.126119                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 2194000     98.36%     98.36% # Request fanout histogram
-system.membus.snoop_fanout::1                   36474      1.64%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 2177563     98.38%     98.38% # Request fanout histogram
+system.membus.snoop_fanout::1                   35784      1.62%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2230474                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            45941500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             2213347                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            45757000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1601000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1572000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          3279160105                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          3230054159                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         2368546008                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         2350415750                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy            4606769                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy            2301227                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
 system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
 system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
 system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
 system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
 system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
@@ -3307,86 +3311,86 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
 system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests     52014816                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests     26342736                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests         3149                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops           2216                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops         2216                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.snoop_filter.tot_requests     52031861                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests     26343539                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests         3136                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops           2272                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops         2272                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51316261201000                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadReq            1497604                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp          23943591                       # Transaction distribution
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.trans_dist::ReadReq            1497693                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp          23955179                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             33648                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            33648                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty      8020601                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean     15885620                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         2314166                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           44021                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq            11                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          44032                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          2000482                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         2000482                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq      15886240                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      6559913                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq      1231249                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp      1225834                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     47744160                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     29579701                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       811490                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1741524                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              79876875                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   2033559380                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1032953822                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2918064                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      6139128                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total             3075570394                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         1503666                       # Total snoops (count)
-system.toL2Bus.snoopTraffic                  65422752                       # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples         38127714                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.016625                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.127861                       # Request fanout histogram
+system.toL2Bus.trans_dist::WritebackDirty      8020839                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean     15900080                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         2311396                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           28791                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq             7                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          28798                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          2005082                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         2005082                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq      15900700                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      6556911                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq      1231319                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp      1226027                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     47787527                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     29554737                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       797902                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1720271                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              79860437                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   2035409428                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1033316830                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2813832                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      5963920                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total             3077504010                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         1542362                       # Total snoops (count)
+system.toL2Bus.snoopTraffic                  65849016                       # Total snoop traffic (bytes)
+system.toL2Bus.snoop_fanout::samples         38107926                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.016628                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.127874                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0               37493845     98.34%     98.34% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 633869      1.66%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0               37474258     98.34%     98.34% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 633668      1.66%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           38127714                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy        31242309916                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total           38107926                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy        31293825988                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           523765                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           519265                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy       15589083360                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy       15589080685                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        7892971168                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        7944642139                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         287709740                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy         286385229                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         712482327                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy         714971913                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu3.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu3.kern.inst.quiesce                       0                       # number of quiesce instructions executed
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt
index 1ebab8c9c..cbc921b4f 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt
@@ -1,158 +1,158 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.317224                       # Number of seconds simulated
-sim_ticks                                51317223946000                       # Number of ticks simulated
-final_tick                               51317223946000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.317217                       # Number of seconds simulated
+sim_ticks                                51317217215000                       # Number of ticks simulated
+final_tick                               51317217215000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 175740                       # Simulator instruction rate (inst/s)
-host_op_rate                                   206507                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             9897363484                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 694116                       # Number of bytes of host memory used
-host_seconds                                  5184.94                       # Real time elapsed on the host
-sim_insts                                   911201050                       # Number of instructions simulated
-sim_ops                                    1070728401                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 222365                       # Simulator instruction rate (inst/s)
+host_op_rate                                   261300                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            12534471719                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 700016                       # Number of bytes of host memory used
+host_seconds                                  4094.09                       # Real time elapsed on the host
+sim_insts                                   910382802                       # Number of instructions simulated
+sim_ops                                    1069785844                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.dtb.walker       175488                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       146560                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          3612352                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         27482328                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       187136                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       157760                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          3726080                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         29409648                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        423552                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             65320904                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      3612352                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      3726080                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         7338432                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     83980672                       # Number of bytes written to this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu0.dtb.walker       183360                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker       154432                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          3744320                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         27933912                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       182144                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       147072                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          3576960                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         29113392                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        413632                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             65449224                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      3744320                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      3576960                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         7321280                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     83967296                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          84001252                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         2742                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         2290                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             56443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            429419                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         2924                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         2465                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             58220                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            459531                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6618                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1020652                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1312198                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          83987876                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         2865                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         2413                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             58505                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            436475                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         2846                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         2298                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             55890                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            454902                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6463                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1022657                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1311989                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1314771                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          3420                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          2856                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               70393                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              535538                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          3647                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          3074                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               72609                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              573095                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8254                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1272885                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          70393                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          72609                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             143001                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1636501                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1314562                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          3573                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          3009                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               72964                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              544338                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          3549                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          2866                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               69703                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              567322                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8060                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1275385                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          72964                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          69703                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             142667                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1636240                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data                401                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1636902                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1636501                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         3420                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         2856                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              70393                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             535939                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         3647                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         3074                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              72609                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             573095                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8254                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2909786                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1020652                       # Number of read requests accepted
-system.physmem.writeReqs                      1314771                       # Number of write requests accepted
-system.physmem.readBursts                     1020652                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1314771                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 65284928                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     36800                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  84000896                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  65320904                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               84001252                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      575                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2239                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bw_write::total                1636641                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1636240                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         3573                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         3009                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              72964                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             544739                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         3549                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         2866                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              69703                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             567322                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8060                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2912027                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1022657                       # Number of read requests accepted
+system.physmem.writeReqs                      1314562                       # Number of write requests accepted
+system.physmem.readBursts                     1022657                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1314562                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 65407680                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     42368                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  83988672                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  65449224                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               83987876                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      662                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2238                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               60738                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               63324                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               61558                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               59296                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               63003                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               70930                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               62473                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               61273                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               57204                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               83606                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              64602                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              64452                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              60809                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              66792                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              61061                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              58956                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               80045                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               81301                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               81272                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               81440                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               83523                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               87218                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               82653                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               82595                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               79330                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               83624                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              82850                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              84015                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              79570                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              84630                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              79832                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              78616                       # Per bank write bursts
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+system.physmem.perBankRdBursts::14              59027                       # Per bank write bursts
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+system.physmem.perBankWrBursts::0               79428                       # Per bank write bursts
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+system.physmem.perBankWrBursts::13              84960                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              78537                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              79161                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                         119                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51317222751500                       # Total gap between requests
+system.physmem.numWrRetry                         117                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51317216009000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1020637                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1022642                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1312198                       # Write request sizes (log2)
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-system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1311989                       # Write request sizes (log2)
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 system.physmem.rdQLenPdf::22                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
@@ -163,176 +163,190 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
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 system.physmem.wrQLenPdf::5                       727                       # What write queue length does an incoming req see
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-system.physmem.bytesPerActivate::samples       586236                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      254.650755                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     152.083309                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     294.038467                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         256952     43.83%     43.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       146727     25.03%     68.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        55530      9.47%     78.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        27689      4.72%     83.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        21119      3.60%     86.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        11926      2.03%     88.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        10672      1.82%     90.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         7426      1.27%     91.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        48195      8.22%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         586236                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         61671                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        16.539767                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev       65.609404                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511           61664     99.99%     99.99% # Reads before turning the bus around for writes
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+system.physmem.wrQLenPdf::54                     1069                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                     1091                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                     1044                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      852                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      760                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                      751                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                      793                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                      438                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                      266                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                      292                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       584051                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      255.792785                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     152.875634                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     294.556382                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         254148     43.51%     43.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       146795     25.13%     68.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        55909      9.57%     78.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        27613      4.73%     82.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        21352      3.66%     86.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        11974      2.05%     88.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895        10495      1.80%     90.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         7232      1.24%     91.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        48533      8.31%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         584051                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         61706                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        16.562133                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev       65.554683                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511           61699     99.99%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::512-1023            3      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-1535            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-2559            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::11776-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           61671                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         61671                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        21.282515                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.526147                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       23.873212                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-31            57372     93.03%     93.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-63            2142      3.47%     96.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-95            1045      1.69%     98.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-127            638      1.03%     99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-159           205      0.33%     99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-191           106      0.17%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-223            28      0.05%     99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-255            57      0.09%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-287            30      0.05%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-319             6      0.01%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-351             4      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-383            11      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-415             7      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::416-447             1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::448-479             2      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-511             4      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-543             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::576-607             3      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::608-639             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::640-671             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::736-767             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::864-895             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::896-927             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::960-991             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::992-1023            1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::1504-1535            1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           61671                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    27430760765                       # Total ticks spent queuing
-system.physmem.totMemAccLat               46557204515                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   5100385000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       26890.87                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total           61706                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         61706                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        21.267348                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.511616                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       23.799712                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-15              139      0.23%      0.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-31           57235     92.75%     92.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-47            1751      2.84%     95.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-63             438      0.71%     96.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-79             620      1.00%     97.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-95             435      0.70%     98.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-111            261      0.42%     98.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-127           360      0.58%     99.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-143           146      0.24%     99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-159            47      0.08%     99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-175            57      0.09%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-191            58      0.09%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-207            16      0.03%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-223            17      0.03%     99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-239            19      0.03%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-255            28      0.05%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-271            17      0.03%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-287            15      0.02%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::288-303             2      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::304-319             1      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::320-335             1      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::336-351             6      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::352-367             3      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::368-383             5      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::384-399             4      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::400-415             4      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::480-495             2      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::496-511             1      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::512-527             3      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::608-623             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::640-655             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::672-687             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::752-767             2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::768-783             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::784-799             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::832-847             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::848-863             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::864-879             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::880-895             2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::896-911             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           61706                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    27544031458                       # Total ticks spent queuing
+system.physmem.totMemAccLat               46706437708                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   5109975000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       26951.24                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  45640.87                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  45701.24                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           1.27                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           1.64                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.27                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.28                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        1.64                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.06                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         7.21                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     787981                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    958372                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   77.25                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.02                       # Row buffer hit rate for writes
-system.physmem.avgGap                     21973416.70                       # Average gap between requests
-system.physmem.pageHitRate                      74.87                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 2249478000                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 1227393750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                3920233200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               4277104560                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3351791311440                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1233069997860                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29708691447750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34305226966560                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.493484                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49422945373021                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1713594740000                       # Time in different power states
+system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                         9.79                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     789656                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    960610                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   77.27                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.20                       # Row buffer hit rate for writes
+system.physmem.avgGap                     21956528.68                       # Average gap between requests
+system.physmem.pageHitRate                      74.98                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 2223494280                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1213216125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                3913798200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               4267753920                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3351790802880                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1231075762515                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29710436097000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34304920924920                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.487622                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49425844576094                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1713594480000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    180683706479                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    177772818906                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 2182466160                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 1190829750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                4036320600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               4227986160                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3351791311440                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1230809355630                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29710674459000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34304912728740                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.487361                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49426230251457                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1713594740000                       # Time in different power states
+system.physmem_1.actEnergy                 2191931280                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1195994250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                4057723800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               4236099120                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3351790802880                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1231757755830                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29709837865500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34305068172660                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.490491                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49424824907095                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1713594480000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    177398580543                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    178797453905                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
 system.realview.nvmem.bytes_read::cpu0.inst          768                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst         1408                       # Number of bytes read from this memory
@@ -355,30 +369,30 @@ system.realview.nvmem.bw_total::cpu0.inst           15                       # T
 system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu1.inst           27                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total              43                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups              134105303                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         90165699                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          5786352                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            89882943                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               61723151                       # Number of BTB hits
+system.cpu0.branchPred.lookups              134591179                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         90304193                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          5810526                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            90589543                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               61837798                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            68.670594                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               17198111                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect            190210                       # Number of incorrect RAS predictions.
-system.cpu0.branchPred.indirectLookups        5005537                       # Number of indirect predictor lookups.
-system.cpu0.branchPred.indirectHits           2645934                       # Number of indirect target hits.
-system.cpu0.branchPred.indirectMisses         2359603                       # Number of indirect misses.
-system.cpu0.branchPredindirectMispredicted       409587                       # Number of mispredicted indirect branches.
+system.cpu0.branchPred.BTBHitPct            68.261519                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               17370059                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect            190077                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.indirectLookups        5078772                       # Number of indirect predictor lookups.
+system.cpu0.branchPred.indirectHits           2686505                       # Number of indirect target hits.
+system.cpu0.branchPred.indirectMisses         2392267                       # Number of indirect misses.
+system.cpu0.branchPredindirectMispredicted       411015                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -408,95 +422,89 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dtb.walker.walks                   899770                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               899770                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        17075                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        93436                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore       556454                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples       343316                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean  2623.475166                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev 14944.534863                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-32767       334883     97.54%     97.54% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::32768-65535         5615      1.64%     99.18% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::65536-98303         1161      0.34%     99.52% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::98304-131071          826      0.24%     99.76% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::131072-163839          305      0.09%     99.85% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::163840-196607          149      0.04%     99.89% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::196608-229375           96      0.03%     99.92% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::229376-262143           57      0.02%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::262144-294911           86      0.03%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::294912-327679           45      0.01%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::327680-360447           14      0.00%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::360448-393215           18      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::393216-425983           26      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::425984-458751           33      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::458752-491519            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::491520-524287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       343316                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples       426919                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 23051.464095                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 18844.709714                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 16480.973938                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535       417565     97.81%     97.81% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071         8400      1.97%     99.78% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607          455      0.11%     99.88% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143          392      0.09%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.walker.walks                   913460                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               913460                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        17456                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        94858                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore       564703                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples       348757                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean  2510.769676                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev 14687.468261                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-65535       346035     99.22%     99.22% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::65536-131071         1894      0.54%     99.76% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::131072-196607          459      0.13%     99.89% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::196608-262143          149      0.04%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::262144-327679          127      0.04%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::327680-393215           27      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::393216-458751           61      0.02%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::458752-524287            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       348757                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples       428972                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 22512.397080                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 18206.266840                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 16738.101214                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535       419694     97.84%     97.84% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071         8206      1.91%     99.75% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607          548      0.13%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143          418      0.10%     99.98% # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walkCompletionTime::262144-327679           68      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215           32      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751            6      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total       426919                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 352898234664                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     0.139794                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev     0.715758                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-3 351858805164     99.71%     99.71% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-7    566388500      0.16%     99.87% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-11    206550000      0.06%     99.92% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-15    120953500      0.03%     99.96% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-19     47115000      0.01%     99.97% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::20-23     25743000      0.01%     99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::24-27     26226000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::28-31     38984000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::32-35      6924500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::36-39       487500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::40-43        24000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::44-47        16500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::48-51        16500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::52-55          500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 352898234664                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        93436     84.55%     84.55% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M        17075     15.45%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total       110511                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       899770                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215           26      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287            6      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total       428972                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples 361724793256                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.150757                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.705483                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-3 360695140256     99.72%     99.72% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-7    568723500      0.16%     99.87% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-11    203544500      0.06%     99.93% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-15    117776000      0.03%     99.96% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-19     46114500      0.01%     99.97% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::20-23     23872000      0.01%     99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::24-27     26539000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::28-31     36172500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::32-35      6478000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::36-39       375000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::40-43        38000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::44-47         6500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::48-51        12500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::52-55         1000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 361724793256                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        94859     84.46%     84.46% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        17456     15.54%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total       112315                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       913460                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       899770                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       110511                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       913460                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       112315                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       110511                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total      1010281                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       112315                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total      1025775                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                   105998610                       # DTB read hits
-system.cpu0.dtb.read_misses                    619021                       # DTB read misses
-system.cpu0.dtb.write_hits                   82262350                       # DTB write hits
-system.cpu0.dtb.write_misses                   280749                       # DTB write misses
-system.cpu0.dtb.flush_tlb                        1081                       # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits                   106460809                       # DTB read hits
+system.cpu0.dtb.read_misses                    623704                       # DTB read misses
+system.cpu0.dtb.write_hits                   82932208                       # DTB write hits
+system.cpu0.dtb.write_misses                   289756                       # DTB write misses
+system.cpu0.dtb.flush_tlb                        1080                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              22329                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_mva_asid              21954                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                    534                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   55918                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      189                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  9571                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                   55225                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      193                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  9182                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    57075                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses               106617631                       # DTB read accesses
-system.cpu0.dtb.write_accesses               82543099                       # DTB write accesses
+system.cpu0.dtb.perms_faults                    56785                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses               107084513                       # DTB read accesses
+system.cpu0.dtb.write_accesses               83221964                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        188260960                       # DTB hits
-system.cpu0.dtb.misses                         899770                       # DTB misses
-system.cpu0.dtb.accesses                    189160730                       # DTB accesses
-system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.hits                        189393017                       # DTB hits
+system.cpu0.dtb.misses                         913460                       # DTB misses
+system.cpu0.dtb.accesses                    190306477                       # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -526,859 +534,861 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.cpu0.itb.walker.walks                   102467                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong               102467                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2         2998                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3        69670                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore        14196                       # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples        88271                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean  1375.933206                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev  8810.022108                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-32767        87313     98.91%     98.91% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-65535          590      0.67%     99.58% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::65536-98303          225      0.25%     99.84% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::98304-131071           97      0.11%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::131072-163839           16      0.02%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::163840-196607           14      0.02%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::196608-229375            4      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::229376-262143            3      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::262144-294911            4      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::294912-327679            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::491520-524287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        88271                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples        86864                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 28386.103564                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 24197.471815                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 17986.515042                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535        84889     97.73%     97.73% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071         1706      1.96%     99.69% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607          161      0.19%     99.88% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143           62      0.07%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679           31      0.04%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215           13      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.cpu0.itb.walker.walks                   102224                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong               102224                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2         2961                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        69807                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore        13996                       # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples        88228                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean  1371.061341                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev  8977.114896                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-32767        87329     98.98%     98.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-65535          530      0.60%     99.58% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::65536-98303          216      0.24%     99.83% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::98304-131071           99      0.11%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::131072-163839           20      0.02%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::163840-196607           15      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::196608-229375            6      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::229376-262143            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::262144-294911            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::294912-327679            4      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::327680-360447            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::360448-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        88228                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        86764                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 27719.480430                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 23267.563993                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 18820.928470                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535        84648     97.56%     97.56% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071         1819      2.10%     99.66% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607          174      0.20%     99.86% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143           69      0.08%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679           30      0.03%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215           20      0.02%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total        86864                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples 606302699128                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     0.904496                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev     0.294288                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0    57963600068      9.56%      9.56% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1   548286629060     90.43%     99.99% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2       47140500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3        4566000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::4         404000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::5         270000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::6          89500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 606302699128                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        69670     95.87%     95.87% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M         2998      4.13%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        72668                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkCompletionTime::total        86764                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples 597945449536                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     0.915932                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev     0.277880                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0    50325346976      8.42%      8.42% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1   547568596060     91.58%     99.99% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2       46828000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3        4056500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::4         391500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::5          54500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::6         126500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::7          49500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 597945449536                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K        69807     95.93%     95.93% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M         2961      4.07%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        72768                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst       102467                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total       102467                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst       102224                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total       102224                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        72668                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        72668                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       175135                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    94697092                       # ITB inst hits
-system.cpu0.itb.inst_misses                    102467                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        72768                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        72768                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       174992                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    95313688                       # ITB inst hits
+system.cpu0.itb.inst_misses                    102224                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                        1081                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb                        1080                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              22329                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_mva_asid              21954                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                    534                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   41669                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                   40789                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                   188921                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                   189995                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                94799559                       # ITB inst accesses
-system.cpu0.itb.hits                         94697092                       # DTB hits
-system.cpu0.itb.misses                         102467                       # DTB misses
-system.cpu0.itb.accesses                     94799559                       # DTB accesses
-system.cpu0.numPwrStateTransitions              15974                       # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples         7987                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean    2945663211.345562                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev   55329339473.705994                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::underflows         3525     44.13%     44.13% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10         4444     55.64%     99.77% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::5e+10-1e+11            2      0.03%     99.80% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11            2      0.03%     99.82% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11            2      0.03%     99.85% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11            3      0.04%     99.89% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11            1      0.01%     99.90% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::overflows            8      0.10%    100.00% # Distribution of time spent in the clock gated state
+system.cpu0.itb.inst_accesses                95415912                       # ITB inst accesses
+system.cpu0.itb.hits                         95313688                       # DTB hits
+system.cpu0.itb.misses                         102224                       # DTB misses
+system.cpu0.itb.accesses                     95415912                       # DTB accesses
+system.cpu0.numPwrStateTransitions              16182                       # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples         8091                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean    3359442146.645409                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev   64779765350.946983                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows         3624     44.79%     44.79% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10         4450     55.00%     99.79% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::5e+10-1e+11            1      0.01%     99.80% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11            3      0.04%     99.84% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11            1      0.01%     99.85% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11            1      0.01%     99.86% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::overflows           10      0.12%    100.00% # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::max_value 1988782294428                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total           7987                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON   27790211876983                       # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 23527012069017                       # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles                       671968082                       # number of cpu cycles simulated
+system.cpu0.pwrStateClkGateDist::max_value 1988782283928                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total           8091                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON   24135970806492                       # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 27181246408508                       # Cumulative time (in ticks) in various power states
+system.cpu0.numCycles                       673796045                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles         245522731                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     595240198                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                  134105303                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          81567196                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                    387351290                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles               13225502                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                   2523731                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles               22012                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingDrainCycles             3023                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu0.fetch.PendingTrapStallCycles      4782962                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       167694                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles         2395                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                 94491838                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes              3604496                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                  39400                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         646988319                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             1.075576                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.327336                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles         248201376                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     597842349                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                  134591179                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          81894362                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                    386081151                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles               13278647                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                   2497741                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles               21664                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles             3050                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles      4790854                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       168722                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles         2591                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                 95107499                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes              3628886                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                  39039                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         648406203                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             1.078367                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.330450                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0               500985180     77.43%     77.43% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                18129867      2.80%     80.24% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                18167874      2.81%     83.04% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                13357518      2.06%     85.11% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                28640593      4.43%     89.54% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                 8987633      1.39%     90.92% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                 9763680      1.51%     92.43% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                 8383348      1.30%     93.73% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                40572626      6.27%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0               501760932     77.38%     77.38% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                18256203      2.82%     80.20% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                18220690      2.81%     83.01% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                13435350      2.07%     85.08% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                28609960      4.41%     89.49% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                 9048805      1.40%     90.89% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                 9824320      1.52%     92.40% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                 8413306      1.30%     93.70% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                40836637      6.30%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           646988319                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.199571                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.885816                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles               199030326                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles            322925985                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                105893213                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles             13875278                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               5261155                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved            19621820                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred              1370848                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts             649217042                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts              4232345                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               5261155                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles               206721651                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               22515587                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles     261202094                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                111943526                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             39341608                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts             633848526                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents                79662                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents               1830943                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents               1627304                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents              19580203                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.FullRegisterEvents            3993                       # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands          606139321                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            975790571                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       747374109                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups           852582                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps            509962376                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                96176945                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts          15656160                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts      13698263                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 77451785                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads           102163876                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           86418656                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads         13880040                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores        14667641                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                 600742993                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded           15759066                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                601574255                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued           855603                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined       81711782                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     51353600                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        357908                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    646988319                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.929807                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.657116                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           648406203                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.199751                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.887275                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles               201305382                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles            321428647                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                106579942                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles             13809088                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               5281102                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved            19732890                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred              1377081                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts             652345167                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts              4243358                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               5281102                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles               208974593                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               22808368                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles     259762289                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                112590129                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles             38987372                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts             636948284                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents                76415                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents               1870283                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents               1736148                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents              19269388                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.FullRegisterEvents            3866                       # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands          608166873                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            978325960                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups       751087221                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups           834633                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps            511551111                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                96615757                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts          15505583                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts      13521940                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 76964594                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads           102747908                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           87125063                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads         13952178                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores        14707468                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                 603971660                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded           15594199                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                604455425                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued           868037                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined       82226578                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     51472860                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        368538                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    648406203                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.932217                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.660002                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0          411195381     63.56%     63.56% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1           99990691     15.45%     79.01% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2           43358439      6.70%     85.71% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3           31042131      4.80%     90.51% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4           23015507      3.56%     94.07% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5           16185943      2.50%     96.57% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6           11141665      1.72%     98.29% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7            6569936      1.02%     99.31% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8            4488626      0.69%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0          412086930     63.55%     63.55% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1           99690109     15.37%     78.93% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2           43563237      6.72%     85.65% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3           31279787      4.82%     90.47% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4           23126821      3.57%     94.04% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5           16303260      2.51%     96.55% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6           11232229      1.73%     98.28% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7            6608117      1.02%     99.30% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8            4515713      0.70%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      646988319                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      648406203                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                2994179     25.40%     25.40% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                 22123      0.19%     25.59% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                   2181      0.02%     25.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     25.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     25.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     25.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     25.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     25.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     25.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     25.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     25.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     25.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     25.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     25.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     25.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     25.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     25.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     25.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     25.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     25.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     25.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     25.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     25.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     25.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     25.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     25.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     25.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     25.61% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead               4797008     40.69%     66.30% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite              3972728     33.70%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                3047764     25.70%     25.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                 24416      0.21%     25.91% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                   3438      0.03%     25.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     25.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     25.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     25.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     25.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     25.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     25.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     25.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     25.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     25.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     25.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     25.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     25.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     25.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     25.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     25.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     25.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     25.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     25.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     25.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     25.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     25.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     25.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     25.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     25.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     25.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead               4792960     40.42%     66.35% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite              3990225     33.65%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass               51      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu            408493998     67.90%     67.90% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult             1413538      0.23%     68.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                65279      0.01%     68.15% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                146      0.00%     68.15% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.15% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.15% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.15% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.15% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.15% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.15% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.15% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.15% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.15% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.15% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.15% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.15% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.15% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.15% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.15% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.15% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.15% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.15% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.15% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.15% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.15% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc         55915      0.01%     68.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead           108222779     17.99%     86.15% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           83322549     13.85%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass               49      0.00%      0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu            410215443     67.87%     67.87% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult             1414052      0.23%     68.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                66288      0.01%     68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                164      0.00%     68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc         69960      0.01%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead           108687129     17.98%     86.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           84002340     13.90%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total             601574255                       # Type of FU issued
-system.cpu0.iq.rate                          0.895242                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                   11788219                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.019596                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads        1861718464                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes        698381981                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses    579322691                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads            1062187                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes            541590                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       470908                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses             612794722                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                 567701                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads         4798771                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total             604455425                       # Type of FU issued
+system.cpu0.iq.rate                          0.897090                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                   11858803                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.019619                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads        1868979076                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes        701958936                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses    582265082                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads            1064817                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes            542988                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       473036                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses             615746479                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                 567700                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads         4852034                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads     16823750                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses        20061                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation       720899                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores      8636995                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads     16874429                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses        20604                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation       721236                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores      8753871                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads      4014042                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked      7828481                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads      4029020                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked      7690355                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               5261155                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles               14418671                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles              6592888                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts          616647515                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts          1731555                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts            102163876                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            86418656                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts          13404445                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                244099                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents              6259110                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents        720899                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect       2467872                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect      2697760                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts             5165632                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts            594649792                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts            105987908                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts          6038347                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles               5281102                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles               14719425                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles              6525674                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts          619711534                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts          1741377                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts            102747908                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            87125063                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts          13231258                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                247990                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents              6185988                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents        721236                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect       2486586                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect      2703924                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts             5190510                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts            597504652                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts            106449995                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts          6051495                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       145456                       # number of nop insts executed
-system.cpu0.iew.exec_refs                   188253040                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches               110177692                       # Number of branches executed
-system.cpu0.iew.exec_stores                  82265132                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.884938                       # Inst execution rate
-system.cpu0.iew.wb_sent                     581218511                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                    579793599                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                286101590                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                497649201                       # num instructions consuming a value
-system.cpu0.iew.wb_rate                      0.862829                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.574906                       # average fanout of values written-back
-system.cpu0.commit.commitSquashedInsts       81765486                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls       15401158                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts          4434486                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    633109401                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.844704                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.839642                       # Number of insts commited each cycle
+system.cpu0.iew.exec_nop                       145675                       # number of nop insts executed
+system.cpu0.iew.exec_refs                   189385273                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches               110604743                       # Number of branches executed
+system.cpu0.iew.exec_stores                  82935278                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.886774                       # Inst execution rate
+system.cpu0.iew.wb_sent                     584170266                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                    582738118                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                287532720                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                500025728                       # num instructions consuming a value
+system.cpu0.iew.wb_rate                      0.864858                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.575036                       # average fanout of values written-back
+system.cpu0.commit.commitSquashedInsts       82281412                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls       15225661                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts          4452035                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    634456144                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.846929                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.842512                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0    436470478     68.94%     68.94% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1     97716674     15.43%     84.38% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2     32967148      5.21%     89.58% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3     15484157      2.45%     92.03% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4     10846506      1.71%     93.74% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5      6530507      1.03%     94.77% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      6073156      0.96%     95.73% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7      3956859      0.62%     96.36% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8     23063916      3.64%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0    437517078     68.96%     68.96% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1     97256113     15.33%     84.29% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2     33197387      5.23%     89.52% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3     15688308      2.47%     91.99% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4     10938676      1.72%     93.72% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5      6579950      1.04%     94.75% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      6141511      0.97%     95.72% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7      3977023      0.63%     96.35% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8     23160098      3.65%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    633109401                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts           455072762                       # Number of instructions committed
-system.cpu0.commit.committedOps             534790277                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    634456144                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts           457096110                       # Number of instructions committed
+system.cpu0.commit.committedOps             537339276                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                     163121787                       # Number of memory references committed
-system.cpu0.commit.loads                     85340126                       # Number of loads committed
-system.cpu0.commit.membars                    3736581                       # Number of memory barriers committed
-system.cpu0.commit.branches                 101711661                       # Number of branches committed
-system.cpu0.commit.fp_insts                    451530                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                490677146                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls            13330927                       # Number of function calls committed.
+system.cpu0.commit.refs                     164244670                       # Number of memory references committed
+system.cpu0.commit.loads                     85873478                       # Number of loads committed
+system.cpu0.commit.membars                    3759461                       # Number of memory barriers committed
+system.cpu0.commit.branches                 102099172                       # Number of branches committed
+system.cpu0.commit.fp_insts                    454376                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                493297626                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls            13466186                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu       370465668     69.27%     69.27% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult        1106577      0.21%     69.48% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv           48950      0.01%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc        47295      0.01%     69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       85340126     15.96%     85.46% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      77781661     14.54%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu       371876704     69.21%     69.21% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult        1107747      0.21%     69.41% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv           49726      0.01%     69.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     69.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     69.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     69.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc        60429      0.01%     69.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.43% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       85873478     15.98%     85.41% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      78371192     14.59%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total        534790277                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events             23063916                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                  1222566942                       # The number of ROB reads
-system.cpu0.rob.rob_writes                 1247016110                       # The number of ROB writes
-system.cpu0.timesIdled                        4124153                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                       24979763                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                 47054019698                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                  455072762                       # Number of Instructions Simulated
-system.cpu0.committedOps                    534790277                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.476617                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.476617                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.677224                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.677224                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               700310786                       # number of integer regfile reads
-system.cpu0.int_regfile_writes              414023994                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                   859135                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                  476716                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                127822251                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes               129020802                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads             1207381115                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes              15553504                       # number of misc regfile writes
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements         10794591                       # number of replacements
+system.cpu0.commit.op_class_0::total        537339276                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events             23160098                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                  1226917419                       # The number of ROB reads
+system.cpu0.rob.rob_writes                 1253216154                       # The number of ROB writes
+system.cpu0.timesIdled                        4189702                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                       25389842                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                 54362488365                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                  457096110                       # Number of Instructions Simulated
+system.cpu0.committedOps                    537339276                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.474080                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.474080                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.678389                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.678389                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads               703759932                       # number of integer regfile reads
+system.cpu0.int_regfile_writes              416323236                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                   842814                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                  524896                       # number of floating regfile writes
+system.cpu0.cc_regfile_reads                127590054                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes               128777466                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads             1210356696                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes              15381690                       # number of misc regfile writes
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.tags.replacements         10779491                       # number of replacements
 system.cpu0.dcache.tags.tagsinuse          511.983410                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          308312311                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs         10795103                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            28.560386                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.total_refs          308062266                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs         10780003                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            28.577197                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle       1667914500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   290.025597                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   221.957813                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.566456                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.433511                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   303.491043                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   208.492367                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.592756                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.407212                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999968                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          169                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          327                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           16                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          175                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          317                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           20                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses       1361016734                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses      1361016734                       # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data     81465542                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     81638403                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total      163103945                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     68252369                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data     68428120                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total     136680489                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       200713                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data       207163                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       407876                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       171912                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu1.data       153997                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       325909                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1802432                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1798763                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      3601195                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2076413                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data      2068312                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      4144725                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    149889823                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data    150220520                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       300110343                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    150090536                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data    150427683                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      300518219                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      6267923                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data      6604970                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total     12872893                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      6633530                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data      6545682                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total     13179212                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       651993                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data       686156                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total      1338149                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       638733                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu1.data       602965                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total      1241698                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       328325                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       330976                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       659301                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data            8                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu1.data            5                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total           13                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data     13540186                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data     13753617                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total      27293803                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data     14192179                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data     14439773                       # number of overall misses
-system.cpu0.dcache.overall_misses::total     28631952                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  95137339500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 103283573000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 198420912500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 235524203196                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 229624162852                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 465148366048                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  14948853955                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data  13357374592                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total  28306228547                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4139762000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   4347889500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   8487651500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       110000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       214000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total       324000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 345610396651                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data 346265110444                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 691875507095                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 345610396651                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data 346265110444                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 691875507095                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     87733465                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     88243373                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total    175976838                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     74885899                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data     74973802                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total    149859701                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       852706                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       893319                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total      1746025                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       810645                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       756962                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total      1567607                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2130757                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      2129739                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      4260496                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2076421                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      2068317                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      4144738                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    163430009                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data    163974137                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    327404146                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    164282715                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data    164867456                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    329150171                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.071443                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.074849                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.073151                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.088582                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.087306                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.087944                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.764616                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.768097                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.766397                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.787932                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.796559                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.792098                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.154088                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.155407                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.154747                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000004                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000002                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000003                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.082850                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.083877                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.083364                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.086389                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.087584                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.086988                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15178.447390                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15637.250888                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 15413.855495                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35505.108622                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35080.250286                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 35294.095432                       # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 23403.916746                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 22152.819139                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 22796.387324                       # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12608.732201                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13136.570325                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12873.712462                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        13750                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        42800                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24923.076923                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25524.789442                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25176.294385                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 25349.179339                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24352.172887                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23979.955256                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 24164.454701                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs     50137821                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets        53336                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs          3624490                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets            999                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    13.833069                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    53.389389                       # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks      8255712                       # number of writebacks
-system.cpu0.dcache.writebacks::total          8255712                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3390240                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data      3655769                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total      7046009                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      5522660                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      5441791                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total     10964451                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         3462                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu1.data         3529                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::total         6991                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       202418                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data       203699                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total       406117                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      8916362                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data      9101089                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total     18017451                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      8916362                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data      9101089                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total     18017451                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2877683                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2949201                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      5826884                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1110870                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1103891                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      2214761                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       642919                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       670026                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total      1312945                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       635271                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       599436                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total      1234707                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       125907                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       127277                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       253184                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            8                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            5                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total           13                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      4623824                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data      4652528                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      9276352                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      5266743                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data      5322554                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total     10589297                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        18054                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        15626                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.tags.tag_accesses       1359846782                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses      1359846782                       # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.ReadReq_hits::cpu0.data     81913095                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data     81085676                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total      162998771                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     68945283                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data     67608016                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total     136553299                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       203242                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data       204927                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       408169                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       172243                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu1.data       153828                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       326071                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1807303                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1793639                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      3600942                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2085816                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data      2057165                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      4142981                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    151030621                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data    148847520                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       299878141                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    151233863                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data    149052447                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      300286310                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      6333331                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data      6515820                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total     12849151                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      6514171                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data      6636089                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total     13150260                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       640566                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data       698533                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total      1339099                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       645837                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu1.data       595706                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total      1241543                       # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       333547                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       322838                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       656385                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data           13                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu1.data            8                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total           21                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data     13493339                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data     13747615                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total      27240954                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data     14133905                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data     14446148                       # number of overall misses
+system.cpu0.dcache.overall_misses::total     28580053                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  98901247500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  99537012000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 198438259500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 227853900939                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 237216026267                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 465069927206                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  15046942422                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data  13204575493                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total  28251517915                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4379004500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   4078607000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   8457611500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       179500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       254000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total       433500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 341802090861                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data 349957613760                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 691759704621                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 341802090861                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data 349957613760                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 691759704621                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     88246426                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data     87601496                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total    175847922                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     75459454                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data     74244105                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total    149703559                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       843808                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       903460                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total      1747268                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       818080                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       749534                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total      1567614                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2140850                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      2116477                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      4257327                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2085829                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      2057173                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      4143002                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    164523960                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data    162595135                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    327119095                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    165367768                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data    163498595                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    328866363                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.071769                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.074380                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.073070                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.086327                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.089382                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.087842                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.759137                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.773175                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.766396                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.789455                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.794768                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.791995                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.155801                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.152536                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.154178                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000006                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000004                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000005                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.082014                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.084551                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.083275                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.085470                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.088356                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.086905                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15615.992201                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15276.206525                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 15443.686474                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34978.188466                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35746.359982                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 35365.835140                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 23298.359218                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 22166.262373                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 22755.166688                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13128.598069                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12633.602612                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12885.138295                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13807.692308                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        31750                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20642.857143                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25331.171985                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25455.878257                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 25394.107145                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24183.132040                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 24224.977742                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 24204.283478                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs     50179402                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets        52249                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs          3620965                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets           1011                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    13.858019                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    51.680514                       # average number of cycles each access was blocked
+system.cpu0.dcache.writebacks::writebacks      8246145                       # number of writebacks
+system.cpu0.dcache.writebacks::total          8246145                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3422225                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data      3613055                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total      7035280                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      5423611                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      5531095                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total     10954706                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         3582                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu1.data         3404                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::total         6986                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       204425                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data       198944                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total       403369                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      8849418                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data      9147554                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total     17996972                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      8849418                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data      9147554                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total     17996972                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2911106                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2902765                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      5813871                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1090560                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1104994                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      2195554                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       631874                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       682564                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total      1314438                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       642255                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       592302                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total      1234557                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       129122                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       123894                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       253016                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data           13                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            8                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total           21                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      4643921                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data      4600061                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      9243982                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      5275795                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data      5282625                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total     10558420                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        17861                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        15819                       # number of ReadReq MSHR uncacheable
 system.cpu0.dcache.ReadReq_mshr_uncacheable::total        33680                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        19503                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        14194                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        18882                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        14815                       # number of WriteReq MSHR uncacheable
 system.cpu0.dcache.WriteReq_mshr_uncacheable::total        33697                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        37557                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        29820                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        36743                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        30634                       # number of overall MSHR uncacheable misses
 system.cpu0.dcache.overall_mshr_uncacheable_misses::total        67377                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  44005676000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  46542154500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  90547830500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  40688703147                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  39847716140                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  80536419287                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  10144598500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  12204187000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  22348785500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  14171149455                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  12627536592                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  26798686047                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1695865500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1763125500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   3458991000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       102000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       209000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       311000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  98865528602                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  99017407232                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 197882935834                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 109010127102                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 111221594232                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 220231721334                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3418077000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2846181000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6264258000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3418077000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   2846181000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6264258000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.032800                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033421                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.033112                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.014834                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014724                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014779                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.753975                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.750041                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.751962                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.783661                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.791897                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.787638                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059090                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.059762                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059426                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000004                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000002                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000003                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028292                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.028374                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.028333                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.032059                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.032284                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.032172                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15292.051279                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15781.275844                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15539.665883                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36627.781061                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36097.509754                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36363.480884                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15778.968268                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18214.497646                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17021.874869                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 22307.250693                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 21065.696074                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 21704.490253                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13469.191546                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13852.663875                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13661.965211                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        12750                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        41800                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23923.076923                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21381.767256                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21282.495717                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21331.977898                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20697.825412                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20896.282918                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20797.577151                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189325.191093                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 182143.926789                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185993.408551                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 91010.384216                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95445.372233                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92973.240126                       # average overall mshr uncacheable latency
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements         16455853                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.958473                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          172258590                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs         16456365                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            10.467597                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      12245675500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   274.034812                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   237.923660                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.535224                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.464695                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999919                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  45537932500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  44832999500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  90370932000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  39266250291                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  40577595959                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  79843846250                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  10081360000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  12415038000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  22496398000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  14258396422                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  12486057493                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  26744453915                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1802187500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1654747000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   3456934500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       166500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       246000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       412500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  99062579213                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  97896652952                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 196959232165                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 109143939213                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 110311690952                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 219455630165                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3399664500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2864633000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6264297500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3399664500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   2864633000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6264297500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.032988                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033136                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.033062                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.014452                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014883                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014666                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.748836                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.755500                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.752282                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.785076                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.790227                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.787539                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.060313                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.058538                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059431                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000006                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000004                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000005                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028226                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.028292                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.028259                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.031903                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.032310                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.032106                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15642.828705                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15444.929059                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15544.020843                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36005.584554                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36722.005693                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36366.150070                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15954.699829                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18188.826249                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17114.841476                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 22200.522257                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 21080.559399                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 21663.198957                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13957.245861                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13356.151226                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13662.908670                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 12807.692308                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        30750                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19642.857143                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21331.667617                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21281.598864                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21306.752021                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20687.676305                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20881.984042                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20784.893020                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190340.098539                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 181088.121879                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185994.581354                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 92525.501456                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 93511.555788                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92973.826380                       # average overall mshr uncacheable latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.tags.replacements         16451372                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.708511                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          172021238                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs         16451884                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            10.456021                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      12245439500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   287.829103                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   223.879408                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.562166                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.437264                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999431                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          133                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          301                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           78                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          157                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          287                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        206421083                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       206421083                       # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst     85737880                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     86520710                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      172258590                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     85737880                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     86520710                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       172258590                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     85737880                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     86520710                       # number of overall hits
-system.cpu0.icache.overall_hits::total      172258590                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      8741497                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst      8964407                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total     17705904                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      8741497                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst      8964407                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total      17705904                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      8741497                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst      8964407                       # number of overall misses
-system.cpu0.icache.overall_misses::total     17705904                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 114800370390                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 118124161372                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 232924531762                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 114800370390                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst 118124161372                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 232924531762                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 114800370390                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst 118124161372                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 232924531762                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     94479377                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     95485117                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    189964494                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     94479377                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     95485117                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    189964494                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     94479377                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     95485117                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    189964494                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.092523                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.093883                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.093206                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.092523                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.093883                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.093206                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.092523                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.093883                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.093206                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13132.804414                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13177.019001                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13155.190029                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13132.804414                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13177.019001                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13155.190029                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13132.804414                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13177.019001                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13155.190029                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs        86344                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses        206174057                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       206174057                       # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.ReadReq_hits::cpu0.inst     86244738                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     85776500                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      172021238                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     86244738                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst     85776500                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       172021238                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     86244738                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst     85776500                       # number of overall hits
+system.cpu0.icache.overall_hits::total      172021238                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      8850303                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst      8850359                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total     17700662                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      8850303                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst      8850359                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total      17700662                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      8850303                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst      8850359                       # number of overall misses
+system.cpu0.icache.overall_misses::total     17700662                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 116359281374                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 116489940381                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 232849221755                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 116359281374                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst 116489940381                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 232849221755                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 116359281374                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst 116489940381                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 232849221755                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     95095041                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst     94626859                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    189721900                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     95095041                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst     94626859                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    189721900                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     95095041                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst     94626859                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    189721900                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.093068                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.093529                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.093298                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.093068                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.093529                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.093298                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.093068                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.093529                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.093298                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13147.491264                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13162.171205                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13154.831257                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13147.491264                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13162.171205                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13154.831257                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13147.491264                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13162.171205                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13154.831257                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs        90295                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs             7449                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs             7581                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    11.591355                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    11.910698                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks     16455853                       # number of writebacks
-system.cpu0.icache.writebacks::total         16455853                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       615386                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst       633929                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total      1249315                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst       615386                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu1.inst       633929                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total      1249315                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst       615386                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu1.inst       633929                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total      1249315                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      8126111                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      8330478                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total     16456589                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      8126111                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst      8330478                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total     16456589                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      8126111                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst      8330478                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total     16456589                       # number of overall MSHR misses
+system.cpu0.icache.writebacks::writebacks     16451372                       # number of writebacks
+system.cpu0.icache.writebacks::total         16451372                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       621647                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst       626857                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total      1248504                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst       621647                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu1.inst       626857                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total      1248504                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst       621647                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu1.inst       626857                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total      1248504                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      8228656                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      8223502                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total     16452158                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      8228656                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst      8223502                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total     16452158                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      8228656                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst      8223502                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total     16452158                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        12438                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst         8200                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total        20638                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        12438                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst         8200                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total        20638                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 101760931927                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 104688612913                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 206449544840                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 101760931927                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 104688612913                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 206449544840                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 101760931927                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 104688612913                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 206449544840                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 103166162413                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 103212304918                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 206378467331                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 103166162413                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 103212304918                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 206378467331                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 103166162413                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 103212304918                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 206378467331                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    974276500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst    641521000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   1615797500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    974276500                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst    641521000                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total   1615797500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.086009                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.087244                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.086630                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.086009                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.087244                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.086630                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.086009                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.087244                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.086630                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12522.710055                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12566.939486                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12545.099403                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12522.710055                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12566.939486                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12545.099403                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12522.710055                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12566.939486                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12545.099403                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.086531                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.086905                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.086717                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.086531                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.086905                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.086717                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.086531                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.086905                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.086717                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12537.425603                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12550.894366                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12544.157875                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12537.425603                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12550.894366                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12544.157875                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12537.425603                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12550.894366                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12544.157875                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 78330.639974                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78234.268293                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 78292.349065                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 78330.639974                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78234.268293                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 78292.349065                       # average overall mshr uncacheable latency
-system.cpu1.branchPred.lookups              134713045                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         90294354                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect          5910949                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            91937142                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               61863845                       # Number of BTB hits
+system.cpu1.branchPred.lookups              133897441                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         89938186                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect          5869763                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            91159166                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               61608831                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            67.289284                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS               17423003                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect            191945                       # Number of incorrect RAS predictions.
-system.cpu1.branchPred.indirectLookups        5099062                       # Number of indirect predictor lookups.
-system.cpu1.branchPred.indirectHits           2694305                       # Number of indirect target hits.
-system.cpu1.branchPred.indirectMisses         2404757                       # Number of indirect misses.
-system.cpu1.branchPredindirectMispredicted       414905                       # Number of mispredicted indirect branches.
-system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
+system.cpu1.branchPred.BTBHitPct            67.583803                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS               17197784                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect            191914                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.indirectLookups        5022071                       # Number of indirect predictor lookups.
+system.cpu1.branchPred.indirectHits           2642299                       # Number of indirect target hits.
+system.cpu1.branchPred.indirectMisses         2379772                       # Number of indirect misses.
+system.cpu1.branchPredindirectMispredicted       413417                       # Number of mispredicted indirect branches.
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1408,89 +1418,93 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dtb.walker.walks                   940458                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong               940458                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        17835                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        93375                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore       588116                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples       352342                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean  2605.512542                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 15403.554578                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-65535       349554     99.21%     99.21% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::65536-131071         1910      0.54%     99.75% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::131072-196607          467      0.13%     99.88% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::196608-262143          147      0.04%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::262144-327679          145      0.04%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::327680-393215           35      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::393216-458751           66      0.02%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::458752-524287           10      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::524288-589823            8      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total       352342                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples       440653                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 22932.098499                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 18696.328712                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 16830.741238                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535       430922     97.79%     97.79% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071         8564      1.94%     99.74% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607          599      0.14%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143          434      0.10%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679           89      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215           36      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total       440653                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 323076797592                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.107209                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.744323                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0-3 321987662592     99.66%     99.66% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4-7    587014500      0.18%     99.84% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8-11    213123500      0.07%     99.91% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12-15    130553500      0.04%     99.95% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::16-19     52805000      0.02%     99.97% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::20-23     28221000      0.01%     99.98% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::24-27     26598000      0.01%     99.98% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::28-31     43358000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::32-35      6987500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::36-39       426000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::40-43        21000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::44-47        16500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::48-51        10000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::52-55          500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 323076797592                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        93376     83.96%     83.96% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M        17835     16.04%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total       111211                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       940458                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.walker.walks                   900943                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               900943                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        17588                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        92135                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore       552674                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples       348269                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean  2521.581019                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 15048.371457                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-65535       345488     99.20%     99.20% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::65536-131071         1911      0.55%     99.75% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::131072-196607          471      0.14%     99.89% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::196608-262143          154      0.04%     99.93% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::262144-327679          142      0.04%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::327680-393215           31      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::393216-458751           66      0.02%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::458752-524287            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::589824-655359            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total       348269                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples       416714                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 22183.198789                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 17895.949159                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 17072.754814                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535       407840     97.87%     97.87% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071         7849      1.88%     99.75% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607          499      0.12%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143          336      0.08%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679          108      0.03%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215           63      0.02%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751           13      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total       416714                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 309953543704                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.014716                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.659727                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0-3 308957195204     99.68%     99.68% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4-7    543608000      0.18%     99.85% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8-11    198540500      0.06%     99.92% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12-15    120617500      0.04%     99.96% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::16-19     43978000      0.01%     99.97% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::20-23     24203000      0.01%     99.98% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::24-27     22128500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::28-31     36223000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::32-35      6651000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::36-39       321500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::40-43        27000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::44-47        20000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::48-51         8000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::52-55         5500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::56-59         6000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::60-63        11000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 309953543704                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        92135     83.97%     83.97% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M        17588     16.03%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total       109723                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       900943                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       940458                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       111211                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       900943                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       109723                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       111211                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total      1051669                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       109723                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total      1010666                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                   107105213                       # DTB read hits
-system.cpu1.dtb.read_misses                    647862                       # DTB read misses
-system.cpu1.dtb.write_hits                   82338491                       # DTB write hits
-system.cpu1.dtb.write_misses                   292596                       # DTB write misses
-system.cpu1.dtb.flush_tlb                        1087                       # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits                   106418453                       # DTB read hits
+system.cpu1.dtb.read_misses                    624156                       # DTB read misses
+system.cpu1.dtb.write_hits                   81533380                       # DTB write hits
+system.cpu1.dtb.write_misses                   276787                       # DTB write misses
+system.cpu1.dtb.flush_tlb                        1086                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              21707                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_mva_asid              22079                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                    541                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   54922                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      184                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  9726                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries                   55782                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      176                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  9564                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    55049                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses               107753075                       # DTB read accesses
-system.cpu1.dtb.write_accesses               82631087                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    55148                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses               107042609                       # DTB read accesses
+system.cpu1.dtb.write_accesses               81810167                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        189443704                       # DTB hits
-system.cpu1.dtb.misses                         940458                       # DTB misses
-system.cpu1.dtb.accesses                    190384162                       # DTB accesses
-system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.hits                        187951833                       # DTB hits
+system.cpu1.dtb.misses                         900943                       # DTB misses
+system.cpu1.dtb.accesses                    188852776                       # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1520,410 +1534,404 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.cpu1.itb.walker.walks                   101953                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong               101953                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2         3135                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        69070                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore        14166                       # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples        87787                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean  1451.501931                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev  9077.444806                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-32767        86783     98.86%     98.86% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::32768-65535          614      0.70%     99.56% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::65536-98303          230      0.26%     99.82% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::98304-131071          110      0.13%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::131072-163839           22      0.03%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::163840-196607            8      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::196608-229375            8      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.cpu1.itb.walker.walks                   102336                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong               102336                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2         3041                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        69360                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore        14089                       # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples        88247                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean  1349.994901                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev  8816.342326                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-32767        87374     99.01%     99.01% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::32768-65535          501      0.57%     99.58% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::65536-98303          211      0.24%     99.82% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::98304-131071          117      0.13%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::131072-163839           19      0.02%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::163840-196607            9      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::196608-229375            2      0.00%     99.98% # Table walker wait (enqueue to first request) latency
 system.cpu1.itb.walker.walkWaitTime::229376-262143            3      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::262144-294911            5      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::294912-327679            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::327680-360447            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::262144-294911            5      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::294912-327679            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::327680-360447            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu1.itb.walker.walkWaitTime::360448-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        87787                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        86371                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 28729.370969                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 24395.132531                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 18742.067885                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-32767        47141     54.58%     54.58% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-65535        37044     42.89%     97.47% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-98303          924      1.07%     98.54% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::98304-131071          961      1.11%     99.65% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-163839           89      0.10%     99.75% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::163840-196607           90      0.10%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-229375           58      0.07%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::229376-262143           20      0.02%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-294911           15      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::294912-327679            6      0.01%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-360447           13      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::360448-393215            4      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-425983            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::425984-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        86371                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 610837012424                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean     0.919047                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev     0.273178                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0    49510897620      8.11%      8.11% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1   561270328804     91.89%     99.99% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2       50540500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::3        4377500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::4         769000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::5          99000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 610837012424                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        69070     95.66%     95.66% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M         3135      4.34%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        72205                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        88247                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        86490                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 27376.708290                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 22843.157676                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 18954.672615                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535        84456     97.65%     97.65% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071         1746      2.02%     99.67% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607          174      0.20%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143           67      0.08%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679           29      0.03%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215            9      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751            4      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-524287            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        86490                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 610599891424                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean     0.922621                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev     0.267613                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0    47307697252      7.75%      7.75% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1   563239770172     92.24%     99.99% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2       45620000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::3        5915500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::4         874500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::5          14000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 610599891424                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K        69360     95.80%     95.80% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M         3041      4.20%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        72401                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst       101953                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total       101953                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst       102336                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total       102336                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        72205                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        72205                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       174158                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    95706620                       # ITB inst hits
-system.cpu1.itb.inst_misses                    101953                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        72401                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        72401                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       174737                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                    94847182                       # ITB inst hits
+system.cpu1.itb.inst_misses                    102336                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                        1087                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb                        1086                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              21707                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_mva_asid              22079                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                    541                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   39902                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                   41108                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                   192638                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                   191650                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                95808573                       # ITB inst accesses
-system.cpu1.itb.hits                         95706620                       # DTB hits
-system.cpu1.itb.misses                         101953                       # DTB misses
-system.cpu1.itb.accesses                     95808573                       # DTB accesses
-system.cpu1.numPwrStateTransitions              16900                       # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples         8450                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean    3209165135.406272                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev   63386513065.949989                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::underflows         3583     42.40%     42.40% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1000-5e+10         4849     57.38%     99.79% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::5e+10-1e+11            3      0.04%     99.82% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11            2      0.02%     99.85% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11            1      0.01%     99.86% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11            1      0.01%     99.87% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::overflows           10      0.12%    100.00% # Distribution of time spent in the clock gated state
+system.cpu1.itb.inst_accesses                94949518                       # ITB inst accesses
+system.cpu1.itb.hits                         94847182                       # DTB hits
+system.cpu1.itb.misses                         102336                       # DTB misses
+system.cpu1.itb.accesses                     94949518                       # DTB accesses
+system.cpu1.numPwrStateTransitions              16690                       # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples         8345                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean    2811784025.136968                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev   54125884171.976646                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows         3484     41.75%     41.75% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10         4842     58.02%     99.77% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5e+10-1e+11            4      0.05%     99.82% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11            1      0.01%     99.83% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11            2      0.02%     99.86% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11            3      0.04%     99.89% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11            1      0.01%     99.90% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::overflows            8      0.10%    100.00% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::max_value 1988782300428                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total           8450                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON   24199778551817                       # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 27117445394183                       # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles                       673200080                       # number of cpu cycles simulated
+system.cpu1.pwrStateClkGateDist::max_value 1988782282928                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total           8345                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON   27852879525232                       # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 23464337689768                       # Cumulative time (in ticks) in various power states
+system.cpu1.numCycles                       669110072                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles         250326293                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                     598056519                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                  134713045                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches          81981153                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                    383149579                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles               13468488                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                   2515216                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles               21179                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingDrainCycles             3210                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu1.fetch.PendingTrapStallCycles      4838435                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       163101                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles         2842                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                 95493345                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes              3679546                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                  39276                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         647753829                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.079477                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.330780                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles         247318637                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                     594168769                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                  133897441                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches          81448914                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                    382780415                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles               13369418                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                   2469656                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles               22020                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles             2942                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles      4831905                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       160199                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles         2485                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                 94635082                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes              3655757                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                  39111                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         644272699                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.077858                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.328781                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0               500909169     77.33%     77.33% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                18369194      2.84%     80.17% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                18392289      2.84%     83.01% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                13444419      2.08%     85.08% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                28522776      4.40%     89.48% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                 9079206      1.40%     90.89% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                 9809102      1.51%     92.40% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                 8415106      1.30%     93.70% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                40812568      6.30%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0               498403789     77.36%     77.36% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                18180113      2.82%     80.18% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                18298329      2.84%     83.02% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                13344455      2.07%     85.09% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                28485052      4.42%     89.51% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                 9005401      1.40%     90.91% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                 9710824      1.51%     92.42% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                 8365736      1.30%     93.72% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                40479000      6.28%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           647753829                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.200108                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.888379                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles               203038997                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles            318780583                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                106758002                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles             13823689                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               5350357                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved            19769330                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred              1403755                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts             652115787                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts              4334955                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               5350357                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles               210763548                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles               23644830                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles     256196843                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                112721527                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles             39074336                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts             636556128                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                84527                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents               2214646                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents               1724456                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents              19278197                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.FullRegisterEvents            3720                       # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands          608321142                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            977030287                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups       750414618                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups           813643                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps            510669806                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                97651331                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts          15437965                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts      13428690                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                 76999253                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads           102745060                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores           86542127                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads         13847171                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores        14669306                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                 603448531                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded           15520984                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                604287606                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued           888730                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined       83031386                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     52028805                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        367516                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    647753829                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.932897                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.658052                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total           644272699                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.200113                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.887999                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles               200592206                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles            318637226                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                105865940                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles             13861849                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               5313208                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved            19620033                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred              1391095                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts             647812132                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts              4304218                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               5313208                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles               208315491                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles               23091878                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles     256219950                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                111868936                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles             39460643                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts             632346200                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                89809                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents               2171113                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents               1552755                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents              19722377                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.FullRegisterEvents            3888                       # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands          605326116                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            973029596                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups       745395954                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups           835166                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps            508286647                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                97039469                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts          15581908                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts      13599233                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                 77351395                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads           101957824                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores           85683722                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads         13730276                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores        14508656                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                 599162654                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded           15675959                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                600368831                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued           870257                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined       82392045                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     51705579                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        355230                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    644272699                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.931855                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.655757                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0          411149730     63.47%     63.47% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1           99844018     15.41%     78.89% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2           43674585      6.74%     85.63% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3           31388880      4.85%     90.48% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4           23216755      3.58%     94.06% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5           16246972      2.51%     96.57% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6           11234988      1.73%     98.30% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7            6567238      1.01%     99.32% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8            4430663      0.68%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0          408550840     63.41%     63.41% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1          100016688     15.52%     78.94% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2           43398898      6.74%     85.67% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3           31119922      4.83%     90.50% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4           23055723      3.58%     94.08% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5           16110351      2.50%     96.58% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6           11122843      1.73%     98.31% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7            6496596      1.01%     99.32% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8            4400838      0.68%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      647753829                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      644272699                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                3092955     25.56%     25.56% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                 25896      0.21%     25.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                   3078      0.03%     25.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     25.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     25.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     25.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     25.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     25.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     25.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     25.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     25.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     25.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     25.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     25.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     25.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     25.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     25.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     25.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     25.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     25.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     25.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     25.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     25.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     25.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     25.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     25.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     25.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     25.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead               4978648     41.15%     66.95% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite              3998858     33.05%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                3033866     25.31%     25.31% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                 23473      0.20%     25.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                   1799      0.02%     25.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     25.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     25.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     25.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%     25.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     25.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     25.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     25.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     25.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     25.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     25.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     25.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     25.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%     25.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     25.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%     25.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     25.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     25.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     25.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     25.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     25.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     25.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     25.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     25.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     25.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     25.52% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead               4963680     41.42%     66.94% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite              3962195     33.06%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass               54      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu            409873437     67.83%     67.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult             1473632      0.24%     68.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                67911      0.01%     68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                190      0.00%     68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                  16      0.00%     68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               1      0.00%     68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt             24      0.00%     68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc         71982      0.01%     68.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead           109389956     18.10%     86.20% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite           83410380     13.80%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass               57      0.00%      0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu            407511218     67.88%     67.88% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult             1473925      0.25%     68.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                66979      0.01%     68.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                186      0.00%     68.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                  16      0.00%     68.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               1      0.00%     68.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              9      0.00%     68.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp             14      0.00%     68.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt             24      0.00%     68.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc         58109      0.01%     68.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead           108674321     18.10%     86.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite           82583972     13.76%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total             604287606                       # Type of FU issued
-system.cpu1.iq.rate                          0.897634                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                   12099435                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.020023                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads        1868279780                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes        702174546                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses    581222842                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads            1037426                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes            531508                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses       461103                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses             615834413                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                 552574                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads         4729905                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total             600368831                       # Type of FU issued
+system.cpu1.iq.rate                          0.897265                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                   11985013                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.019963                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads        1856828451                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes        697391618                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses    577348747                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads            1037180                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes            532278                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses       459183                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses             611800062                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                 553725                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads         4645881                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads     17106229                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses        20767                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation       716806                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores      8739633                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads     16996855                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses        20011                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation       704534                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores      8628630                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads      3947805                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked      8490514                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads      3900409                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked      8595303                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               5350357                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles               15089845                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles              6765703                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts          619117650                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts          1756443                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts            102745060                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts            86542127                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts          13138616                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                241917                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents              6436383                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents        716806                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect       2534366                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect      2735696                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts             5270062                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts            597242145                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts            107094882                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts          6118047                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles               5313208                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles               14601213                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles              6790244                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts          614987274                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts          1737370                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts            101957824                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts            85683722                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts          13306309                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                234327                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents              6472536                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents        704534                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect       2511910                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect      2724374                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts             5236284                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts            593397792                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts            106407717                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts          6082445                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       148135                       # number of nop insts executed
-system.cpu1.iew.exec_refs                   189434078                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches               110489810                       # Number of branches executed
-system.cpu1.iew.exec_stores                  82339196                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.887169                       # Inst execution rate
-system.cpu1.iew.wb_sent                     583107932                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                    581683945                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                287154690                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                498859903                       # num instructions consuming a value
-system.cpu1.iew.wb_rate                      0.864058                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.575622                       # average fanout of values written-back
-system.cpu1.commit.commitSquashedInsts       83090114                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls       15153468                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts          4526792                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    633652727                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.845792                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.838559                       # Number of insts commited each cycle
+system.cpu1.iew.exec_nop                       148661                       # number of nop insts executed
+system.cpu1.iew.exec_refs                   187941905                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches               109851293                       # Number of branches executed
+system.cpu1.iew.exec_stores                  81534188                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.886846                       # Inst execution rate
+system.cpu1.iew.wb_sent                     579236319                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                    577807930                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                285288573                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                495728954                       # num instructions consuming a value
+system.cpu1.iew.wb_rate                      0.863547                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.575493                       # average fanout of values written-back
+system.cpu1.commit.commitSquashedInsts       82442886                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls       15320729                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts          4497993                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    630278595                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.844780                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.835584                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0    436801872     68.93%     68.93% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1     97306167     15.36%     84.29% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2     33196725      5.24%     89.53% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3     15570610      2.46%     91.99% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4     11096620      1.75%     93.74% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5      6694600      1.06%     94.79% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6      6152090      0.97%     95.77% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7      3917687      0.62%     96.38% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8     22916356      3.62%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0    433887749     68.84%     68.84% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1     97721864     15.50%     84.35% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2     32952593      5.23%     89.57% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3     15389192      2.44%     92.02% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4     10994625      1.74%     93.76% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5      6638239      1.05%     94.81% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6      6092126      0.97%     95.78% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7      3888165      0.62%     96.40% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8     22714042      3.60%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    633652727                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts           456128288                       # Number of instructions committed
-system.cpu1.commit.committedOps             535938124                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    630278595                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts           453286692                       # Number of instructions committed
+system.cpu1.commit.committedOps             532446568                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                     163441324                       # Number of memory references committed
-system.cpu1.commit.loads                     85638830                       # Number of loads committed
-system.cpu1.commit.membars                    3762780                       # Number of memory barriers committed
-system.cpu1.commit.branches                 101898340                       # Number of branches committed
-system.cpu1.commit.fp_insts                    443284                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                491997101                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls            13483818                       # Number of function calls committed.
+system.cpu1.commit.refs                     162016061                       # Number of memory references committed
+system.cpu1.commit.loads                     84960969                       # Number of loads committed
+system.cpu1.commit.membars                    3734725                       # Number of memory barriers committed
+system.cpu1.commit.branches                 101308962                       # Number of branches committed
+system.cpu1.commit.fp_insts                    440790                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                488486887                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls            13305521                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu       371242424     69.27%     69.27% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult        1140857      0.21%     69.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv           50916      0.01%     69.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            8      0.00%     69.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp           13      0.00%     69.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt           21      0.00%     69.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc        62561      0.01%     69.50% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.50% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.50% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.50% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead       85638830     15.98%     85.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite      77802494     14.52%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu       369191199     69.34%     69.34% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult        1139544      0.21%     69.55% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv           50295      0.01%     69.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            8      0.00%     69.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp           13      0.00%     69.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt           21      0.00%     69.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc        49427      0.01%     69.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.57% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead       84960969     15.96%     85.53% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite      77055092     14.47%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total        535938124                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events             22916356                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                  1225792229                       # The number of ROB reads
-system.cpu1.rob.rob_writes                 1252182686                       # The number of ROB writes
-system.cpu1.timesIdled                        4237640                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                       25446251                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                 54234885938                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                  456128288                       # Number of Instructions Simulated
-system.cpu1.committedOps                    535938124                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.475901                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.475901                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.677552                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.677552                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads               703163553                       # number of integer regfile reads
-system.cpu1.int_regfile_writes              415853151                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                   819685                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                  527216                       # number of floating regfile writes
-system.cpu1.cc_regfile_reads                127646217                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes               128772606                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads             1207600226                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes              15276931                       # number of misc regfile writes
-system.iobus.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq                40295                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40295                       # Transaction distribution
+system.cpu1.commit.op_class_0::total        532446568                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events             22714042                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                  1218446611                       # The number of ROB reads
+system.cpu1.rob.rob_writes                 1243796841                       # The number of ROB writes
+system.cpu1.timesIdled                        4173884                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                       24837373                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                 46928670537                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                  453286692                       # Number of Instructions Simulated
+system.cpu1.committedOps                    532446568                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              1.476130                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.476130                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.677447                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.677447                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads               698541221                       # number of integer regfile reads
+system.cpu1.int_regfile_writes              412892879                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                   836436                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                  478776                       # number of floating regfile writes
+system.cpu1.cc_regfile_reads                127759728                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes               128888879                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads             1201368002                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes              15442226                       # number of misc regfile writes
+system.iobus.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.iobus.trans_dist::ReadReq                40306                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40306                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
 system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
@@ -1940,11 +1948,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230948                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230948                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230970                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230970                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353732                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353754                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
@@ -1959,18 +1967,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334224                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334224                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334312                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334312                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492144                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             47814500                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7492232                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             47813000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               345500                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               348500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                 9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy                10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
@@ -1982,79 +1990,79 @@ system.iobus.reqLayer14.occupancy                9500                       # La
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer15.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               14500                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               14000                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy                9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            25714000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            25706500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer24.occupancy            40142500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           568747115                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           568865504                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147708000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147730000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements               115455                       # number of replacements
-system.iocache.tags.tagsinuse               10.425592                       # Cycle average of tags in use
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.replacements               115466                       # number of replacements
+system.iocache.tags.tagsinuse               10.425537                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115471                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115482                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13089208185000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.544364                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.881227                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.221523                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.430077                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.651599                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13089208816000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     5.904041                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     4.521495                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.369003                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.282593                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.651596                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039623                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039623                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.tag_accesses              1039722                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039722                       # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8810                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8847                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8821                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8858                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide       115474                       # number of demand (read+write) misses
-system.iocache.demand_misses::total            115514                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide       115485                       # number of demand (read+write) misses
+system.iocache.demand_misses::total            115525                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide       115474                       # number of overall misses
-system.iocache.overall_misses::total           115514                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5085500                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1644992106                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1650077606                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide       115485                       # number of overall misses
+system.iocache.overall_misses::total           115525                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5166000                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1639680634                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1644846634                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  12805896509                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  12805896509                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5436500                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide  14450888615                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  14456325115                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5436500                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide  14450888615                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  14456325115                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  12789916870                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  12789916870                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5517000                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide  14429597504                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  14435114504                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5517000                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide  14429597504                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total  14435114504                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8810                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8847                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8821                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8858                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide       115474                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total          115514                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide       115485                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total          115525                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide       115474                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total         115514                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide       115485                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total         115525                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -2068,53 +2076,53 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137445.945946                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 186718.740749                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 186512.671640                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 139621.621622                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 185883.758531                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 185690.520885                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120058.281229                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 120058.281229                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet 135912.500000                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 125144.089709                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 125147.818576                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet 135912.500000                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 125144.089709                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 125147.818576                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         32488                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 119908.468368                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 119908.468368                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet       137925                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 124947.807109                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 124952.300403                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet       137925                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 124947.807109                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 124952.300403                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         32611                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3420                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3377                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.499415                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.656796                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.writebacks::writebacks          106630                       # number of writebacks
 system.iocache.writebacks::total               106630                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8810                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8847                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8821                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8858                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide       115474                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total       115514                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide       115485                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total       115525                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide       115474                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total       115514                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3235500                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1204492106                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1207727606                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide       115485                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total       115525                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3316000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1198630634                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1201946634                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7465855613                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   7465855613                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3436500                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   8670347719                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   8673784219                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3436500                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   8670347719                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   8673784219                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7449853156                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   7449853156                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3517000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   8648483790                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   8652000790                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3517000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   8648483790                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   8652000790                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -2128,613 +2136,610 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87445.945946                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136718.740749                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 136512.671640                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 89621.621622                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135883.758531                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 135690.520885                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69994.146226                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69994.146226                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85912.500000                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 75084.847836                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 75088.597218                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85912.500000                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 75084.847836                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 75088.597218                       # average overall mshr miss latency
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
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-system.l2c.tags.sampled_refs                  1485492                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    34.317651                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle               2400888500                       # Cycle when the warmup percentage was hit.
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-system.l2c.tags.occ_blocks::cpu0.dtb.walker   187.101749                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   261.194581                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3307.125044                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     8251.641261                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   171.238322                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   249.704860                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     3886.905366                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data    13383.155483                       # Average occupied blocks per requestor
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-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002613                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.003810                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.059309                       # Average percentage of cache occupancy
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+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69844.119440                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        87925                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 74888.373295                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 74892.887167                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        87925                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 74888.373295                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 74892.887167                       # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
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 system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
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-system.l2c.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
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-system.l2c.tags.occ_task_id_percent::1023     0.004791                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.959473                       # Percentage of cache occupancy per task id
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-system.l2c.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.l2c.ReadReq_hits::cpu0.dtb.walker       530836                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker       183475                       # number of ReadReq hits
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-system.l2c.WritebackDirty_hits::total         8255712                       # number of WritebackDirty hits
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 system.l2c.SCUpgradeReq_misses::cpu1.data            2                       # number of SCUpgradeReq misses
 system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
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+system.l2c.ReadExReq_accesses::total          2177126                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu0.inst      8228410                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu1.inst      8223225                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::total      16451635                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data      3665086                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data      3703245                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total      7368331                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu0.data       642255                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu1.data       592302                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::total      1234557                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker       532821                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker       177893                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst         8228410                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data         4747107                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker       526185                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker       175193                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst         8223225                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data         4798350                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total            27409184                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker       532821                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker       177893                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst        8228410                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data        4747107                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker       526185                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker       175193                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst        8223225                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data        4798350                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total           27409184                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.005377                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.013699                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.005409                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.013260                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.007415                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.127025                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.135791                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.131452                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.250000                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.095238                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.261089                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.267114                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.264120                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.005600                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.005804                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.005702                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.042193                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.043995                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.043099                       # miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu0.data     0.447715                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu1.data     0.391388                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::total     0.420691                       # miss rate for InvalidateReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.005377                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.013699                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.005600                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.092087                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.005409                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.013260                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.005804                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.094916                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.036370                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.005377                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.013699                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.005600                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.092087                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.005409                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.013260                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.005804                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.094916                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.036370                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 88404.013962                       # average ReadReq miss latency
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+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 88284.258609                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89758.286698                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 89197.306847                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 17726.720648                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 18183.990719                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 17965.262648                       # average UpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        84000                       # average SCUpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::total        84000                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 102131.753951                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 102289.103681                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 102209.176239                       # average ReadExReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 86248.210919                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 86103.621871                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 86171.274741                       # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 90764.124396                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 92675.117033                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 91838.407613                       # average ReadSharedReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu0.data     5.019215                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu1.data     8.236831                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::total     6.462817                       # average InvalidateReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 89496.359665                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 89765.138408                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 86248.210919                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 98468.042752                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88927.667579                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 90032.986805                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 86103.621871                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 98571.992421                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 97259.030719                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::cpu0.inst 86248.210919                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 98468.042752                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88927.667579                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 90032.986805                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 86103.621871                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 98571.992421                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 97259.030719                       # average overall miss latency
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+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 102522.297773                       # average ReadExReq miss latency
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+system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 86035.504756                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 86215.599215                       # average ReadCleanReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 90611.842190                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 93179.670765                       # average ReadSharedReq miss latency
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+system.l2c.InvalidateReq_avg_miss_latency::cpu0.data     2.392652                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu1.data     0.623328                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::total     1.602913                       # average InvalidateReq miss latency
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+system.l2c.demand_avg_miss_latency::cpu0.data 97967.907747                       # average overall miss latency
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+system.l2c.demand_avg_miss_latency::cpu1.data 99180.198972                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 97323.740751                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::cpu0.data 97967.907747                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::cpu1.data 99180.198972                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 97323.740751                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.writebacks::writebacks             1205568                       # number of writebacks
-system.l2c.writebacks::total                  1205568                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0.dtb.walker            5                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu0.itb.walker           22                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.itb.walker           36                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                63                       # number of ReadReq MSHR hits
-system.l2c.ReadCleanReq_mshr_hits::cpu1.inst            1                       # number of ReadCleanReq MSHR hits
+system.l2c.writebacks::writebacks             1205359                       # number of writebacks
+system.l2c.writebacks::total                  1205359                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu0.itb.walker           24                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.itb.walker           25                       # number of ReadReq MSHR hits
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 system.l2c.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu0.data            8                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.data           15                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total           23                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.dtb.walker            5                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.itb.walker           22                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data              8                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.itb.walker           36                       # number of demand (read+write) MSHR hits
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-system.l2c.demand_mshr_hits::cpu1.data             15                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 87                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.dtb.walker            5                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.itb.walker           22                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data             8                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.itb.walker           36                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst             1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data            15                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                87                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         2742                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         2290                       # number of ReadReq MSHR misses
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-system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         2465                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           10421                       # number of ReadReq MSHR misses
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 system.l2c.CleanEvict_mshr_misses::writebacks            2                       # number of CleanEvict MSHR misses
 system.l2c.CleanEvict_mshr_misses::total            2                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data        18541                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data        18582                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        37123                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         1976                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         2155                       # number of UpgradeReq MSHR misses
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 system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            2                       # number of SCUpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data       291422                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data       282288                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        573710                       # number of ReadExReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu0.inst        44017                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu1.inst        50056                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::total        94073                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data       138582                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data       177926                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total       316508                       # number of ReadSharedReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu0.data       287794                       # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu1.data       234192                       # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::total       521986                       # number of InvalidateReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker         2742                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker         2290                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        44017                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       430004                       # number of demand (read+write) MSHR misses
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 system.l2c.ReadReq_mshr_uncacheable::total        54318                       # number of ReadReq MSHR uncacheable
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 system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data       148000                       # number of SCUpgradeReq MSHR miss cycles
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 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    781472499                       # number of ReadReq MSHR uncacheable cycles
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 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    781472499                       # number of overall MSHR uncacheable cycles
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 system.l2c.overall_mshr_uncacheable_latency::cpu1.inst    514421000                       # number of overall MSHR uncacheable cycles
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 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
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-system.l2c.UpgradeReq_mshr_miss_rate::total     0.783715                       # mshr miss rate for UpgradeReq accesses
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-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.005717                       # mshr miss rate for ReadCleanReq accesses
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-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.042887                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.453026                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.390687                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::total     0.422761                       # mshr miss rate for InvalidateReq accesses
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-system.l2c.overall_mshr_miss_rate::cpu1.data     0.095347                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.036211                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 79480.672502                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 79973.799127                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 78926.984952                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 80245.841785                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 79614.673064                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19006.364274                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19001.533742                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19003.946341                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.127025                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.135791                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.131452                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.250000                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.095238                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.261089                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.267114                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.264120                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.005600                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.005804                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.005702                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.042190                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.043992                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.043096                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.447715                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.391388                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::total     0.420691                       # mshr miss rate for InvalidateReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.005377                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.013564                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.005600                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.092084                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.005409                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.013117                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005804                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.094914                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.036367                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.005377                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.013564                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.005600                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.092084                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.005409                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.013117                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005804                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.094914                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.036367                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 78403.491449                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 80889.556983                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 78283.557273                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 79847.693647                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 79264.777202                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19075.151822                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19117.169374                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19097.070927                       # average UpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        74000                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        74000                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 92131.695733                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92289.048897                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 92209.119710                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 76247.904832                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 76104.413936                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 76171.553698                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80764.461337                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 82677.046081                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 81839.627062                       # average ReadSharedReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20804.352231                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20903.544980                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20848.855624                       # average InvalidateReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79480.672502                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79973.799127                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 76247.904832                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 88468.255214                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 78926.984952                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 80245.841785                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76104.413936                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 88572.896818                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 87260.977881                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79480.672502                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79973.799127                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76247.904832                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 88468.255214                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 78926.984952                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 80245.841785                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76104.413936                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 88572.896818                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 87260.977881                       # average overall mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 91994.532955                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92522.282420                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 92263.003062                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 76403.188850                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 76035.170180                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 76215.948734                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80613.042243                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 83179.567594                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 81929.786467                       # average ReadSharedReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20807.504530                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20901.302761                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20849.371468                       # average InvalidateReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78403.491449                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80889.556983                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 76403.188850                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 87968.507633                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 78283.557273                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79847.693647                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76035.170180                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 89180.270785                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 87325.160425                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78403.491449                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80889.556983                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76403.188850                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 87968.507633                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 78283.557273                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79847.693647                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76035.170180                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 89180.270785                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 87325.160425                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62829.433912                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176820.593774                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177835.619506                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 62734.268293                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169639.415077                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131429.691796                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 168582.590556                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131430.161254                       # average ReadReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62829.433912                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 84999.307719                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 86446.996707                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 62734.268293                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 88892.873910                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 81111.151497                       # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests       3206101                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests      1605959                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests         3062                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 87053.861722                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 81111.441220                       # average overall mshr uncacheable latency
+system.membus.snoop_filter.tot_requests       3173701                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests      1572230                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests         3254                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadReq               54318                       # Transaction distribution
-system.membus.trans_dist::ReadResp             484167                       # Transaction distribution
+system.membus.trans_dist::ReadResp             484946                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33697                       # Transaction distribution
 system.membus.trans_dist::WriteResp             33697                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1312198                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           224447                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            37872                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1311989                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           225778                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4711                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               8                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            573072                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           573072                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        429849                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        628542                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            574465                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           574465                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        430628                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        626011                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           78                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6864                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4014812                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4144458                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237587                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       237587                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4382045                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3984552                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4114198                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237454                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       237454                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4351652                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         2212                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13728                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    142074284                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    142246058                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7247872                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7247872                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               149493930                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             2896                       # Total snoops (count)
-system.membus.snoopTraffic                     184832                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples           1757355                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.019576                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.138538                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    142199148                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    142370922                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7237952                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7237952                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               149608874                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             3063                       # Total snoops (count)
+system.membus.snoopTraffic                     195520                       # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples           1723835                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.019089                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.136837                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 1722953     98.04%     98.04% # Request fanout histogram
-system.membus.snoop_fanout::1                   34402      1.96%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 1690929     98.09%     98.09% # Request fanout histogram
+system.membus.snoop_fanout::1                   32906      1.91%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             1757355                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           114108500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             1723835                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           114103500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               51156                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5404000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5424500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          8771663634                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          8729629317                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         5453450415                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         5464439160                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           44589202                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           44651356                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
 system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
 system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
 system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
 system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
 system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
@@ -2777,89 +2782,89 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
 system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests     55371072                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests     28119352                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests         4995                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.snoop_filter.tot_requests     55313500                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests     28081340                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests         5055                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.toL2Bus.snoop_filter.tot_snoops           1866                       # Total number of snoops made to the snoop filter.
 system.toL2Bus.snoop_filter.hit_single_snoops         1866                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51317223946000                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadReq            2053309                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp          25890690                       # Transaction distribution
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.trans_dist::ReadReq            2056199                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp          25877432                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             33697                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            33697                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty      9461280                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean     16455852                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         2755609                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           47371                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq            13                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          47384                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          2180359                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         2180359                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq      16456589                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      7382467                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq      1266004                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp      1234707                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     49409857                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     32615082                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       883766                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      2568418                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              85477123                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   2107688320                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1140469546                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2969568                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      8655976                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total             3259783410                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         2003011                       # Total snoops (count)
-system.toL2Bus.snoopTraffic                  81599088                       # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples         30844610                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.026862                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.161680                       # Request fanout histogram
+system.toL2Bus.trans_dist::WritebackDirty      9451504                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean     16451372                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         2751395                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           31429                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq            21                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          31450                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          2177126                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         2177126                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq      16452157                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      7370941                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq      1264166                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp      1234557                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     49396440                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     32537915                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       866839                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      2547134                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              85348328                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   2107113280                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1138900522                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2824688                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      8472048                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total             3257310538                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         2046689                       # Total snoops (count)
+system.toL2Bus.snoopTraffic                  81942376                       # Total snoop traffic (bytes)
+system.toL2Bus.snoop_fanout::samples         30811624                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.026814                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.161540                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0               30016066     97.31%     97.31% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 828544      2.69%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0               29985433     97.32%     97.32% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 826191      2.68%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           30844610                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy        53049239176                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total           30811624                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy        53009049492                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          1413407                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          1413410                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy       24732629203                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy       24725297607                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy       15040354777                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy       15008598618                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         512966184                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy         514146176                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy        1489584962                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy        1491177210                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   16437                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                   16436                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt
index 3836d4f0c..bda055a3e 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt
@@ -1,160 +1,160 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.820975                       # Number of seconds simulated
-sim_ticks                                51820974875500                       # Number of ticks simulated
-final_tick                               51820974875500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.820973                       # Number of seconds simulated
+sim_ticks                                51820973246500                       # Number of ticks simulated
+final_tick                               51820973246500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 496355                       # Simulator instruction rate (inst/s)
-host_op_rate                                   583273                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            28752228320                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 675168                       # Number of bytes of host memory used
-host_seconds                                  1802.33                       # Real time elapsed on the host
-sim_insts                                   894595581                       # Number of instructions simulated
-sim_ops                                    1051249500                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 758799                       # Simulator instruction rate (inst/s)
+host_op_rate                                   891661                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            43998522404                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 681336                       # Number of bytes of host memory used
+host_seconds                                  1177.79                       # Real time elapsed on the host
+sim_insts                                   893704771                       # Number of instructions simulated
+sim_ops                                    1050188306                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.dtb.walker       122624                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       122112                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          2604528                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         25895856                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       149760                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       136256                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          2570820                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         25432280                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        409472                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             57443708                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      2604528                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      2570820                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5175348                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     78747648                       # Number of bytes written to this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu0.dtb.walker       125632                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker       134272                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          2648688                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         26060912                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       150272                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       137792                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          2660612                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         25358744                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        379264                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             57656188                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      2648688                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      2660612                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         5309300                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     78776832                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data             4                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data         20576                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          78768228                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         1916                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         1908                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             64977                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            404626                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         2340                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         2129                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             56295                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            397389                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6398                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                937978                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1230432                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          78797412                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         1963                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         2098                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             65667                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            407205                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         2348                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         2153                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             57698                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            396240                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           5926                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                941298                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1230888                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data                1                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data             2572                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1233005                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          2366                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          2356                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               50260                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              499718                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          2890                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          2629                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               49610                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              490772                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             7902                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1108503                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          50260                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          49610                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              99870                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1519610                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1233461                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          2424                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          2591                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               51112                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              502903                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          2900                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          2659                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               51342                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              489353                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             7319                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1112603                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          51112                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          51342                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             102455                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1520173                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data                  0                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                397                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1520007                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1519610                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         2366                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         2356                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              50260                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             499718                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         2890                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         2629                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              49610                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             491169                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            7902                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2628510                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        937978                       # Number of read requests accepted
-system.physmem.writeReqs                      1233005                       # Number of write requests accepted
-system.physmem.readBursts                      937978                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1233005                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 59999232                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     31360                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  78767552                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  57443708                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               78768228                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      490                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2262                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bw_write::total                1520570                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1520173                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         2424                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         2591                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              51112                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             502903                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         2900                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         2659                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              51342                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             489750                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            7319                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2633173                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        941298                       # Number of read requests accepted
+system.physmem.writeReqs                      1233461                       # Number of write requests accepted
+system.physmem.readBursts                      941298                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1233461                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 60206144                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     36928                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  78797632                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  57656188                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               78797412                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      577                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2247                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               55925                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               62794                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               56907                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               56516                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               54249                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               59650                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               52080                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               52710                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               54230                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              101225                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              56377                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              58912                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              52835                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              56393                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              52915                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              53770                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               75516                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               81375                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               78514                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               79379                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               75747                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               80437                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               73343                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               74340                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               74711                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               79754                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              76052                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              78875                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              73771                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              78567                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              74862                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              75500                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               57499                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               62142                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               57490                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               55825                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               53833                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               61722                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               53577                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               53386                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               55741                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              100411                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              55379                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              62273                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              51298                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              56710                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              52113                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              51322                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               75972                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               80204                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               78083                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               78701                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               75891                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               81886                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               74948                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               74400                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               74844                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               78454                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              75419                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              80852                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              73391                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              78907                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              74453                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              74808                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          33                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51820971954500                       # Total gap between requests
+system.physmem.numWrRetry                          19                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51820970325500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                   43101                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  894862                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  898182                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1230432                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    903465                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     28234                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       424                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       351                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       479                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       470                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       661                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       471                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      1195                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       317                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      410                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      171                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      178                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      122                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      117                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      113                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                       97                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                       92                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       68                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       51                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        2                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1230888                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    907166                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     28188                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       382                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       299                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       464                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       455                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       583                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       455                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      1201                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       288                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      345                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      136                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      154                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      121                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      102                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                       98                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       89                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                       85                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       65                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       45                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
@@ -166,149 +166,144 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                      1665                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                      1590                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                      1559                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                      1529                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                      1516                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                      1493                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                      1478                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                      1464                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                      1445                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                      1435                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                     1424                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                     1413                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                     1405                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                     1393                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                     1380                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    33891                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    39270                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    66568                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    69647                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    73027                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    70654                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    69180                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    71444                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    74057                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    71008                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    76504                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    74752                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    70724                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    69059                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    69030                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    66768                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    66112                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    65180                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1400                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     1294                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1211                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      885                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      653                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      687                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      585                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      394                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                      1683                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                      1619                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                      1583                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                      1562                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                      1543                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                      1521                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                      1511                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                      1493                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                      1484                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                      1481                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                     1457                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                     1448                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                     1430                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                     1420                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                     1405                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    33965                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    39434                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    66705                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    69572                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    73099                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    70516                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    69275                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    71602                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    74263                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    71156                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    76473                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    74873                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    70803                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    68999                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    68901                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    66607                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    66114                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    65182                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     1385                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     1199                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     1071                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      886                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      685                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      547                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      569                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      375                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::41                      341                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      378                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      311                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      311                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      262                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      322                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      263                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      232                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      215                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      188                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      168                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      182                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      182                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      142                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      129                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      133                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      106                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       76                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      127                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       564009                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      246.035904                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     148.070971                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     287.068931                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         250512     44.42%     44.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       146974     26.06%     70.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        49960      8.86%     79.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        27236      4.83%     84.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        18139      3.22%     87.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        12170      2.16%     89.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         8948      1.59%     91.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         7660      1.36%     92.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        42410      7.52%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         564009                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         65824                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        14.242267                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      106.817618                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          65819     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::42                      341                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      329                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      294                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      256                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      327                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      215                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      240                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      223                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      230                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      155                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      160                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      173                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      162                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      147                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      151                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      157                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       83                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       66                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       60                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       50                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       61                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       566411                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      245.410940                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     147.848960                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     286.502889                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         251457     44.39%     44.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       147984     26.13%     70.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        50578      8.93%     79.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        27084      4.78%     84.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        18527      3.27%     87.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        12015      2.12%     89.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         8676      1.53%     91.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         7490      1.32%     92.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        42600      7.52%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         566411                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         65859                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        14.283773                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      106.722670                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          65854     99.99%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            2      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::7168-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::12288-13311            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::22528-23551            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           65824                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         65824                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        18.697481                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.054439                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        6.954009                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3               139      0.21%      0.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                76      0.12%      0.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11               52      0.08%      0.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15             125      0.19%      0.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           51932     78.90%     79.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23            9755     14.82%     94.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27            1068      1.62%     95.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             579      0.88%     96.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             868      1.32%     98.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             349      0.53%     98.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              83      0.13%     98.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              31      0.05%     98.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              49      0.07%     98.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              50      0.08%     98.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              24      0.04%     99.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              26      0.04%     99.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             422      0.64%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              35      0.05%     99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              36      0.05%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              31      0.05%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              19      0.03%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               4      0.01%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               5      0.01%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               3      0.00%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               3      0.00%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.00%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.00%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111            16      0.02%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             1      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           65859                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         65859                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        18.694681                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.068066                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        6.774692                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3               123      0.19%      0.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                75      0.11%      0.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11               55      0.08%      0.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15             134      0.20%      0.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           51847     78.72%     79.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23            9800     14.88%     94.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27            1125      1.71%     95.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             552      0.84%     96.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             892      1.35%     98.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             360      0.55%     98.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              86      0.13%     98.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              48      0.07%     98.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              56      0.09%     98.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              44      0.07%     98.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              24      0.04%     99.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              39      0.06%     99.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             432      0.66%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              30      0.05%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              32      0.05%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              26      0.04%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              20      0.03%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.00%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               1      0.00%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               4      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               6      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             2      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             7      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.00%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             2      0.00%     99.95% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::124-127             3      0.00%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            12      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             6      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             3      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             4      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             3      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            17      0.03%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             3      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             2      0.00%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::188-191             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           65824                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    12248455604                       # Total ticks spent queuing
-system.physmem.totMemAccLat               29826355604                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   4687440000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       13065.19                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::192-195             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           65859                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    12279482516                       # Total ticks spent queuing
+system.physmem.totMemAccLat               29918001266                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   4703605000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       13053.27                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31815.19                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  31803.27                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           1.16                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           1.52                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        1.11                       # Average system read bandwidth in MiByte/s
@@ -318,42 +313,42 @@ system.physmem.busUtil                           0.02                       # Da
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         9.53                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     705562                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    898659                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   75.26                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.02                       # Row buffer hit rate for writes
-system.physmem.avgGap                     23869819.32                       # Average gap between requests
-system.physmem.pageHitRate                      73.99                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 2151787680                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 1174090500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                3516442800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               4008858480                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3384694126320                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1301405336775                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29951001041250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34647951683805                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.608648                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49825590774964                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1730416220000                       # Time in different power states
+system.physmem.avgWrQLen                        11.56                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     706352                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    899170                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   75.09                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.03                       # Row buffer hit rate for writes
+system.physmem.avgGap                     23828373.78                       # Average gap between requests
+system.physmem.pageHitRate                      73.92                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 2184439320                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1191906375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                3552658200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               4018150800                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3384693617760                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1306740976245                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29946315984000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34648697732700                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.623145                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49817760765674                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1730415960000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    264967468786                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    272796109326                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 2112120360                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 1152446625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                3795924600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3966356160                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3384694126320                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1300719308715                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29951602820250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34648043103030                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.610412                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49826557272121                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1730416220000                       # Time in different power states
+system.physmem_1.actEnergy                 2097627840                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1144539000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                3784926600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3960109440                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3384693617760                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1304293519080                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29948462876250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34648437215970                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.618118                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49821299610951                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1730415960000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    264000971629                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    269251106549                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
 system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
@@ -370,9 +365,9 @@ system.realview.nvmem.bw_inst_read::total            2                       # I
 system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total               3                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
@@ -380,7 +375,7 @@ system.cf0.dma_write_full_pages                  1666                       # Nu
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -410,66 +405,66 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.cpu0.dtb.walker.walks                   134174                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               134174                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        20899                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        96911                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore           13                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples       134161                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0         134161    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       134161                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples       117823                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 25678.780883                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 22579.177668                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 13711.855097                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535       116916     99.23%     99.23% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071          782      0.66%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607           48      0.04%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143           40      0.03%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679           26      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215            7      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total       117823                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples   4912294556                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     1.048082                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0     -236192296     -4.81%     -4.81% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1     5148486852    104.81%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total   4912294556                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        96912     82.26%     82.26% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M        20899     17.74%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total       117811                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       134174                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.walker.walks                   131570                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               131570                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        20583                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        94968                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore            7                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples       131563                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0         131563    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       131563                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples       115558                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 24585.701552                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 21339.790503                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 14301.317993                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535       114596     99.17%     99.17% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071          825      0.71%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607           55      0.05%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143           40      0.03%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679           25      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215           11      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total       115558                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples   4911919556                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     1.054990                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0     -270104796     -5.50%     -5.50% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1     5182024352    105.50%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total   4911919556                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        94969     82.19%     82.19% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        20583     17.81%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total       115552                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       131570                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       134174                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       117811                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       131570                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       115552                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       117811                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       251985                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       115552                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       247122                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    83610055                       # DTB read hits
-system.cpu0.dtb.read_misses                    101997                       # DTB read misses
-system.cpu0.dtb.write_hits                   76232981                       # DTB write hits
-system.cpu0.dtb.write_misses                    32177                       # DTB write misses
+system.cpu0.dtb.read_hits                    83870325                       # DTB read hits
+system.cpu0.dtb.read_misses                    100143                       # DTB read misses
+system.cpu0.dtb.write_hits                   76256860                       # DTB write hits
+system.cpu0.dtb.write_misses                    31427                       # DTB write misses
 system.cpu0.dtb.flush_tlb                       51828                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              22117                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                    537                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   74001                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_tlb_mva_asid              21293                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                    538                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   73309                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  4744                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                  4917                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    10268                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                83712052                       # DTB read accesses
-system.cpu0.dtb.write_accesses               76265158                       # DTB write accesses
+system.cpu0.dtb.perms_faults                     9888                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                83970468                       # DTB read accesses
+system.cpu0.dtb.write_accesses               76288287                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        159843036                       # DTB hits
-system.cpu0.dtb.misses                         134174                       # DTB misses
-system.cpu0.dtb.accesses                    159977210                       # DTB accesses
-system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.hits                        160127185                       # DTB hits
+system.cpu0.dtb.misses                         131570                       # DTB misses
+system.cpu0.dtb.accesses                    160258755                       # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -499,586 +494,580 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.cpu0.itb.walker.walks                    79618                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong                79618                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2         4423                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3        69406                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples        79618                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0          79618    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        79618                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples        73829                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 28640.046594                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 25708.417232                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 15347.109309                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-32767        36310     49.18%     49.18% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-65535        36530     49.48%     98.66% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-98303          322      0.44%     99.10% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::98304-131071          541      0.73%     99.83% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-163839            9      0.01%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::163840-196607           50      0.07%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-229375           12      0.02%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::229376-262143           20      0.03%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-294911           14      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::294912-327679            7      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-360447            4      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::360448-393215            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-425983            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total        73829                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.cpu0.itb.walker.walks                    77633                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                77633                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2         4406                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        67615                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples        77633                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0          77633    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        77633                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        72021                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 27701.552325                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 24376.545883                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 16846.806682                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535        70875     98.41%     98.41% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071          990      1.37%     99.78% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607           61      0.08%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143           51      0.07%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679           30      0.04%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215            8      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total        72021                       # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walksPending::samples   -294749296                       # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::0     -294749296    100.00%    100.00% # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::total   -294749296                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        69406     94.01%     94.01% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M         4423      5.99%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        73829                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::4K        67615     93.88%     93.88% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M         4406      6.12%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        72021                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        79618                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        79618                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        77633                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        77633                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        73829                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        73829                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       153447                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   446783848                       # ITB inst hits
-system.cpu0.itb.inst_misses                     79618                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        72021                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        72021                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       149654                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   447669719                       # ITB inst hits
+system.cpu0.itb.inst_misses                     77633                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                       51828                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              22117                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                    537                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   55085                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              21293                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                    538                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   53432                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               446863466                       # ITB inst accesses
-system.cpu0.itb.hits                        446783848                       # DTB hits
-system.cpu0.itb.misses                          79618                       # DTB misses
-system.cpu0.itb.accesses                    446863466                       # DTB accesses
-system.cpu0.numPwrStateTransitions              16584                       # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples         8292                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean    5987638231.190425                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev   124545672847.091751                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::underflows         3540     42.69%     42.69% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10         4687     56.52%     99.22% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::5e+10-1e+11            1      0.01%     99.23% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11            5      0.06%     99.29% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11           45      0.54%     99.83% # Distribution of time spent in the clock gated state
+system.cpu0.itb.inst_accesses               447747352                       # ITB inst accesses
+system.cpu0.itb.hits                        447669719                       # DTB hits
+system.cpu0.itb.misses                          77633                       # DTB misses
+system.cpu0.itb.accesses                    447747352                       # DTB accesses
+system.cpu0.numPwrStateTransitions              16472                       # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples         8236                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean    5647358953.626396                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev   114048668982.955048                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows         3496     42.45%     42.45% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10         4676     56.78%     99.22% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::5e+10-1e+11            1      0.01%     99.24% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11            4      0.05%     99.28% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11           45      0.55%     99.83% # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11            1      0.01%     99.84% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11            1      0.01%     99.86% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11            1      0.01%     99.85% # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11            1      0.01%     99.87% # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::7.5e+11-8e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::overflows           10      0.12%    100.00% # Distribution of time spent in the clock gated state
 system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::max_value 5700356716960                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total           8292                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON   2171478662469                       # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 49649496213031                       # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles                     51821531497                       # number of cpu cycles simulated
+system.cpu0.pwrStateClkGateDist::max_value 5700356989224                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total           8236                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON   5309324904433                       # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 46511648342067                       # Cumulative time (in ticks) in various power states
+system.cpu0.numCycles                     51821514544                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   16350                       # number of quiesce instructions executed
-system.cpu0.committedInsts                  446506838                       # Number of instructions committed
-system.cpu0.committedOps                    524620955                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            481485743                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                439185                       # Number of float alu accesses
-system.cpu0.num_func_calls                   26339620                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     68267650                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   481485743                       # number of integer instructions
-system.cpu0.num_fp_insts                       439185                       # number of float instructions
-system.cpu0.num_int_register_reads          703915697                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         382127275                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads              705229                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             378788                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           117675600                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes          117367653                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                    159834987                       # number of memory refs
-system.cpu0.num_load_insts                   83607531                       # Number of load instructions
-system.cpu0.num_store_insts                  76227456                       # Number of store instructions
-system.cpu0.num_idle_cycles              50234015072.883141                       # Number of idle cycles
-system.cpu0.num_busy_cycles              1587516424.116865                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.030634                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.969366                       # Percentage of idle cycles
-system.cpu0.Branches                         99742938                       # Number of branches fetched
+system.cpu0.kern.inst.quiesce                   16340                       # number of quiesce instructions executed
+system.cpu0.committedInsts                  447398457                       # Number of instructions committed
+system.cpu0.committedOps                    525429864                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            482287917                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                434588                       # Number of float alu accesses
+system.cpu0.num_func_calls                   26374142                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     68421724                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   482287917                       # number of integer instructions
+system.cpu0.num_fp_insts                       434588                       # number of float instructions
+system.cpu0.num_int_register_reads          704372154                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         382730581                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads              702801                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes             363748                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads           117948117                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes          117634638                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                    160118732                       # number of memory refs
+system.cpu0.num_load_insts                   83867967                       # Number of load instructions
+system.cpu0.num_store_insts                  76250765                       # Number of store instructions
+system.cpu0.num_idle_cycles              50235171233.913414                       # Number of idle cycles
+system.cpu0.num_busy_cycles              1586343310.086583                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.030612                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.969388                       # Percentage of idle cycles
+system.cpu0.Branches                         99895335                       # Number of branches fetched
 system.cpu0.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                363863642     69.32%     69.32% # Class of executed instruction
-system.cpu0.op_class::IntMult                 1121256      0.21%     69.53% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    48514      0.01%     69.54% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     69.54% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     69.54% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     69.54% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     69.54% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     69.54% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     69.54% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     69.54% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.54% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     69.54% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     69.54% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     69.54% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     69.54% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     69.54% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.54% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     69.54% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.54% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     69.54% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.54% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.54% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.54% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.54% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.54% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc             55488      0.01%     69.55% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.55% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.55% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.55% # Class of executed instruction
-system.cpu0.op_class::MemRead                83607531     15.93%     85.48% # Class of executed instruction
-system.cpu0.op_class::MemWrite               76227456     14.52%    100.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                364386062     69.31%     69.31% # Class of executed instruction
+system.cpu0.op_class::IntMult                 1119710      0.21%     69.52% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    49931      0.01%     69.53% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     69.53% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     69.53% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     69.53% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     69.53% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     69.53% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     69.53% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     69.53% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.53% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     69.53% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     69.53% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     69.53% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     69.53% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     69.53% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.53% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     69.53% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.53% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     69.53% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.53% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.53% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.53% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.53% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.53% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc             52613      0.01%     69.54% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.54% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.54% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.54% # Class of executed instruction
+system.cpu0.op_class::MemRead                83867967     15.95%     85.50% # Class of executed instruction
+system.cpu0.op_class::MemWrite               76250765     14.50%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 524923888                       # Class of executed instruction
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements         10233133                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.965653                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          310246690                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs         10233645                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            30.316343                       # Average number of references to valid blocks.
+system.cpu0.op_class::total                 525727049                       # Class of executed instruction
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.tags.replacements         10225430                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.965656                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          309996830                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs         10225942                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            30.314746                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle       3504381500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   237.355546                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   274.610106                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.463585                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.536348                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   249.556484                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   262.409172                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.487415                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.512518                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999933                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          415                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           49                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0           49                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          404                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           58                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses       1292621561                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses      1292621561                       # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data     78084246                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     78779688                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total      156863934                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     72276585                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data     72648252                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total     144924837                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       197426                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data       197729                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       395155                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       164722                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu1.data       170823                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       335545                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1869757                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1817939                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      3687696                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2017973                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data      1975667                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      3993640                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    150525553                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data    151598763                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       302124316                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    150722979                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data    151796492                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      302519471                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      2626633                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data      2692297                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      5318930                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1125686                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data      1099795                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      2225481                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       666350                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data       645260                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total      1311610                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       622669                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu1.data       609834                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total      1232503                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       148976                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       158663                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       307639                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data            2                       # number of StoreCondReq misses
+system.cpu0.dcache.tags.tag_accesses       1291585318                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses      1291585318                       # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.ReadReq_hits::cpu0.data     78353332                       # number of ReadReq hits
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+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       165435                       # number of WriteLineReq hits
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+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1850088                       # number of LoadLockedReq hits
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+system.cpu0.dcache.WriteReq_misses::cpu0.data      1113708                       # number of WriteReq misses
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+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       150530                       # number of LoadLockedReq misses
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 system.cpu0.dcache.StoreCondReq_misses::cpu1.data            1                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total            3                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      4374988                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data      4401926                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       8776914                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      5041338                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data      5047186                       # number of overall misses
-system.cpu0.dcache.overall_misses::total     10088524                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  41851762000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  42562196000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  84413958000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  34117734500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  33482014000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  67599748500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  12812675500                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data  12470666000                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total  25283341500                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2198112500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   2331851500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   4529964000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       114000                       # number of StoreCondReq miss cycles
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+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  42239397500                       # number of ReadReq miss cycles
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+system.cpu0.dcache.ReadReq_miss_latency::total  84686043500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  33748047000                       # number of WriteReq miss cycles
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+system.cpu0.dcache.WriteReq_miss_latency::total  66505395500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  12855930500                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data  12465111500                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total  25321042000                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2217899500                       # number of LoadLockedReq miss cycles
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+system.cpu0.dcache.LoadLockedReq_miss_latency::total   4520823500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data        84500                       # number of StoreCondReq miss cycles
 system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data        83000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total       197000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  88782172000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data  88514876000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 177297048000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  88782172000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data  88514876000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 177297048000                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     80710879                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     81471985                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total    162182864                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     73402271                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data     73748047                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total    147150318                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       863776                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       842989                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total      1706765                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       787391                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       780657                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total      1568048                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2018733                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      1976602                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      3995335                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2017975                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      1975668                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      3993643                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    154900541                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data    156000689                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    310901230                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    155764317                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data    156843678                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    312607995                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.032544                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.033046                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.032796                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.015336                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.014913                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.015124                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.771438                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.765443                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.768477                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.790800                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.781180                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.786011                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.073797                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.080271                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.077000                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_latency::total       167500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  88843375000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data  87669106000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 176512481000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  88843375000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data  87669106000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 176512481000                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     80999258                       # number of ReadReq accesses(hits+misses)
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+system.cpu0.dcache.WriteReq_accesses::cpu0.data     73440456                       # number of WriteReq accesses(hits+misses)
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+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       791279                       # number of WriteLineReq accesses(hits+misses)
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+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.032666                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.033023                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.032845                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.015165                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.014843                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.015004                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.771024                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.764375                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.767718                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.790927                       # miss rate for WriteLineReq accesses
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+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.786254                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.075242                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.079071                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.077148                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000001                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000001                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.028244                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.028217                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.028231                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.032365                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.032180                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.032272                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15933.616154                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15808.878441                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 15870.477333                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30308.393726                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 30443.868175                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 30375.342903                       # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 20577.024872                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 20449.279640                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 20513.817411                       # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14754.809500                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14696.882701                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14724.934095                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        57000                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.028251                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.028154                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.028203                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.032314                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.032132                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.032223                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15963.937578                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15855.155723                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 15909.227595                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30302.419485                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 29986.697590                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 30146.083548                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 20541.749222                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 20540.375112                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 20541.072748                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14733.936757                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14681.865417                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14707.365356                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        84500                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        83000                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 65666.666667                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20293.123547                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20108.215358                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 20200.385694                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17610.835060                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17537.470583                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 17574.131558                       # average overall miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        83750                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20258.538522                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20032.215018                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 20145.493937                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17614.373092                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17457.340591                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 17536.027630                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks      7895103                       # number of writebacks
-system.cpu0.dcache.writebacks::total          7895103                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        10951                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data        10880                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total        21831                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data         9894                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data        11327                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total        21221                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        36169                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data        35602                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        71771                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data        20845                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data        22207                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total        43052                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data        20845                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data        22207                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total        43052                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2615682                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2681417                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      5297099                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1115792                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1088468                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      2204260                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       665476                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       644343                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total      1309819                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       622669                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       609834                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total      1232503                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       112807                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       123061                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       235868                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            2                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.writebacks::writebacks      7886218                       # number of writebacks
+system.cpu0.dcache.writebacks::total          7886218                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        10945                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data        12188                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total        23133                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data         9895                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data        11343                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total        21238                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        35225                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data        35643                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        70868                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data        20840                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data        23531                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total        44371                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data        20840                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data        23531                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total        44371                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2634981                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2664963                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      5299944                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1103813                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1081053                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      2184866                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       657436                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       644587                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total      1302023                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       625844                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       606859                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total      1232703                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       115305                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       121212                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       236517                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            1                       # number of StoreCondReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            1                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total            3                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      4354143                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data      4379719                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      8733862                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      5019619                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data      5024062                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total     10043681                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16676                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        17030                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        33706                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        14991                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        18719                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      4364638                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data      4352875                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      8717513                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      5022074                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data      4997462                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total     10019536                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16630                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        17075                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        33705                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        15387                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        18323                       # number of WriteReq MSHR uncacheable
 system.cpu0.dcache.WriteReq_mshr_uncacheable::total        33710                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        31667                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        35749                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        67416                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  38950730500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  39600598000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  78551328500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  32683890500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  32050078500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  64733969000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  10672378000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  10358334500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  21030712500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  12190006500                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  11860832000                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  24050838500                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1508170000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1647856500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   3156026500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       112000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        32017                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        35398                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        67415                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  39320815000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  39467824000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  78788639000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  32324995500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  31332558500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  63657554000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  10585454000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  10489503500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  21074957500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  12230086500                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  11858252500                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  24088339000                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1546592000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1620640000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   3167232000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data        83500                       # number of StoreCondReq MSHR miss cycles
 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data        82000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       194000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  83824627500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  83511508500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 167336136000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  94497005500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  93869843000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 188366848500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3111292000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3121623000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6232915000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3111292000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   3121623000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6232915000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.032408                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.032912                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.032661                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015201                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014759                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014980                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.770427                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.764355                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.767428                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.790800                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.781180                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.786011                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.055880                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.062259                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059036                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       165500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  83875897000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  82658635000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 166534532000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  94461351000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  93148138500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 187609489500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3103960000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3128821500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6232781500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3103960000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   3128821500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6232781500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.032531                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.032873                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.032702                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015030                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014688                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014859                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.769986                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.763295                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.766659                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.790927                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.781493                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.786254                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.057635                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.061103                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059361                       # mshr miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000001                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000001                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028109                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.028075                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.028092                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.032226                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.032032                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.032129                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14891.233147                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14768.533951                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14829.122223                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29292.099692                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29445.127004                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29367.664885                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16037.209456                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16075.808226                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16056.197459                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 19577.024872                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 19449.279640                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 19513.817411                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13369.471753                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13390.566467                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13380.477640                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        56000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028117                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.028003                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.028060                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.032175                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.031976                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.032076                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14922.618038                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14809.895672                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14865.938017                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29284.847615                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28983.369456                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29135.678801                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16101.117067                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16273.216028                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16186.317369                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 19541.749222                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 19540.375112                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 19541.072748                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13413.052339                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13370.293370                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13391.138903                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        83500                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        82000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 64666.666667                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19251.693732                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19067.777750                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19159.466454                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18825.533472                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18684.053461                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18754.762173                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 186573.039098                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 183301.409278                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184920.043909                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 98250.292102                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 87320.568408                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92454.536015                       # average overall mshr uncacheable latency
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements         13781825                       # number of replacements
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        82750                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19217.148593                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18989.434569                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19103.445214                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18809.231206                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18639.088902                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18724.369023                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 186648.226097                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 183239.912152                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184921.569500                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 96947.246775                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 88389.781909                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92453.927168                       # average overall mshr uncacheable latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.tags.replacements         13794841                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          511.891071                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          881366045                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs         13782337                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            63.948955                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      31614405500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   231.253269                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   280.637803                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.451667                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.548121                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.total_refs          880461329                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs         13795353                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            63.823037                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      31612122500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   239.271634                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   272.619438                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.467327                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.532460                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.999787                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          245                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          192                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3            9                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           78                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          211                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          217                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        908930729                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       908930729                       # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst    439927744                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst    441438301                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      881366045                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    439927744                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst    441438301                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       881366045                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    439927744                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst    441438301                       # number of overall hits
-system.cpu0.icache.overall_hits::total      881366045                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      6856104                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst      6926238                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total     13782342                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      6856104                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst      6926238                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total      13782342                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      6856104                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst      6926238                       # number of overall misses
-system.cpu0.icache.overall_misses::total     13782342                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  92096826500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  93000613500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 185097440000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  92096826500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst  93000613500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 185097440000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  92096826500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst  93000613500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 185097440000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    446783848                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst    448364539                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    895148387                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    446783848                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst    448364539                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    895148387                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    446783848                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst    448364539                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    895148387                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.015345                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015448                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.015397                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.015345                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015448                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.015397                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.015345                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015448                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.015397                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13432.822270                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13427.291049                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13430.042586                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13432.822270                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13427.291049                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13430.042586                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13432.822270                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13427.291049                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13430.042586                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        908052045                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       908052045                       # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.cpu0.icache.ReadReq_hits::cpu0.inst    440828036                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst    439633293                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      880461329                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    440828036                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst    439633293                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       880461329                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    440828036                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst    439633293                       # number of overall hits
+system.cpu0.icache.overall_hits::total      880461329                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      6841683                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst      6953675                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total     13795358                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      6841683                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst      6953675                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total      13795358                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      6841683                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst      6953675                       # number of overall misses
+system.cpu0.icache.overall_misses::total     13795358                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  91946479500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  93460380000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 185406859500                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  91946479500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst  93460380000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 185406859500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  91946479500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst  93460380000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 185406859500                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    447669719                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst    446586968                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    894256687                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    447669719                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst    446586968                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    894256687                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    447669719                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst    446586968                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    894256687                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.015283                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015571                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.015427                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.015283                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015571                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.015427                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.015283                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015571                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.015427                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13439.161022                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13440.429701                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13439.800511                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13439.161022                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13440.429701                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13439.800511                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13439.161022                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13440.429701                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13439.800511                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks     13781825                       # number of writebacks
-system.cpu0.icache.writebacks::total         13781825                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6856104                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      6926238                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total     13782342                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      6856104                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst      6926238                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total     13782342                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      6856104                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst      6926238                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total     13782342                       # number of overall MSHR misses
+system.cpu0.icache.writebacks::writebacks     13794841                       # number of writebacks
+system.cpu0.icache.writebacks::total         13794841                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6841683                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      6953675                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total     13795358                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      6841683                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst      6953675                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total     13795358                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      6841683                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst      6953675                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total     13795358                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        25924                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst        17201                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total        43125                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        25924                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst        17201                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total        43125                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  85240722500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  86074375500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 171315098000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  85240722500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  86074375500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 171315098000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  85240722500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  86074375500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 171315098000                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  85104796500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  86506705000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 171611501500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  85104796500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  86506705000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 171611501500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  85104796500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  86506705000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 171611501500                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1959551500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst   1303928500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   3263480000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1959551500                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst   1303928500                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total   3263480000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.015345                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015448                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.015397                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.015345                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015448                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.015397                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.015345                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015448                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.015397                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12432.822270                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12427.291049                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12430.042586                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12432.822270                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12427.291049                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12430.042586                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12432.822270                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12427.291049                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12430.042586                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.015283                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015571                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.015427                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.015283                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015571                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.015427                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.015283                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015571                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.015427                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12439.161022                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12440.429701                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12439.800511                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12439.161022                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12440.429701                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12439.800511                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12439.161022                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12440.429701                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12439.800511                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 75588.315846                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 75805.389222                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 75674.898551                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 75588.315846                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 75805.389222                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 75674.898551                       # average overall mshr uncacheable latency
-system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1108,70 +1097,76 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.cpu1.dtb.walker.walks                   131388                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong               131388                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        20694                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        94767                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore           12                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples       131376                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean     0.304470                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev    84.045560                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-2047       131374    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.walker.walks                   132777                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               132777                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        20416                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        96210                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore           14                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples       132763                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean     0.225967                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev    59.372165                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-2047       132761    100.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::10240-12287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::26624-28671            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total       131376                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples       115473                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 25989.651260                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 22881.227305                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 14446.882730                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535       114392     99.06%     99.06% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071          917      0.79%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607           63      0.05%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143           52      0.05%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679           33      0.03%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215           11      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total       115473                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples   5991401436                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     1.130704                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0     -783101296    -13.07%    -13.07% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1     6774502732    113.07%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total   5991401436                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        94767     82.08%     82.08% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M        20694     17.92%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total       115461                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       131388                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkWaitTime::16384-18431            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total       132763                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples       116640                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 24809.139232                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 21505.913100                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 14394.407415                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-32767        77454     66.40%     66.40% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-65535        38152     32.71%     99.11% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-98303          546      0.47%     99.58% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::98304-131071          345      0.30%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-163839            7      0.01%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::163840-196607           46      0.04%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-229375            7      0.01%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::229376-262143           32      0.03%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-294911           26      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::294912-327679           11      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-360447            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::360448-393215            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-425983            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total       116640                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples  -4577799504                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.827535                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.377784                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0     -789509296     17.25%     17.25% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1    -3788290208     82.75%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total  -4577799504                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        96210     82.49%     82.49% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M        20416     17.51%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total       116626                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       132777                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       131388                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       115461                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       132777                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       116626                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       115461                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total       246849                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       116626                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total       249403                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    84308595                       # DTB read hits
-system.cpu1.dtb.read_misses                    100203                       # DTB read misses
-system.cpu1.dtb.write_hits                   76530288                       # DTB write hits
-system.cpu1.dtb.write_misses                    31185                       # DTB write misses
+system.cpu1.dtb.read_hits                    83913526                       # DTB read hits
+system.cpu1.dtb.read_misses                    101272                       # DTB read misses
+system.cpu1.dtb.write_hits                   76384029                       # DTB write hits
+system.cpu1.dtb.write_misses                    31505                       # DTB write misses
 system.cpu1.dtb.flush_tlb                       51822                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              20910                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                    530                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   73106                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid              21568                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                    527                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   72847                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  4660                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                  4726                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                     9685                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                84408798                       # DTB read accesses
-system.cpu1.dtb.write_accesses               76561473                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    10026                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                84014798                       # DTB read accesses
+system.cpu1.dtb.write_accesses               76415534                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        160838883                       # DTB hits
-system.cpu1.dtb.misses                         131388                       # DTB misses
-system.cpu1.dtb.accesses                    160970271                       # DTB accesses
-system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.hits                        160297555                       # DTB hits
+system.cpu1.dtb.misses                         132777                       # DTB misses
+system.cpu1.dtb.accesses                    160430332                       # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1201,144 +1196,150 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.cpu1.itb.walker.walks                    76510                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong                76510                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2         4384                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        66713                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples        76510                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0          76510    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        76510                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        71097                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 29111.284583                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 26008.835767                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 16533.926039                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535        69890     98.30%     98.30% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071         1057      1.49%     99.79% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607           63      0.09%     99.88% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143           56      0.08%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679           18      0.03%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215            4      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751            6      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        71097                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.cpu1.itb.walker.walks                    78422                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                78422                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2         4294                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        68564                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples        78422                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0          78422    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        78422                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        72858                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 27889.977765                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 24544.855352                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 16997.530464                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-32767        38730     53.16%     53.16% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-65535        32903     45.16%     98.32% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-98303          429      0.59%     98.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::98304-131071          642      0.88%     99.79% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-163839            9      0.01%     99.80% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::163840-196607           58      0.08%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-229375           14      0.02%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::229376-262143           33      0.05%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-294911           12      0.02%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::294912-327679            7      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-360447            5      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::360448-393215            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-425983            3      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::425984-458751            3      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-491519            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        72858                       # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walksPending::samples   -850152296                       # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::0     -850152296    100.00%    100.00% # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::total   -850152296                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        66713     93.83%     93.83% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M         4384      6.17%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        71097                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::4K        68564     94.11%     94.11% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M         4294      5.89%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        72858                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        76510                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total        76510                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        78422                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        78422                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        71097                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        71097                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       147607                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   448364539                       # ITB inst hits
-system.cpu1.itb.inst_misses                     76510                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        72858                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        72858                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       151280                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   446586968                       # ITB inst hits
+system.cpu1.itb.inst_misses                     78422                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                       51822                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              20910                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                    530                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   52840                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              21568                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                    527                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   53690                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               448441049                       # ITB inst accesses
-system.cpu1.itb.hits                        448364539                       # DTB hits
-system.cpu1.itb.misses                          76510                       # DTB misses
-system.cpu1.itb.accesses                    448441049                       # DTB accesses
-system.cpu1.numPwrStateTransitions              16068                       # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples         8034                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean    6192978089.022779                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev   118311828609.490631                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::underflows         3509     43.68%     43.68% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1000-5e+10         4459     55.50%     99.18% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::5e+10-1e+11            4      0.05%     99.23% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11           45      0.56%     99.79% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11            2      0.02%     99.81% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::2.5e+11-3e+11            1      0.01%     99.83% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11            1      0.01%     99.84% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::overflows           13      0.16%    100.00% # Distribution of time spent in the clock gated state
+system.cpu1.itb.inst_accesses               446665390                       # ITB inst accesses
+system.cpu1.itb.hits                        446586968                       # DTB hits
+system.cpu1.itb.misses                          78422                       # DTB misses
+system.cpu1.itb.accesses                    446665390                       # DTB accesses
+system.cpu1.numPwrStateTransitions              16158                       # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples         8079                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean    6172474015.634856                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev   126400173933.037643                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows         3542     43.84%     43.84% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10         4472     55.35%     99.20% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5e+10-1e+11            4      0.05%     99.24% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11           45      0.56%     99.80% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11            2      0.02%     99.83% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::2.5e+11-3e+11            2      0.02%     99.85% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::overflows           12      0.15%    100.00% # Distribution of time spent in the clock gated state
 system.cpu1.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::max_value 3977581604528                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total           8034                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON   2066588908291                       # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 49754385967209                       # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles                     51820418254                       # number of cpu cycles simulated
+system.cpu1.pwrStateClkGateDist::max_value 5966386038488                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total           8079                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON   1953555674186                       # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 49867417572314                       # Cumulative time (in ticks) in various power states
+system.cpu1.numCycles                     51820431949                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu1.committedInsts                  448088743                       # Number of instructions committed
-system.cpu1.committedOps                    526628545                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses            483582453                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                455004                       # Number of float alu accesses
-system.cpu1.num_func_calls                   26546962                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts     68480445                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                   483582453                       # number of integer instructions
-system.cpu1.num_fp_insts                       455004                       # number of float instructions
-system.cpu1.num_int_register_reads          705060671                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes         383633333                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads              735821                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes             380160                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads           117946404                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes          117660346                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                    160831979                       # number of memory refs
-system.cpu1.num_load_insts                   84305574                       # Number of load instructions
-system.cpu1.num_store_insts                  76526405                       # Number of store instructions
-system.cpu1.num_idle_cycles              50231588268.978668                       # Number of idle cycles
-system.cpu1.num_busy_cycles              1588829985.021333                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.030660                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.969340                       # Percentage of idle cycles
-system.cpu1.Branches                        100054364                       # Number of branches fetched
+system.cpu1.committedInsts                  446306314                       # Number of instructions committed
+system.cpu1.committedOps                    524758442                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses            481884827                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                461371                       # Number of float alu accesses
+system.cpu1.num_func_calls                   26537022                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts     68126137                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                   481884827                       # number of integer instructions
+system.cpu1.num_fp_insts                       461371                       # number of float instructions
+system.cpu1.num_int_register_reads          702656955                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes         382236658                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads              740777                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes             397264                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads           117187848                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes          116906080                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                    160291234                       # number of memory refs
+system.cpu1.num_load_insts                   83910548                       # Number of load instructions
+system.cpu1.num_store_insts                  76380686                       # Number of store instructions
+system.cpu1.num_idle_cycles              50237560488.814125                       # Number of idle cycles
+system.cpu1.num_busy_cycles              1582871460.185875                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.030545                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.969455                       # Percentage of idle cycles
+system.cpu1.Branches                         99714086                       # Number of branches fetched
 system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                364882138     69.25%     69.25% # Class of executed instruction
-system.cpu1.op_class::IntMult                 1103160      0.21%     69.46% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    49288      0.01%     69.47% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     69.47% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     69.47% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     69.47% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     69.47% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     69.47% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     69.47% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     69.47% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.47% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     69.47% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     69.47% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     69.47% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     69.47% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     69.47% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.47% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     69.47% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.47% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     69.47% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.47% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.47% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.47% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.47% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.47% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc             54935      0.01%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::MemRead                84305574     16.00%     85.48% # Class of executed instruction
-system.cpu1.op_class::MemWrite               76526405     14.52%    100.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                363557209     69.24%     69.24% # Class of executed instruction
+system.cpu1.op_class::IntMult                 1101804      0.21%     69.45% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    48133      0.01%     69.46% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.46% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc             57875      0.01%     69.47% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.47% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.47% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.47% # Class of executed instruction
+system.cpu1.op_class::MemRead                83910548     15.98%     85.45% # Class of executed instruction
+system.cpu1.op_class::MemWrite               76380686     14.55%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                 526921542                       # Class of executed instruction
-system.iobus.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq                40309                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40309                       # Transaction distribution
+system.cpu1.op_class::total                 525056297                       # Class of executed instruction
+system.iobus.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.iobus.trans_dist::ReadReq                40314                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40314                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
 system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
@@ -1355,11 +1356,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230976                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230976                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230986                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230986                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353760                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353770                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
@@ -1374,16 +1375,16 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334336                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334336                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334376                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334376                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492256                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             42146500                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7492296                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             42149000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               323500                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               324000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer3.occupancy                11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
@@ -1401,75 +1402,75 @@ system.iobus.reqLayer16.occupancy               17000                       # La
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy               11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            25738000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            25704500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            38603500                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            38608500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           568948940                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           568719305                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147736000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147746000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements               115469                       # number of replacements
-system.iocache.tags.tagsinuse               10.457310                       # Cycle average of tags in use
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.replacements               115474                       # number of replacements
+system.iocache.tags.tagsinuse               10.457313                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115485                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115490                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13153887286000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.511180                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.946130                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.219449                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.434133                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13153882422000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.510792                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.946521                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.219424                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.434158                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.653582                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039749                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039749                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
+system.iocache.tags.tag_accesses              1039794                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039794                       # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8824                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8861                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8829                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8866                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide       115488                       # number of demand (read+write) misses
-system.iocache.demand_misses::total            115528                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide       115493                       # number of demand (read+write) misses
+system.iocache.demand_misses::total            115533                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide       115488                       # number of overall misses
-system.iocache.overall_misses::total           115528                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5086000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1592669163                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1597755163                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide       115493                       # number of overall misses
+system.iocache.overall_misses::total           115533                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5103000                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1592841262                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1597944262                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  12771081777                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  12771081777                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5437000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide  14363750940                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  14369187940                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5437000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide  14363750940                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  14369187940                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  12773360043                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  12773360043                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5454000                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide  14366201305                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  14371655305                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5454000                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide  14366201305                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total  14371655305                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8824                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8861                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8829                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8866                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide       115488                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total          115528                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide       115493                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total          115533                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide       115488                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total         115528                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide       115493                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total         115533                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -1483,53 +1484,53 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 180492.878853                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 180313.188466                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137918.918919                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 180410.155397                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 180232.829010                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 119731.884956                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 119731.884956                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       135925                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 124374.402016                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 124378.401253                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       135925                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 124374.402016                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 124378.401253                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         30368                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 119753.244234                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 119753.244234                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet       136350                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 124390.234083                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 124394.374811                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet       136350                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 124390.234083                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 124394.374811                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         30355                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3349                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3247                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.067781                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.348630                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.writebacks::writebacks          106630                       # number of writebacks
 system.iocache.writebacks::total               106630                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8824                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8861                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8829                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8866                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide       115488                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total       115528                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide       115493                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total       115533                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide       115488                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total       115528                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3236000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1151469163                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1154705163                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide       115493                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total       115533                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3253000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1151391262                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1154644262                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7431123166                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   7431123166                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3437000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   8582592329                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   8586029329                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3437000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   8582592329                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   8586029329                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7433322678                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   7433322678                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3454000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   8584713940                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   8588167940                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3454000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   8584713940                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   8588167940                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -1543,591 +1544,594 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130492.878853                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 130313.188466                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87918.918919                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130410.155397                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 130232.829010                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69668.521394                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69668.521394                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85925                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 74315.879823                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 74319.899323                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85925                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 74315.879823                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 74319.899323                       # average overall mshr miss latency
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements                  1307989                       # number of replacements
-system.l2c.tags.tagsinuse                65252.064264                       # Cycle average of tags in use
-system.l2c.tags.total_refs                   44034643                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1371175                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    32.114532                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle               6646395500                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   38392.380157                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   144.452542                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   212.975590                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3457.790228                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     9508.612364                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   156.104056                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   224.227466                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     2866.176081                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data    10289.345780                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.585821                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002204                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.003250                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.052762                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.145090                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002382                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.003421                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.043734                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.157003                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.995667                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023          258                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        62928                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          257                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           36                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          416                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2434                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5412                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        54630                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.003937                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.960205                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                395596143                       # Number of tag accesses
-system.l2c.tags.data_accesses               395596143                       # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.l2c.ReadReq_hits::cpu0.dtb.walker       248480                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker       169318                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker       245899                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker       163828                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                 827525                       # number of ReadReq hits
-system.l2c.WritebackDirty_hits::writebacks      7895103                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total         7895103                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks     13780242                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total        13780242                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data            5072                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data            4937                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               10009                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           827908                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data           804935                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total              1632843                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst       6817014                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst       6887144                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total          13704158                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data      3253717                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data      3311406                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total          6565123                       # number of ReadSharedReq hits
-system.l2c.InvalidateReq_hits::cpu0.data       363022                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::cpu1.data       359819                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::total           722841                       # number of InvalidateReq hits
-system.l2c.demand_hits::cpu0.dtb.walker        248480                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker        169318                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst             6817014                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data             4081625                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker        245899                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker        163828                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst             6887144                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data             4116341                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                22729649                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker       248480                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker       169318                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst            6817014                       # number of overall hits
-system.l2c.overall_hits::cpu0.data            4081625                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker       245899                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker       163828                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst            6887144                       # number of overall hits
-system.l2c.overall_hits::cpu1.data            4116341                       # number of overall hits
-system.l2c.overall_hits::total               22729649                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker         1916                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker         1908                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker         2340                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker         2129                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                 8293                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data         17934                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         17937                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             35871                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data            2                       # number of SCUpgradeReq misses
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69689.142335                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69689.142335                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        86350                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 74331.032530                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 74335.193754                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        86350                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 74331.032530                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 74335.193754                       # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.l2c.tags.replacements                  1313152                       # number of replacements
+system.l2c.tags.tagsinuse                65370.708254                       # Cycle average of tags in use
+system.l2c.tags.total_refs                   46163144                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1376667                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    33.532542                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle               6637701500                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   10009.384485                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker   223.831306                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   257.129416                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3503.499374                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data    24340.454100                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   220.642740                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   259.400016                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     2811.960142                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data    23744.406675                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.152731                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.003415                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.003923                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.053459                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.371406                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.003367                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.003958                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.042907                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.362311                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.997478                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023          266                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        63249                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          266                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           28                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          242                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2          805                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         5995                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        56179                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023     0.004059                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.965103                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                392950064                       # Number of tag accesses
+system.l2c.tags.data_accesses               392950064                       # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.l2c.ReadReq_hits::cpu0.dtb.walker       228515                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker       155195                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker       232922                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker       157807                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                 774439                       # number of ReadReq hits
+system.l2c.WritebackDirty_hits::writebacks      7886218                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total         7886218                       # number of WritebackDirty hits
+system.l2c.WritebackClean_hits::writebacks     13793267                       # number of WritebackClean hits
+system.l2c.WritebackClean_hits::total        13793267                       # number of WritebackClean hits
+system.l2c.UpgradeReq_hits::cpu0.data           13066                       # number of UpgradeReq hits
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-system.l2c.overall_accesses::cpu1.data        4514415                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total           23619326                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.007652                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.011143                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.009426                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.012829                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.009922                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.779536                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.784165                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.781844                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_accesses::total             2                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data      1088826                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data      1065957                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total          2154783                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu0.inst      6841683                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu1.inst      6953675                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::total      13795358                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data      3407722                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data      3430762                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total      6838484                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu0.data       625844                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu1.data       606859                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::total      1232703                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker       230478                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker       157293                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst         6841683                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data         4496548                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker       235270                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker       159960                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst         6953675                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data         4496719                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total            23571626                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker       230478                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker       157293                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst        6841683                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data        4496548                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker       235270                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker       159960                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst        6953675                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data        4496719                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total           23571626                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.008517                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.013338                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.009980                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.013460                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.010935                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.128178                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.129902                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.129043                       # miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.242388                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.244614                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.243487                       # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.005701                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.005644                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.005673                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.041323                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.039844                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.040577                       # miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu0.data     0.416990                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu1.data     0.409972                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::total     0.413518                       # miss rate for InvalidateReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.007652                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.011143                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.005701                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.090294                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.009426                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.012829                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.005644                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.088178                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.037667                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.007652                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.011143                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.005701                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.090294                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.009426                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.012829                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.005644                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.088178                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.037667                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 86887.787056                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 88477.987421                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 86587.179487                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 86828.558008                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 87153.623538                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 14327.367012                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 14610.609355                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 14469.000028                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data        54500                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.243909                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.240947                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.242443                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.005814                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.005824                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.005819                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.041701                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.040840                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.041269                       # miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu0.data     0.415078                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu1.data     0.414965                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::total     0.415022                       # miss rate for InvalidateReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.008517                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.013338                       # miss rate for demand accesses
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+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 87433.134583                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 87921.040409                       # average ReadReq miss latency
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+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 18123.661397                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 17565.558990                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data        82000                       # average SCUpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        80500                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 63166.666667                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 82001.797054                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81983.378667                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 81992.661792                       # average ReadExReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 82910.283960                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 82683.762214                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 82797.017293                       # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 84404.148366                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 84590.812502                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 84496.528165                       # average ReadSharedReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu0.data     0.219529                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu1.data     1.569906                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::total     0.881957                       # average InvalidateReq miss latency
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-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 88477.987421                       # average overall miss latency
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-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 86828.558008                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 82683.762214                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 82883.463879                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 86828.558008                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 82683.762214                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::total 82892.897085                       # average overall miss latency
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+system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 82713.398523                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 82655.847877                       # average ReadCleanReq miss latency
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+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 84507.229879                       # average ReadSharedReq miss latency
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+system.l2c.InvalidateReq_avg_miss_latency::cpu1.data     1.578477                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::total     0.888391                       # average InvalidateReq miss latency
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+system.l2c.overall_avg_miss_latency::cpu1.data 82718.765745                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 82871.542270                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.writebacks::writebacks             1123802                       # number of writebacks
-system.l2c.writebacks::total                  1123802                       # number of writebacks
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         1916                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         1908                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         2340                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         2129                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total            8293                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data        17934                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data        17937                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        35871                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            2                       # number of SCUpgradeReq MSHR misses
+system.l2c.writebacks::writebacks             1124258                       # number of writebacks
+system.l2c.writebacks::total                  1124258                       # number of writebacks
+system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         1963                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         2098                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         2348                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         2153                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total            8562                       # number of ReadReq MSHR misses
+system.l2c.CleanEvict_mshr_misses::writebacks            1                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total            1                       # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         1921                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         1961                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         3882                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            1                       # number of SCUpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data       264878                       # number of ReadExReq MSHR misses
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-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.005644                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.005673                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.041323                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.039844                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.040577                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.416990                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.409972                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::total     0.413518                       # mshr miss rate for InvalidateReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.007652                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.011143                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.005701                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.090294                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.009426                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.012829                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005644                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.088178                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.037667                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.007652                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.011143                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.005701                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.090294                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.009426                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.012829                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005644                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.088178                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.037667                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 76887.787056                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 78477.987421                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76587.179487                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76828.558008                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 77153.623538                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18916.583027                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18919.496014                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18918.039642                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        44500                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.243909                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.240947                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.242443                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.005814                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.005824                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.005819                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.041701                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.040840                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.041269                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.415078                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.414965                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::total     0.415022                       # mshr miss rate for InvalidateReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.008517                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.013338                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.005814                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.090665                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.009980                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.013460                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005824                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.088276                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.037904                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.008517                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.013338                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.005814                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.090665                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.009980                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.013460                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005824                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.088276                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.037904                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 77271.268467                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 78612.488084                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 77433.134583                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 77921.040409                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 77807.696800                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19077.824050                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19017.848037                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19047.527048                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        72000                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        70500                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 53166.666667                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 72001.797054                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71983.378667                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 71992.661792                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72910.283960                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72683.762214                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72797.017293                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 74403.995372                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74590.725350                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 74496.407757                       # average ReadSharedReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 18670.722173                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 18670.205788                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::total 18670.468860                       # average InvalidateReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76887.787056                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78477.987421                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72910.283960                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 72833.398851                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76587.179487                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76828.558008                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72683.762214                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72883.433794                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 72892.859506                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76887.787056                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78477.987421                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72910.283960                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 72833.398851                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76587.179487                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76828.558008                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72683.762214                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72883.433794                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 72892.859506                       # average overall mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        71250                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 72113.209501                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71743.107550                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 71931.252668                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72597.259930                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72713.398523                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72655.847877                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 74539.819731                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74507.090984                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 74523.570805                       # average ReadSharedReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 18669.456913                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 18671.128760                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::total 18670.279848                       # average InvalidateReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77271.268467                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78612.488084                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72597.259930                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 72959.051121                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77433.134583                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 77921.040409                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72713.398523                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72718.716719                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 72871.496473                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77271.268467                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78612.488084                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72597.259930                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 72959.051121                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77433.134583                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 77921.040409                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72713.398523                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72718.716719                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 72871.496473                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63088.315846                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174050.071960                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174124.804570                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63305.389222                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 170778.479154                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 111091.017948                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 170717.481698                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 111090.901991                       # average ReadReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63088.315846                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 91655.635204                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 90442.436830                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63305.389222                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81354.933005                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 77213.287378                       # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests       2973114                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests      1487263                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests         3311                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 82349.313521                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 77212.900308                       # average overall mshr uncacheable latency
+system.membus.snoop_filter.tot_requests       2952008                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests      1460758                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests         3777                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq               76831                       # Transaction distribution
-system.membus.trans_dist::ReadResp             449832                       # Transaction distribution
+system.membus.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadReq               76830                       # Transaction distribution
+system.membus.trans_dist::ReadResp             456752                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33710                       # Transaction distribution
 system.membus.trans_dist::WriteResp             33710                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1230432                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           191908                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            36440                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1230888                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           196616                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4451                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               8                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            524978                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           524978                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        373001                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        616319                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            521854                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           521854                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        379922                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        618256                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6942                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3721926                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      3851630                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237395                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       237395                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4089025                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6940                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3704616                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      3834318                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       236933                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       236933                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4071251                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13884                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    128978144                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    129147994                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7233792                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7233792                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               136381786                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             3125                       # Total snoops (count)
-system.membus.snoopTraffic                     199488                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples           1661282                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.019128                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.136975                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13880                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    129250016                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    129419862                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7203584                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7203584                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               136623446                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             3602                       # Total snoops (count)
+system.membus.snoopTraffic                     230016                       # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples           1635025                       # Request fanout histogram
+system.membus.snoop_fanout::mean             0.019925                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.139743                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 1629505     98.09%     98.09% # Request fanout histogram
-system.membus.snoop_fanout::1                   31777      1.91%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 1602447     98.01%     98.01% # Request fanout histogram
+system.membus.snoop_fanout::1                   32578      1.99%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             1661282                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           106916500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             1635025                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           106891500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               41500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5690500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5673000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          8079257005                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          8054295189                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         4924178426                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         4944826036                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           44658046                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           44675477                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
 system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
 system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
 system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
 system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
 system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
@@ -2170,86 +2174,86 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
 system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests     48659442                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests     24643437                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests         1748                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops           2028                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops         2028                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.snoop_filter.tot_requests     48651794                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests     24630474                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests         1743                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops           2027                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops         2027                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadReq            1290012                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp          21916025                       # Transaction distribution
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
+system.toL2Bus.trans_dist::ReadReq            1286860                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp          21921577                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             33710                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            33710                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty      9018905                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean     13781825                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         2522217                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           45883                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq             3                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          45886                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          2158380                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         2158380                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq      13782342                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      6845459                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq      1260926                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp      1232503                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     41432759                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     30927957                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       796484                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1252515                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              74409715                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   1764279188                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1081608326                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2697464                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      3989080                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total             2852574058                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         1717339                       # Total snoops (count)
-system.toL2Bus.snoopTraffic                  74998872                       # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples         26724704                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.021941                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.146492                       # Request fanout histogram
+system.toL2Bus.trans_dist::WritebackDirty      9010476                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean     13794841                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         2528106                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           30086                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq             2                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          30088                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          2154783                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         2154783                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq      13795358                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      6841623                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq      1261461                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp      1232703                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     41471807                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     30873248                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       776442                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1216589                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              74338086                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   1765945236                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1080533506                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2538024                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      3725984                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total             2852742750                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         1772959                       # Total snoops (count)
+system.toL2Bus.snoopTraffic                  75424744                       # Total snoop traffic (bytes)
+system.toL2Bus.snoop_fanout::samples         26717035                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.021855                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.146208                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0               26138332     97.81%     97.81% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 586372      2.19%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0               26133147     97.81%     97.81% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 583888      2.19%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           26724704                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy        46394070000                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total           26717035                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy        46394041000                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          1633889                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          1620386                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy       20716638000                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy       20736162000                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy       14191518968                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy       14171869470                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         459301000                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy         459189000                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         753880000                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy         750841000                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------